gpio/omap: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kevin Hilman <khilman@linaro.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
parent
4edd7901ee
commit
661553b9c6
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@ -108,12 +108,12 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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u32 l;
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reg += bank->regs->direction;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if (is_input)
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l |= 1 << gpio;
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else
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l &= ~(1 << gpio);
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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bank->context.oe = l;
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}
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@ -132,7 +132,7 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
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bank->context.dataout &= ~l;
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}
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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}
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/* set data out value using mask register */
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@ -142,12 +142,12 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
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u32 gpio_bit = GPIO_BIT(bank, gpio);
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u32 l;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if (enable)
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l |= gpio_bit;
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else
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l &= ~gpio_bit;
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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bank->context.dataout = l;
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}
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@ -155,26 +155,26 @@ static int _get_gpio_datain(struct gpio_bank *bank, int offset)
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{
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void __iomem *reg = bank->base + bank->regs->datain;
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return (__raw_readl(reg) & (1 << offset)) != 0;
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return (readl_relaxed(reg) & (1 << offset)) != 0;
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}
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static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
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{
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void __iomem *reg = bank->base + bank->regs->dataout;
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return (__raw_readl(reg) & (1 << offset)) != 0;
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return (readl_relaxed(reg) & (1 << offset)) != 0;
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}
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static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
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{
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int l = __raw_readl(base + reg);
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int l = readl_relaxed(base + reg);
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if (set)
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l |= mask;
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else
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l &= ~mask;
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__raw_writel(l, base + reg);
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writel_relaxed(l, base + reg);
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}
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static inline void _gpio_dbck_enable(struct gpio_bank *bank)
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@ -183,7 +183,7 @@ static inline void _gpio_dbck_enable(struct gpio_bank *bank)
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clk_enable(bank->dbck);
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bank->dbck_enabled = true;
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__raw_writel(bank->dbck_enable_mask,
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writel_relaxed(bank->dbck_enable_mask,
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bank->base + bank->regs->debounce_en);
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}
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}
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@ -196,7 +196,7 @@ static inline void _gpio_dbck_disable(struct gpio_bank *bank)
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* enabled but the clock is not, GPIO module seems to be unable
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* to detect events and generate interrupts at least on OMAP3.
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*/
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__raw_writel(0, bank->base + bank->regs->debounce_en);
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writel_relaxed(0, bank->base + bank->regs->debounce_en);
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clk_disable(bank->dbck);
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bank->dbck_enabled = false;
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@ -233,10 +233,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
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clk_enable(bank->dbck);
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reg = bank->base + bank->regs->debounce;
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__raw_writel(debounce, reg);
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writel_relaxed(debounce, reg);
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reg = bank->base + bank->regs->debounce_en;
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val = __raw_readl(reg);
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val = readl_relaxed(reg);
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if (debounce)
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val |= l;
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@ -244,7 +244,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
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val &= ~l;
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bank->dbck_enable_mask = val;
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__raw_writel(val, reg);
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writel_relaxed(val, reg);
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clk_disable(bank->dbck);
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/*
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* Enable debounce clock per module.
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@ -283,12 +283,12 @@ static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
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bank->dbck_enable_mask &= ~gpio_bit;
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bank->context.debounce_en &= ~gpio_bit;
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__raw_writel(bank->context.debounce_en,
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writel_relaxed(bank->context.debounce_en,
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bank->base + bank->regs->debounce_en);
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if (!bank->dbck_enable_mask) {
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bank->context.debounce = 0;
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__raw_writel(bank->context.debounce, bank->base +
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writel_relaxed(bank->context.debounce, bank->base +
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bank->regs->debounce);
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clk_disable(bank->dbck);
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bank->dbck_enabled = false;
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@ -311,18 +311,18 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
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trigger & IRQ_TYPE_EDGE_FALLING);
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bank->context.leveldetect0 =
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__raw_readl(bank->base + bank->regs->leveldetect0);
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readl_relaxed(bank->base + bank->regs->leveldetect0);
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bank->context.leveldetect1 =
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__raw_readl(bank->base + bank->regs->leveldetect1);
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readl_relaxed(bank->base + bank->regs->leveldetect1);
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bank->context.risingdetect =
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__raw_readl(bank->base + bank->regs->risingdetect);
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readl_relaxed(bank->base + bank->regs->risingdetect);
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bank->context.fallingdetect =
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__raw_readl(bank->base + bank->regs->fallingdetect);
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readl_relaxed(bank->base + bank->regs->fallingdetect);
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if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
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_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
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bank->context.wake_en =
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__raw_readl(bank->base + bank->regs->wkup_en);
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readl_relaxed(bank->base + bank->regs->wkup_en);
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}
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/* This part needs to be executed always for OMAP{34xx, 44xx} */
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@ -347,8 +347,8 @@ static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
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exit:
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bank->level_mask =
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__raw_readl(bank->base + bank->regs->leveldetect0) |
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__raw_readl(bank->base + bank->regs->leveldetect1);
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readl_relaxed(bank->base + bank->regs->leveldetect0) |
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readl_relaxed(bank->base + bank->regs->leveldetect1);
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}
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#ifdef CONFIG_ARCH_OMAP1
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@ -366,13 +366,13 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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reg += bank->regs->irqctrl;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if ((l >> gpio) & 1)
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l &= ~(1 << gpio);
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else
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l |= 1 << gpio;
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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}
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#else
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static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
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@ -390,7 +390,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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} else if (bank->regs->irqctrl) {
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reg += bank->regs->irqctrl;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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if (trigger & IRQ_TYPE_EDGE_RISING)
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@ -400,7 +400,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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else
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return -EINVAL;
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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} else if (bank->regs->edgectrl1) {
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if (gpio & 0x08)
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reg += bank->regs->edgectrl2;
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@ -408,7 +408,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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reg += bank->regs->edgectrl1;
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gpio &= 0x07;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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l &= ~(3 << (gpio << 1));
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if (trigger & IRQ_TYPE_EDGE_RISING)
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l |= 2 << (gpio << 1);
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@ -418,8 +418,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
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/* Enable wake-up during idle for dynamic tick */
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_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
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bank->context.wake_en =
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__raw_readl(bank->base + bank->regs->wkup_en);
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__raw_writel(l, reg);
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readl_relaxed(bank->base + bank->regs->wkup_en);
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writel_relaxed(l, reg);
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}
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return 0;
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}
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@ -430,17 +430,17 @@ static void _enable_gpio_module(struct gpio_bank *bank, unsigned offset)
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void __iomem *reg = bank->base + bank->regs->pinctrl;
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/* Claim the pin for MPU */
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__raw_writel(__raw_readl(reg) | (1 << offset), reg);
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writel_relaxed(readl_relaxed(reg) | (1 << offset), reg);
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}
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if (bank->regs->ctrl && !BANK_USED(bank)) {
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void __iomem *reg = bank->base + bank->regs->ctrl;
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u32 ctrl;
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ctrl = __raw_readl(reg);
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ctrl = readl_relaxed(reg);
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/* Module is enabled, clocks are not gated */
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ctrl &= ~GPIO_MOD_CTRL_BIT;
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__raw_writel(ctrl, reg);
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writel_relaxed(ctrl, reg);
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bank->context.ctrl = ctrl;
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}
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}
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@ -455,17 +455,17 @@ static void _disable_gpio_module(struct gpio_bank *bank, unsigned offset)
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/* Disable wake-up during idle for dynamic tick */
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_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
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bank->context.wake_en =
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__raw_readl(bank->base + bank->regs->wkup_en);
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readl_relaxed(bank->base + bank->regs->wkup_en);
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}
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if (bank->regs->ctrl && !BANK_USED(bank)) {
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void __iomem *reg = bank->base + bank->regs->ctrl;
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u32 ctrl;
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ctrl = __raw_readl(reg);
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ctrl = readl_relaxed(reg);
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/* Module is disabled, clocks are gated */
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ctrl |= GPIO_MOD_CTRL_BIT;
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__raw_writel(ctrl, reg);
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writel_relaxed(ctrl, reg);
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bank->context.ctrl = ctrl;
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}
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}
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@ -474,7 +474,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
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{
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void __iomem *reg = bank->base + bank->regs->direction;
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return __raw_readl(reg) & mask;
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return readl_relaxed(reg) & mask;
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}
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static int gpio_irq_type(struct irq_data *d, unsigned type)
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@ -538,16 +538,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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void __iomem *reg = bank->base;
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reg += bank->regs->irqstatus;
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__raw_writel(gpio_mask, reg);
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writel_relaxed(gpio_mask, reg);
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/* Workaround for clearing DSP GPIO interrupts to allow retention */
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if (bank->regs->irqstatus2) {
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reg = bank->base + bank->regs->irqstatus2;
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__raw_writel(gpio_mask, reg);
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writel_relaxed(gpio_mask, reg);
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}
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/* Flush posted write for the irq status to avoid spurious interrupts */
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__raw_readl(reg);
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readl_relaxed(reg);
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}
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static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
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@ -562,7 +562,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
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u32 mask = (1 << bank->width) - 1;
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if (bank->regs->irqenable_inv)
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l = ~l;
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l &= mask;
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@ -580,7 +580,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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bank->context.irqenable1 |= gpio_mask;
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} else {
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if (bank->regs->irqenable_inv)
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l &= ~gpio_mask;
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else
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@ -588,7 +588,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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bank->context.irqenable1 = l;
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}
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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}
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static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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@ -602,7 +602,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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bank->context.irqenable1 &= ~gpio_mask;
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} else {
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reg += bank->regs->irqenable;
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l = __raw_readl(reg);
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l = readl_relaxed(reg);
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if (bank->regs->irqenable_inv)
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l |= gpio_mask;
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else
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@ -610,7 +610,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
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bank->context.irqenable1 = l;
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}
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__raw_writel(l, reg);
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writel_relaxed(l, reg);
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}
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static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
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@ -646,7 +646,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
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else
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bank->context.wake_en &= ~gpio_bit;
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__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
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writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
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spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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@ -748,7 +748,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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u32 enabled;
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enabled = _get_gpio_irqbank_mask(bank);
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isr_saved = isr = __raw_readl(isr_reg) & enabled;
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isr_saved = isr = readl_relaxed(isr_reg) & enabled;
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if (bank->level_mask)
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level_mask = bank->level_mask & enabled;
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@ -883,7 +883,7 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
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writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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@ -898,7 +898,7 @@ static int omap_mpuio_resume_noirq(struct device *dev)
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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__raw_writel(bank->context.wake_en, mask_reg);
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writel_relaxed(bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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@ -1011,7 +1011,7 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
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if (called || bank->regs->revision == USHRT_MAX)
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return;
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rev = __raw_readw(bank->base + bank->regs->revision);
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rev = readw_relaxed(bank->base + bank->regs->revision);
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pr_info("OMAP GPIO hardware version %d.%d\n",
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(rev >> 4) & 0x0f, rev & 0x0f);
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@ -1032,20 +1032,20 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
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l = 0xffff;
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if (bank->is_mpuio) {
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__raw_writel(l, bank->base + bank->regs->irqenable);
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writel_relaxed(l, bank->base + bank->regs->irqenable);
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return;
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}
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_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
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_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
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if (bank->regs->debounce_en)
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__raw_writel(0, base + bank->regs->debounce_en);
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writel_relaxed(0, base + bank->regs->debounce_en);
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/* Save OE default value (0xffffffff) in the context */
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bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
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bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
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/* Initialize interface clk ungated, module enabled */
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if (bank->regs->ctrl)
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__raw_writel(0, base + bank->regs->ctrl);
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writel_relaxed(0, base + bank->regs->ctrl);
|
||||
|
||||
bank->dbck = clk_get(bank->dev, "dbclk");
|
||||
if (IS_ERR(bank->dbck))
|
||||
|
@ -1282,11 +1282,11 @@ static int omap_gpio_runtime_suspend(struct device *dev)
|
|||
*/
|
||||
wake_low = bank->context.leveldetect0 & bank->context.wake_en;
|
||||
if (wake_low)
|
||||
__raw_writel(wake_low | bank->context.fallingdetect,
|
||||
writel_relaxed(wake_low | bank->context.fallingdetect,
|
||||
bank->base + bank->regs->fallingdetect);
|
||||
wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
|
||||
if (wake_hi)
|
||||
__raw_writel(wake_hi | bank->context.risingdetect,
|
||||
writel_relaxed(wake_hi | bank->context.risingdetect,
|
||||
bank->base + bank->regs->risingdetect);
|
||||
|
||||
if (!bank->enabled_non_wakeup_gpios)
|
||||
|
@ -1301,7 +1301,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
|
|||
* non-wakeup GPIOs. Otherwise spurious IRQs will be
|
||||
* generated. See OMAP2420 Errata item 1.101.
|
||||
*/
|
||||
bank->saved_datain = __raw_readl(bank->base +
|
||||
bank->saved_datain = readl_relaxed(bank->base +
|
||||
bank->regs->datain);
|
||||
l1 = bank->context.fallingdetect;
|
||||
l2 = bank->context.risingdetect;
|
||||
|
@ -1309,8 +1309,8 @@ static int omap_gpio_runtime_suspend(struct device *dev)
|
|||
l1 &= ~bank->enabled_non_wakeup_gpios;
|
||||
l2 &= ~bank->enabled_non_wakeup_gpios;
|
||||
|
||||
__raw_writel(l1, bank->base + bank->regs->fallingdetect);
|
||||
__raw_writel(l2, bank->base + bank->regs->risingdetect);
|
||||
writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
|
||||
writel_relaxed(l2, bank->base + bank->regs->risingdetect);
|
||||
|
||||
bank->workaround_enabled = true;
|
||||
|
||||
|
@ -1358,9 +1358,9 @@ static int omap_gpio_runtime_resume(struct device *dev)
|
|||
* generate a PRCM wakeup. Here we restore the
|
||||
* pre-runtime_suspend() values for edge triggering.
|
||||
*/
|
||||
__raw_writel(bank->context.fallingdetect,
|
||||
writel_relaxed(bank->context.fallingdetect,
|
||||
bank->base + bank->regs->fallingdetect);
|
||||
__raw_writel(bank->context.risingdetect,
|
||||
writel_relaxed(bank->context.risingdetect,
|
||||
bank->base + bank->regs->risingdetect);
|
||||
|
||||
if (bank->loses_context) {
|
||||
|
@ -1382,7 +1382,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
l = __raw_readl(bank->base + bank->regs->datain);
|
||||
l = readl_relaxed(bank->base + bank->regs->datain);
|
||||
|
||||
/*
|
||||
* Check if any of the non-wakeup interrupt GPIOs have changed
|
||||
|
@ -1412,24 +1412,24 @@ static int omap_gpio_runtime_resume(struct device *dev)
|
|||
if (gen) {
|
||||
u32 old0, old1;
|
||||
|
||||
old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
|
||||
old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
|
||||
old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
|
||||
old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
|
||||
|
||||
if (!bank->regs->irqstatus_raw0) {
|
||||
__raw_writel(old0 | gen, bank->base +
|
||||
writel_relaxed(old0 | gen, bank->base +
|
||||
bank->regs->leveldetect0);
|
||||
__raw_writel(old1 | gen, bank->base +
|
||||
writel_relaxed(old1 | gen, bank->base +
|
||||
bank->regs->leveldetect1);
|
||||
}
|
||||
|
||||
if (bank->regs->irqstatus_raw0) {
|
||||
__raw_writel(old0 | l, bank->base +
|
||||
writel_relaxed(old0 | l, bank->base +
|
||||
bank->regs->leveldetect0);
|
||||
__raw_writel(old1 | l, bank->base +
|
||||
writel_relaxed(old1 | l, bank->base +
|
||||
bank->regs->leveldetect1);
|
||||
}
|
||||
__raw_writel(old0, bank->base + bank->regs->leveldetect0);
|
||||
__raw_writel(old1, bank->base + bank->regs->leveldetect1);
|
||||
writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
|
||||
writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
|
||||
}
|
||||
|
||||
bank->workaround_enabled = false;
|
||||
|
@ -1471,55 +1471,55 @@ static void omap_gpio_init_context(struct gpio_bank *p)
|
|||
struct omap_gpio_reg_offs *regs = p->regs;
|
||||
void __iomem *base = p->base;
|
||||
|
||||
p->context.ctrl = __raw_readl(base + regs->ctrl);
|
||||
p->context.oe = __raw_readl(base + regs->direction);
|
||||
p->context.wake_en = __raw_readl(base + regs->wkup_en);
|
||||
p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0);
|
||||
p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1);
|
||||
p->context.risingdetect = __raw_readl(base + regs->risingdetect);
|
||||
p->context.fallingdetect = __raw_readl(base + regs->fallingdetect);
|
||||
p->context.irqenable1 = __raw_readl(base + regs->irqenable);
|
||||
p->context.irqenable2 = __raw_readl(base + regs->irqenable2);
|
||||
p->context.ctrl = readl_relaxed(base + regs->ctrl);
|
||||
p->context.oe = readl_relaxed(base + regs->direction);
|
||||
p->context.wake_en = readl_relaxed(base + regs->wkup_en);
|
||||
p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
|
||||
p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
|
||||
p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
|
||||
p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
|
||||
p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
|
||||
p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
|
||||
|
||||
if (regs->set_dataout && p->regs->clr_dataout)
|
||||
p->context.dataout = __raw_readl(base + regs->set_dataout);
|
||||
p->context.dataout = readl_relaxed(base + regs->set_dataout);
|
||||
else
|
||||
p->context.dataout = __raw_readl(base + regs->dataout);
|
||||
p->context.dataout = readl_relaxed(base + regs->dataout);
|
||||
|
||||
p->context_valid = true;
|
||||
}
|
||||
|
||||
static void omap_gpio_restore_context(struct gpio_bank *bank)
|
||||
{
|
||||
__raw_writel(bank->context.wake_en,
|
||||
writel_relaxed(bank->context.wake_en,
|
||||
bank->base + bank->regs->wkup_en);
|
||||
__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
|
||||
__raw_writel(bank->context.leveldetect0,
|
||||
writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
|
||||
writel_relaxed(bank->context.leveldetect0,
|
||||
bank->base + bank->regs->leveldetect0);
|
||||
__raw_writel(bank->context.leveldetect1,
|
||||
writel_relaxed(bank->context.leveldetect1,
|
||||
bank->base + bank->regs->leveldetect1);
|
||||
__raw_writel(bank->context.risingdetect,
|
||||
writel_relaxed(bank->context.risingdetect,
|
||||
bank->base + bank->regs->risingdetect);
|
||||
__raw_writel(bank->context.fallingdetect,
|
||||
writel_relaxed(bank->context.fallingdetect,
|
||||
bank->base + bank->regs->fallingdetect);
|
||||
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
||||
__raw_writel(bank->context.dataout,
|
||||
writel_relaxed(bank->context.dataout,
|
||||
bank->base + bank->regs->set_dataout);
|
||||
else
|
||||
__raw_writel(bank->context.dataout,
|
||||
writel_relaxed(bank->context.dataout,
|
||||
bank->base + bank->regs->dataout);
|
||||
__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
|
||||
writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
|
||||
|
||||
if (bank->dbck_enable_mask) {
|
||||
__raw_writel(bank->context.debounce, bank->base +
|
||||
writel_relaxed(bank->context.debounce, bank->base +
|
||||
bank->regs->debounce);
|
||||
__raw_writel(bank->context.debounce_en,
|
||||
writel_relaxed(bank->context.debounce_en,
|
||||
bank->base + bank->regs->debounce_en);
|
||||
}
|
||||
|
||||
__raw_writel(bank->context.irqenable1,
|
||||
writel_relaxed(bank->context.irqenable1,
|
||||
bank->base + bank->regs->irqenable);
|
||||
__raw_writel(bank->context.irqenable2,
|
||||
writel_relaxed(bank->context.irqenable2,
|
||||
bank->base + bank->regs->irqenable2);
|
||||
}
|
||||
#endif /* CONFIG_PM_RUNTIME */
|
||||
|
|
Loading…
Reference in New Issue