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This is the bulk of the pin control changes for the v5.13 kernel cycle 

Core changes:
 
 - A semantic change to handle pinmux and pinconf in explicit order
   while up until now we depended on the semantic order in the
   device tree. The device tree is a functional programming
   language and does not imply any order, so the right thing is
   for the pin control core to provide these semantics.
 
 - Add a new pinmux-select debugfs file which makes it possible to
   go in and select functions for a pin manually (iteratively, at
   the prompt) for debugging purposes.
 
 - Fixes to gpio regmap handling for a new pin control driver
   making use of regmap-gpio.
 
 - Use octal permissions on debugfs files.
 
 New drivers:
 
 - A massive rewrite of the former custom pin control driver for
   MIPS Broadcom devices to instead use the pin control subsystem.
   New pin control drivers for BCM6345, BCM6328, BCM6358, BCM6362,
   BCM6368, BCM63268 and BCM6318 SoC variants are implemented.
 
 - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and
   PMR735B in the Qualcomm PMIC GPIO driver. Also the two GPIOs
   on PM8008 are supported.
 
 - Support for the Rockchip RK3568/RK3566 pin controller.
 
 - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and
   X2000.
 
 - Support for Mediatek MTK8195.
 
 - Add a new Xilinx ZynqMP pin control driver.
 
 Driver improvements and non-urgent fixes:
 
 - Modularization and improvements of the Rockchip drivers.
 
 - Some new pins added to the description of new Renesas SoCs.
 
 - Clarifications of the GPIO base calculation in the Intel driver.
 
 - Fix the function names for the MPP54 and MPP55 pins in the Armada
   CP110 pin controller.
 
 - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.
 
 - Support for ACPI probing of the Qualcomm SC8180x.
 
 - Fix interrupt clear status on rockchip
 
 - Fix some missing pins on the Ingenic JZ4770, some semantic
   fixes for the behaviour of the Ingenic pin controller.
   Add DMIC pins for JZ4780, X1000, X1500 and X1830.
 
 - A slew of janitorial like of_node_put() calls.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmCL5sAACgkQQRCzN7AZ
 XXNX5RAAtdPvDrPzzWdeqNLyodnJu/SyeA2xbmsvywrSvgpSx3FojFW9AXY/sr7w
 RuhGGA5KhnrovwiabRKoZ0d0lC/JtKdx5g2o9ePFHDy+7BzFnVacBjL38UftSKy0
 4QpDNJ3zock/XTUgJdaJEsbHhP/N4fOF/SbLpguYzGz7JpybNrZ+2M73yeQSL6uE
 yuhn/AgFMLgWS47nSAH91Yt387+XCEfB75nftXyFSN9GpQ9i3VixWsG3Um/Stoma
 aR7IIknvHdpCrOHH1IKohYcdlOkE7Wh2wHXSJVv26M49Ri5KSXu17lsUknebQ/oq
 UeDYdd/2q/wFjxdEbG2tqinEYHs3e1RPmatVesgyibtYHGwjnSFo/G6UtG4948ii
 1exwBi+0fw58YWLu/z4bhnNtZx6VsOev6mJ5GF7pyYzGIJy3r5J/9KCDzOJEoLom
 YTVmgZRjzJuH/i0rPgyg3lSxlP/pdvdk1YUMlIYN1zWdPnRqj7/q+qaxPOkltqD+
 20NFkvhQuuq+dLn4jtNK9xr2+vIKxIRPClT3D/lAihEPC5MUaFw/+y/V7c1hEJfS
 d1dh5DwgHK7i55/lqLFaXeNNYsmY/SiFecoB8xyFnOJFsHlSHe/6NfjmRhOMUn6V
 IX2GG4CBAzaheIWtN/ub/DcQ1vwA2n9hO5WX+Y3CXkIxXUFPmJY=
 =QrEn
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "There is a lot going on!

  Core changes:

   - A semantic change to handle pinmux and pinconf in explicit order
     while up until now we depended on the semantic order in the device
     tree. The device tree is a functional programming language and does
     not imply any order, so the right thing is for the pin control core
     to provide these semantics.

   - Add a new pinmux-select debugfs file which makes it possible to go
     in and select functions for a pin manually (iteratively, at the
     prompt) for debugging purposes.

   - Fixes to gpio regmap handling for a new pin control driver making
     use of regmap-gpio.

   - Use octal permissions on debugfs files.

  New drivers:

   - A massive rewrite of the former custom pin control driver for MIPS
     Broadcom devices to instead use the pin control subsystem. New pin
     control drivers for BCM6345, BCM6328, BCM6358, BCM6362, BCM6368,
     BCM63268 and BCM6318 SoC variants are implemented.

   - Support for PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B
     in the Qualcomm PMIC GPIO driver. Also the two GPIOs on PM8008 are
     supported.

   - Support for the Rockchip RK3568/RK3566 pin controller.

   - Support for Ingenic JZ4730, JZ4750, JZ4755, JZ4775 and X2000.

   - Support for Mediatek MTK8195.

   - Add a new Xilinx ZynqMP pin control driver.

  Driver improvements and non-urgent fixes:

   - Modularization and improvements of the Rockchip drivers.

   - Some new pins added to the description of new Renesas SoCs.

   - Clarifications of the GPIO base calculation in the Intel driver.

   - Fix the function names for the MPP54 and MPP55 pins in the Armada
     CP110 pin controller.

   - GPIO wakeup interrupt map for Qualcomm SC7280 and SM8350.

   - Support for ACPI probing of the Qualcomm SC8180x.

   - Fix interrupt clear status on rockchip

   - Fix some missing pins on the Ingenic JZ4770, some semantic fixes
     for the behaviour of the Ingenic pin controller. Add DMIC pins for
     JZ4780, X1000, X1500 and X1830.

   - A slew of janitorial like of_node_put() calls"

* tag 'pinctrl-v5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: Add Xilinx ZynqMP pinctrl driver support
  firmware: xilinx: Add pinctrl support
  pinctrl: rockchip: do coding style for mux route struct
  pinctrl: Add PIN_CONFIG_MODE_PWM to enum pin_config_param
  pinctrl: Introduce MODE group in enum pin_config_param
  pinctrl: Keep enum pin_config_param ordered by name
  dt-bindings: pinctrl: Add binding for ZynqMP pinctrl driver
  pinctrl: core: Fix kernel doc string for pin_get_name()
  pinctrl: mediatek: use spin lock in mtk_rmw
  pinctrl: add drive for I2C related pins on MT8195
  pinctrl: add pinctrl driver on mt8195
  dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
  pinctrl: Ingenic: Add pinctrl driver for X2000.
  pinctrl: Ingenic: Add pinctrl driver for JZ4775.
  pinctrl: Ingenic: Add pinctrl driver for JZ4755.
  pinctrl: Ingenic: Add pinctrl driver for JZ4750.
  pinctrl: Ingenic: Add pinctrl driver for JZ4730.
  dt-bindings: pinctrl: Add bindings for new Ingenic SoCs.
  pinctrl: Ingenic: Reformat the code.
  pinctrl: Ingenic: Add DMIC pins support for Ingenic SoCs.
  ...
This commit is contained in:
Linus Torvalds 2021-04-30 13:04:30 -07:00
parent 592fa9532d 8b242ca700
commit 65ec0a7d24
121 changed files with 13663 additions and 1072 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
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@ -142,8 +142,8 @@ mpp50 50 gpio, ge1(rxclk), mss_i2c(sda), spi1(csn0), uart2(txd), uart0(rxd), xg(
mpp51 51 gpio, ge1(rxd0), mss_i2c(sck), spi1(csn1), uart2(rxd), uart0(cts), sdio(pwr10)
mpp52 52 gpio, ge1(rxd1), synce1(clk), synce2(clk), spi1(csn2), uart1(cts), led(clk), pcie(rstoutn), pcie0(clkreq)
mpp53 53 gpio, ge1(rxd2), ptp(clk), spi1(csn3), uart1(rxd), led(stb), sdio(led)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio(card_detect)
mpp54 54 gpio, ge1(rxd3), synce2(clk), ptp(pclk_out), synce1(clk), led(data), sdio(hw_rst), sdio_wp(wr_protect)
mpp55 55 gpio, ge1(rxctl_rxdv), ptp(pulse), sdio(led), sdio_cd(card_detect)
mpp56 56 gpio, tdm(drx), au(i2sdo_spdifo), spi0(clk), uart1(rxd), sata1(present_act), sdio(clk)
mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(present_act), sdio(cmd)
mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio(d0)

46
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt
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@ -1,46 +0,0 @@
Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
Required properties:
- compatible: should be "brcm,bcm6345-gpio"
- reg-names: must contain
"dat" - data register
"dirout" - direction (output) register
- reg: address + size pairs describing the GPIO register sets;
order must correspond with the order of entries in reg-names
- #gpio-cells: must be set to 2. The first cell is the pin number and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a gpio controller.
Optional properties:
- native-endian: use native endian memory.
Examples:
- BCM6338:
gpio: gpio-controller@fffe0407 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0407 1>, <0xfffe040f 1>;
#gpio-cells = <2>;
gpio-controller;
};
- BCM6345:
gpio: gpio-controller@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
#gpio-cells = <2>;
gpio-controller;
};

86
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml Normal file
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6345 GPIO controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description: |+
Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
are the only ones which don't need a pinctrl driver.
BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6345 have 16-bit data and dirout registers, where GPIO state can be read
and/or written, and the direction changed from input to output.
BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data
and dirout registers, where GPIO state can be read and/or written, and the
direction changed from input to output.
properties:
compatible:
enum:
- brcm,bcm6318-gpio
- brcm,bcm6328-gpio
- brcm,bcm6345-gpio
- brcm,bcm6358-gpio
- brcm,bcm6362-gpio
- brcm,bcm6368-gpio
- brcm,bcm63268-gpio
gpio-controller: true
"#gpio-cells":
const: 2
gpio-ranges:
maxItems: 1
native-endian: true
reg:
maxItems: 2
reg-names:
items:
- const: dirout
- const: dat
required:
- compatible
- reg
- reg-names
- gpio-controller
- '#gpio-cells'
additionalProperties: false
examples:
- |
gpio@fffe0406 {
compatible = "brcm,bcm6345-gpio";
reg-names = "dirout", "dat";
reg = <0xfffe0406 2>, <0xfffe040a 2>;
native-endian;
gpio-controller;
#gpio-cells = <2>;
};
- |
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};

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Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml Normal file
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@ -0,0 +1,177 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6318 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6318-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6318-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6318-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6318-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 50>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@10 {
compatible = "brcm,bcm6318-pinctrl";
reg = <0x18 0x10>, <0x54 0x18>;
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "ephy0_spd_led";
pins = "gpio0";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "ephy1_spd_led";
pins = "gpio1";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "ephy2_spd_led";
pins = "gpio2";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "ephy3_spd_led";
pins = "gpio3";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio4";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio5";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio6";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio7";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio8";
};
pinctrl_inet_fail_led: inet_fail_led-pins {
function = "inet_fail_led";
pins = "gpio9";
};
pinctrl_dsl_led: dsl_led-pins {
function = "dsl_led";
pins = "gpio10";
};
pinctrl_post_fail_led: post_fail_led-pins {
function = "post_fail_led";
pins = "gpio11";
};
pinctrl_wlan_wps_led: wlan_wps_led-pins {
function = "wlan_wps_led";
pins = "gpio12";
};
pinctrl_usb_pwron: usb_pwron-pins {
function = "usb_pwron";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio13";
};
pinctrl_usb_active: usb_active-pins {
function = "usb_active";
pins = "gpio40";
};
};
};

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@ -0,0 +1,194 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM63268 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm63268-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@100000c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x100000c0 0x80>;
ranges = <0 0x100000c0 0x80>;
gpio@0 {
compatible = "brcm,bcm63268-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 52>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@10 {
compatible = "brcm,bcm63268-pinctrl";
reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio0";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio1";
};
};
pinctrl_hsspi_cs4: hsspi_cs4-pins {
function = "hsspi_cs4";
pins = "gpio16";
};
pinctrl_hsspi_cs5: hsspi_cs5-pins {
function = "hsspi_cs5";
pins = "gpio17";
};
pinctrl_hsspi_cs6: hsspi_cs6-pins {
function = "hsspi_cs6";
pins = "gpio8";
};
pinctrl_hsspi_cs7: hsspi_cs7-pins {
function = "hsspi_cs7";
pins = "gpio9";
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio18";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio19";
};
};
pinctrl_vreq_clk: vreq_clk-pins {
function = "vreq_clk";
pins = "gpio22";
};
pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
function = "pcie_clkreq_b";
pins = "gpio23";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio30";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio31";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
pinctrl_gpio35_alt: gpio35_alt-pins {
function = "gpio35_alt";
pin = "gpio35";
};
pinctrl_dectpd: dectpd-pins {
function = "dectpd";
group = "dectpd_grp";
};
pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
function = "vdsl_phy_override_0";
group = "vdsl_phy_override_0_grp";
};
pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
function = "vdsl_phy_override_1";
group = "vdsl_phy_override_1_grp";
};
pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
function = "vdsl_phy_override_2";
group = "vdsl_phy_override_2_grp";
};
pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
function = "vdsl_phy_override_3";
group = "vdsl_phy_override_3_grp";
};
pinctrl_dsl_gpio8: dsl_gpio8-pins {
function = "dsl_gpio8";
group = "dsl_gpio8";
};
pinctrl_dsl_gpio9: dsl_gpio9-pins {
function = "dsl_gpio9";
group = "dsl_gpio9";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6328 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6328-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6328-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6328-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6328-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6328-pinctrl";
reg = <0x18 0x10>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio11";
};
pinctrl_pcie_clkreq: pcie_clkreq-pins {
function = "pcie_clkreq";
pins = "gpio16";
};
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "led";
pins = "gpio17";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "led";
pins = "gpio18";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "led";
pins = "gpio19";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "led";
pins = "gpio20";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio25";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio26";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio27";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio28";
};
pinctrl_hsspi_cs1: hsspi_cs1-pins {
function = "hsspi_cs1";
pins = "hsspi_cs1";
};
pinctrl_usb_port1_device: usb_port1_device-pins {
function = "usb_device_port";
pins = "usb_port1";
};
pinctrl_usb_port1_host: usb_port1_host-pins {
function = "usb_host_port";
pins = "usb_port1";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6358 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6358-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6358-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@fffe0080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6358-gpio-sysctl", "syscon", "simple-mfd";
reg = <0xfffe0080 0x80>;
ranges = <0 0xfffe0080 0x80>;
gpio@0 {
compatible = "brcm,bcm6358-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 40>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6358-pinctrl";
reg = <0x18 0x4>;
pinctrl_ebi_cs: ebi_cs-pins {
function = "ebi_cs";
groups = "ebi_cs_grp";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
groups = "uart1_grp";
};
pinctrl_serial_led: serial_led-pins {
function = "serial_led";
groups = "serial_led_grp";
};
pinctrl_legacy_led: legacy_led-pins {
function = "legacy_led";
groups = "legacy_led_grp";
};
pinctrl_led: led-pins {
function = "led";
groups = "led_grp";
};
pinctrl_spi_cs_23: spi_cs-pins {
function = "spi_cs";
groups = "spi_cs_grp";
};
pinctrl_utopia: utopia-pins {
function = "utopia";
groups = "utopia_grp";
};
pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
function = "pwm_syn_clk";
groups = "pwm_syn_clk_grp";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
groups = "sys_irq_grp";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6362 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6362-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6362-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6362-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6362-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 48>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6362-pinctrl";
reg = <0x18 0x10>, <0x38 0x4>;
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio0";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio1";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio2";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio4";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio5";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio6";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio7";
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio8";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio9";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio10";
};
pinctrl_ntr_pulse: ntr_pulse-pins {
function = "ntr_pulse";
pins = "gpio11";
};
pinctrl_uart1_scts: uart1_scts-pins {
function = "uart1_scts";
pins = "gpio12";
};
pinctrl_uart1_srts: uart1_srts-pins {
function = "uart1_srts";
pins = "gpio13";
};
pinctrl_uart1: uart1-pins {
pinctrl_uart1_sdin: uart1_sdin-pins {
function = "uart1_sdin";
pins = "gpio14";
};
pinctrl_uart1_sdout: uart1_sdout-pins {
function = "uart1_sdout";
pins = "gpio15";
};
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio16";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio17";
};
pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
function = "adsl_spi_clk";
pins = "gpio18";
};
pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
function = "adsl_spi_cs";
pins = "gpio19";
};
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio20";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio21";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio22";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio23";
};
pinctrl_ext_irq0: ext_irq0-pins {
function = "ext_irq0";
pins = "gpio24";
};
pinctrl_ext_irq1: ext_irq1-pins {
function = "ext_irq1";
pins = "gpio25";
};
pinctrl_ext_irq2: ext_irq2-pins {
function = "ext_irq2";
pins = "gpio26";
};
pinctrl_ext_irq3: ext_irq3-pins {
function = "ext_irq3";
pins = "gpio27";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Broadcom BCM6368 SoC GPIO system controller which provides a register map
for controlling the GPIO and pins of the SoC.
properties:
"#address-cells": true
"#size-cells": true
compatible:
items:
- const: brcm,bcm6368-gpio-sysctl
- const: syscon
- const: simple-mfd
ranges:
maxItems: 1
reg:
maxItems: 1
patternProperties:
"^gpio@[0-9a-f]+$":
# Child node
type: object
$ref: "../gpio/brcm,bcm6345-gpio.yaml"
description:
GPIO controller for the SoC GPIOs. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
"^pinctrl@[0-9a-f]+$":
# Child node
type: object
$ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml"
description:
Pin controller for the SoC pins. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.
required:
- "#address-cells"
- compatible
- ranges
- reg
- "#size-cells"
additionalProperties: false
examples:
- |
syscon@10000080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
reg = <0x10000080 0x80>;
ranges = <0 0x10000080 0x80>;
gpio@0 {
compatible = "brcm,bcm6368-gpio";
reg-names = "dirout", "dat";
reg = <0x0 0x8>, <0x8 0x8>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 38>;
#gpio-cells = <2>;
};
pinctrl: pinctrl@18 {
compatible = "brcm,bcm6368-pinctrl";
reg = <0x18 0x4>, <0x38 0x4>;
pinctrl_analog_afe_0: analog_afe_0-pins {
function = "analog_afe_0";
pins = "gpio0";
};
pinctrl_analog_afe_1: analog_afe_1-pins {
function = "analog_afe_1";
pins = "gpio1";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio2";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio4";
};
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio5";
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio6";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio7";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio8";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio9";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio10";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio11";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio12";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio14";
};
pinctrl_pci: pci-pins {
pinctrl_pci_req1: pci_req1-pins {
function = "pci_req1";
pins = "gpio16";
};
pinctrl_pci_gnt1: pci_gnt1-pins {
function = "pci_gnt1";
pins = "gpio17";
};
pinctrl_pci_intb: pci_intb-pins {
function = "pci_intb";
pins = "gpio18";
};
pinctrl_pci_req0: pci_req0-pins {
function = "pci_req0";
pins = "gpio19";
};
pinctrl_pci_gnt0: pci_gnt0-pins {
function = "pci_gnt0";
pins = "gpio20";
};
};
pinctrl_pcmcia: pcmcia-pins {
pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
function = "pcmcia_cd1";
pins = "gpio22";
};
pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
function = "pcmcia_cd2";
pins = "gpio23";
};
pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
function = "pcmcia_vs1";
pins = "gpio24";
};
pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
function = "pcmcia_vs2";
pins = "gpio25";
};
};
pinctrl_ebi_cs2: ebi_cs2-pins {
function = "ebi_cs2";
pins = "gpio26";
};
pinctrl_ebi_cs3: ebi_cs3-pins {
function = "ebi_cs3";
pins = "gpio27";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio28";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio29";
};
pinctrl_spi_cs4: spi_cs4-pins {
function = "spi_cs4";
pins = "gpio30";
};
pinctrl_spi_cs5: spi_cs5-pins {
function = "spi_cs5";
pins = "gpio31";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
group = "uart1_grp";
};
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6318 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6318 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6318-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led,
ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led,
serial_led_data, serial_led_clk, inet_act_led, inet_fail_led,
dsl_led, post_fail_led, wlan_wps_led, usb_pwron,
usb_device_led, usb_active ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6318-pinctrl";
reg = <0x18 0x10>, <0x54 0x18>;
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "ephy0_spd_led";
pins = "gpio0";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "ephy1_spd_led";
pins = "gpio1";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "ephy2_spd_led";
pins = "gpio2";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "ephy3_spd_led";
pins = "gpio3";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio4";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio5";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio6";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio7";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio8";
};
pinctrl_inet_fail_led: inet_fail_led-pins {
function = "inet_fail_led";
pins = "gpio9";
};
pinctrl_dsl_led: dsl_led-pins {
function = "dsl_led";
pins = "gpio10";
};
pinctrl_post_fail_led: post_fail_led-pins {
function = "post_fail_led";
pins = "gpio11";
};
pinctrl_wlan_wps_led: wlan_wps_led-pins {
function = "wlan_wps_led";
pins = "gpio12";
};
pinctrl_usb_pwron: usb_pwron-pins {
function = "usb_pwron";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio13";
};
pinctrl_usb_active: usb_active-pins {
function = "usb_active";
pins = "gpio40";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM63268 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm63268-pinctrl
reg:
maxItems: 3
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
nand, gpio35_alt, dectpd, vdsl_phy_override_0,
vdsl_phy_override_1, vdsl_phy_override_2,
vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
pins:
enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
dectpd_grp, vdsl_phy_override_0_grp,
vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@10 {
compatible = "brcm,bcm63268-pinctrl";
reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio0";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio1";
};
};
pinctrl_hsspi_cs4: hsspi_cs4-pins {
function = "hsspi_cs4";
pins = "gpio16";
};
pinctrl_hsspi_cs5: hsspi_cs5-pins {
function = "hsspi_cs5";
pins = "gpio17";
};
pinctrl_hsspi_cs6: hsspi_cs6-pins {
function = "hsspi_cs6";
pins = "gpio8";
};
pinctrl_hsspi_cs7: hsspi_cs7-pins {
function = "hsspi_cs7";
pins = "gpio9";
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio18";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio19";
};
};
pinctrl_vreq_clk: vreq_clk-pins {
function = "vreq_clk";
pins = "gpio22";
};
pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
function = "pcie_clkreq_b";
pins = "gpio23";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio30";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio31";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
pinctrl_gpio35_alt: gpio35_alt-pins {
function = "gpio35_alt";
pin = "gpio35";
};
pinctrl_dectpd: dectpd-pins {
function = "dectpd";
group = "dectpd_grp";
};
pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
function = "vdsl_phy_override_0";
group = "vdsl_phy_override_0_grp";
};
pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
function = "vdsl_phy_override_1";
group = "vdsl_phy_override_1_grp";
};
pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
function = "vdsl_phy_override_2";
group = "vdsl_phy_override_2_grp";
};
pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
function = "vdsl_phy_override_3";
group = "vdsl_phy_override_3_grp";
};
pinctrl_dsl_gpio8: dsl_gpio8-pins {
function = "dsl_gpio8";
group = "dsl_gpio8";
};
pinctrl_dsl_gpio9: dsl_gpio9-pins {
function = "dsl_gpio9";
group = "dsl_gpio9";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6328 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6328 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6328-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,
led, ephy0_act_led, ephy1_act_led, ephy2_act_led,
ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]
pins:
enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,
gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,
usb_port1 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6328-pinctrl";
reg = <0x18 0x10>;
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio6";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio7";
};
};
pinctrl_inet_act_led: inet_act_led-pins {
function = "inet_act_led";
pins = "gpio11";
};
pinctrl_pcie_clkreq: pcie_clkreq-pins {
function = "pcie_clkreq";
pins = "gpio16";
};
pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
function = "led";
pins = "gpio17";
};
pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
function = "led";
pins = "gpio18";
};
pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
function = "led";
pins = "gpio19";
};
pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
function = "led";
pins = "gpio20";
};
pinctrl_ephy0_act_led: ephy0_act_led-pins {
function = "ephy0_act_led";
pins = "gpio25";
};
pinctrl_ephy1_act_led: ephy1_act_led-pins {
function = "ephy1_act_led";
pins = "gpio26";
};
pinctrl_ephy2_act_led: ephy2_act_led-pins {
function = "ephy2_act_led";
pins = "gpio27";
};
pinctrl_ephy3_act_led: ephy3_act_led-pins {
function = "ephy3_act_led";
pins = "gpio28";
};
pinctrl_hsspi_cs1: hsspi_cs1-pins {
function = "hsspi_cs1";
pins = "hsspi_cs1";
};
pinctrl_usb_port1_device: usb_port1_device-pins {
function = "usb_device_port";
pins = "usb_port1";
};
pinctrl_usb_port1_host: usb_port1_host-pins {
function = "usb_host_port";
pins = "usb_port1";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6358 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6358 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6358-pinctrl
reg:
maxItems: 1
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia,
pwm_syn_clk, sys_irq ]
pins:
enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,
led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6358-pinctrl";
reg = <0x18 0x4>;
pinctrl_ebi_cs: ebi_cs-pins {
function = "ebi_cs";
groups = "ebi_cs_grp";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
groups = "uart1_grp";
};
pinctrl_serial_led: serial_led-pins {
function = "serial_led";
groups = "serial_led_grp";
};
pinctrl_legacy_led: legacy_led-pins {
function = "legacy_led";
groups = "legacy_led_grp";
};
pinctrl_led: led-pins {
function = "led";
groups = "led_grp";
};
pinctrl_spi_cs_23: spi_cs-pins {
function = "spi_cs";
groups = "spi_cs_grp";
};
pinctrl_utopia: utopia-pins {
function = "utopia";
groups = "utopia_grp";
};
pinctrl_pwm_syn_clk: pwm_syn_clk-pins {
function = "pwm_syn_clk";
groups = "pwm_syn_clk_grp";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
groups = "sys_irq_grp";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6362 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6362 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6362-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data,
robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1,
inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts,
uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso,
adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led,
ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1,
ext_irq2, ext_irq3, nand ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,
gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6362-pinctrl";
reg = <0x18 0x10>, <0x38 0x4>;
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio0";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio1";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio2";
};
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio4";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio5";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio6";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio7";
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio8";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio9";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio10";
};
pinctrl_ntr_pulse: ntr_pulse-pins {
function = "ntr_pulse";
pins = "gpio11";
};
pinctrl_uart1_scts: uart1_scts-pins {
function = "uart1_scts";
pins = "gpio12";
};
pinctrl_uart1_srts: uart1_srts-pins {
function = "uart1_srts";
pins = "gpio13";
};
pinctrl_uart1: uart1-pins {
pinctrl_uart1_sdin: uart1_sdin-pins {
function = "uart1_sdin";
pins = "gpio14";
};
pinctrl_uart1_sdout: uart1_sdout-pins {
function = "uart1_sdout";
pins = "gpio15";
};
};
pinctrl_adsl_spi: adsl_spi-pins {
pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
function = "adsl_spi_miso";
pins = "gpio16";
};
pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
function = "adsl_spi_mosi";
pins = "gpio17";
};
pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
function = "adsl_spi_clk";
pins = "gpio18";
};
pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
function = "adsl_spi_cs";
pins = "gpio19";
};
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio20";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio21";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio22";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio23";
};
pinctrl_ext_irq0: ext_irq0-pins {
function = "ext_irq0";
pins = "gpio24";
};
pinctrl_ext_irq1: ext_irq1-pins {
function = "ext_irq1";
pins = "gpio25";
};
pinctrl_ext_irq2: ext_irq2-pins {
function = "ext_irq2";
pins = "gpio26";
};
pinctrl_ext_irq3: ext_irq3-pins {
function = "ext_irq3";
pins = "gpio27";
};
pinctrl_nand: nand-pins {
function = "nand";
group = "nand_grp";
};
};

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM6368 pin controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
description:
Bindings for Broadcom's BCM6368 memory-mapped pin controller.
properties:
compatible:
const: brcm,bcm6368-pinctrl
reg:
maxItems: 2
patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
properties:
function:
enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data,
serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led,
ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0,
robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb,
pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1,
pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4,
spi_cs5, uart1 ]
pins:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,
gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,
gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23,
gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,
gpio31, uart1_grp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pinctrl@18 {
compatible = "brcm,bcm6368-pinctrl";
reg = <0x18 0x4>, <0x38 0x4>;
pinctrl_analog_afe_0: analog_afe_0-pins {
function = "analog_afe_0";
pins = "gpio0";
};
pinctrl_analog_afe_1: analog_afe_1-pins {
function = "analog_afe_1";
pins = "gpio1";
};
pinctrl_sys_irq: sys_irq-pins {
function = "sys_irq";
pins = "gpio2";
};
pinctrl_serial_led: serial_led-pins {
pinctrl_serial_led_data: serial_led_data-pins {
function = "serial_led_data";
pins = "gpio3";
};
pinctrl_serial_led_clk: serial_led_clk-pins {
function = "serial_led_clk";
pins = "gpio4";
};
};
pinctrl_inet_led: inet_led-pins {
function = "inet_led";
pins = "gpio5";
};
pinctrl_ephy0_led: ephy0_led-pins {
function = "ephy0_led";
pins = "gpio6";
};
pinctrl_ephy1_led: ephy1_led-pins {
function = "ephy1_led";
pins = "gpio7";
};
pinctrl_ephy2_led: ephy2_led-pins {
function = "ephy2_led";
pins = "gpio8";
};
pinctrl_ephy3_led: ephy3_led-pins {
function = "ephy3_led";
pins = "gpio9";
};
pinctrl_robosw_led_data: robosw_led_data-pins {
function = "robosw_led_data";
pins = "gpio10";
};
pinctrl_robosw_led_clk: robosw_led_clk-pins {
function = "robosw_led_clk";
pins = "gpio11";
};
pinctrl_robosw_led0: robosw_led0-pins {
function = "robosw_led0";
pins = "gpio12";
};
pinctrl_robosw_led1: robosw_led1-pins {
function = "robosw_led1";
pins = "gpio13";
};
pinctrl_usb_device_led: usb_device_led-pins {
function = "usb_device_led";
pins = "gpio14";
};
pinctrl_pci: pci-pins {
pinctrl_pci_req1: pci_req1-pins {
function = "pci_req1";
pins = "gpio16";
};
pinctrl_pci_gnt1: pci_gnt1-pins {
function = "pci_gnt1";
pins = "gpio17";
};
pinctrl_pci_intb: pci_intb-pins {
function = "pci_intb";
pins = "gpio18";
};
pinctrl_pci_req0: pci_req0-pins {
function = "pci_req0";
pins = "gpio19";
};
pinctrl_pci_gnt0: pci_gnt0-pins {
function = "pci_gnt0";
pins = "gpio20";
};
};
pinctrl_pcmcia: pcmcia-pins {
pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
function = "pcmcia_cd1";
pins = "gpio22";
};
pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
function = "pcmcia_cd2";
pins = "gpio23";
};
pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
function = "pcmcia_vs1";
pins = "gpio24";
};
pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
function = "pcmcia_vs2";
pins = "gpio25";
};
};
pinctrl_ebi_cs2: ebi_cs2-pins {
function = "ebi_cs2";
pins = "gpio26";
};
pinctrl_ebi_cs3: ebi_cs3-pins {
function = "ebi_cs3";
pins = "gpio27";
};
pinctrl_spi_cs2: spi_cs2-pins {
function = "spi_cs2";
pins = "gpio28";
};
pinctrl_spi_cs3: spi_cs3-pins {
function = "spi_cs3";
pins = "gpio29";
};
pinctrl_spi_cs4: spi_cs4-pins {
function = "spi_cs4";
pins = "gpio30";
};
pinctrl_spi_cs5: spi_cs5-pins {
function = "spi_cs5";
pins = "gpio31";
};
pinctrl_uart1: uart1-pins {
function = "uart1";
group = "uart1_grp";
};
};

23
Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
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@ -17,10 +17,12 @@ description: >
naming scheme "PxN" where x is a character identifying the GPIO port with
which the pin is associated and N is an integer from 0 to 31 identifying the
pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
pins.
and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
pins. The X2000 contains 5 GPIO ports, PA to PE, for a total of 160 pins.
The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains 6 GPIO
ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO ports,
PA to PG, for a total of 224 pins.
maintainers:
- Paul Cercueil <paul@crapouillou.net>
@ -32,20 +34,28 @@ properties:
compatible:
oneOf:
- enum:
- ingenic,jz4730-pinctrl
- ingenic,jz4740-pinctrl
- ingenic,jz4725b-pinctrl
- ingenic,jz4750-pinctrl
- ingenic,jz4755-pinctrl
- ingenic,jz4760-pinctrl
- ingenic,jz4770-pinctrl
- ingenic,jz4775-pinctrl
- ingenic,jz4780-pinctrl
- ingenic,x1000-pinctrl
- ingenic,x1500-pinctrl
- ingenic,x1830-pinctrl
- ingenic,x2000-pinctrl
- items:
- const: ingenic,jz4760b-pinctrl
- const: ingenic,jz4760-pinctrl
- items:
- const: ingenic,x1000e-pinctrl
- const: ingenic,x1000-pinctrl
- items:
- const: ingenic,x2000e-pinctrl
- const: ingenic,x2000-pinctrl
reg:
maxItems: 1
@ -62,14 +72,19 @@ patternProperties:
properties:
compatible:
enum:
- ingenic,jz4730-gpio
- ingenic,jz4740-gpio
- ingenic,jz4725b-gpio
- ingenic,jz4750-gpio
- ingenic,jz4755-gpio
- ingenic,jz4760-gpio
- ingenic,jz4770-gpio
- ingenic,jz4775-gpio
- ingenic,jz4780-gpio
- ingenic,x1000-gpio
- ingenic,x1500-gpio
- ingenic,x1830-gpio
- ingenic,x2000-gpio
reg:
items:

151
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml Normal file
View File

@ -0,0 +1,151 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8195 Pin Controller
maintainers:
- Sean Wang <sean.wang@mediatek.com>
description: |
The Mediatek's Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8195-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
const: 2
gpio-ranges:
description: gpio valid number range.
maxItems: 1
reg:
description: |
Physical address base for gpio base registers. There are 8 GPIO
physical address base in mt8195.
maxItems: 8
reg-names:
description: |
Gpio base register names.
maxItems: 8
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
An example of using macro:
pincontroller {
/* GPIO0 set as multifunction GPIO0 */
gpio_pin {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
};
/* GPIO8 set as multifunction SDA0 */
i2c0_pin {
pinmux = <PINMUX_GPIO8__FUNC_SDA0>;
};
};
$ref: "pinmux-node.yaml"
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined
as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
drive-strength:
description: |
It can support some arguments which is from 0 to 7. It can only support
2/4/6/8/10/12/14/16mA in mt8195.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8195-pinctrl";
reg = <0x10005000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11eb0000 0x1000>,
<0x11f40000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
"iocfg_br", "iocfg_lm", "iocfg_rb",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 144>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pio-pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
output-low;
};
};

14
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
View File

@ -27,8 +27,15 @@ PMIC's from Qualcomm.
"qcom,pm660l-gpio"
"qcom,pm8150-gpio"
"qcom,pm8150b-gpio"
"qcom,pm8350-gpio"
"qcom,pm8350b-gpio"
"qcom,pm8350c-gpio"
"qcom,pmk8350-gpio"
"qcom,pmr735a-gpio"
"qcom,pmr735b-gpio"
"qcom,pm6150-gpio"
"qcom,pm6150l-gpio"
"qcom,pm8008-gpio"
"qcom,pmx55-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
@ -109,8 +116,15 @@ to specify in a pin configuration subnode:
and gpio8)
gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
gpio1-gpio12 for pm8150l (hole on gpio7)
gpio1-gpio10 for pm8350
gpio1-gpio8 for pm8350b
gpio1-gpio9 for pm8350c
gpio1-gpio4 for pmk8350
gpio1-gpio4 for pmr735a
gpio1-gpio4 for pmr735b
gpio1-gpio10 for pm6150
gpio1-gpio12 for pm6150l
gpio1-gpio2 for pm8008
gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@ -33,6 +33,7 @@ Required properties for iomux controller:
"rockchip,rk3328-pinctrl": for Rockchip RK3328
"rockchip,rk3368-pinctrl": for Rockchip RK3368
"rockchip,rk3399-pinctrl": for Rockchip RK3399
"rockchip,rk3568-pinctrl": for Rockchip RK3568
- rockchip,grf: phandle referencing a syscon providing the
"general register files"

336
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@ -0,0 +1,336 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
ZynqMP's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
properties:
compatible:
const: xlnx,zynqmp-pinctrl
patternProperties:
'^(.*-)?(default|gpio)$':
type: object
patternProperties:
'^mux':
type: object
description:
Pinctrl node's client devices use subnodes for pin muxes,
which in turn use below standard properties.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
can0_1_grp, can0_2_grp, can0_3_grp,
can0_4_grp, can0_5_grp, can0_6_grp,
can0_7_grp, can0_8_grp, can0_9_grp,
can0_10_grp, can0_11_grp, can0_12_grp,
can0_13_grp, can0_14_grp, can0_15_grp,
can0_16_grp, can0_17_grp, can0_18_grp,
can1_0_grp, can1_1_grp, can1_2_grp,
can1_3_grp, can1_4_grp, can1_5_grp,
can1_6_grp, can1_7_grp, can1_8_grp,
can1_9_grp, can1_10_grp, can1_11_grp,
can1_12_grp, can1_13_grp, can1_14_grp,
can1_15_grp, can1_16_grp, can1_17_grp,
can1_18_grp, can1_19_grp, uart0_0_grp,
uart0_1_grp, uart0_2_grp, uart0_3_grp,
uart0_4_grp, uart0_5_grp, uart0_6_grp,
uart0_7_grp, uart0_8_grp, uart0_9_grp,
uart0_10_grp, uart0_11_grp, uart0_12_grp,
uart0_13_grp, uart0_14_grp, uart0_15_grp,
uart0_16_grp, uart0_17_grp, uart0_18_grp,
uart1_0_grp, uart1_1_grp, uart1_2_grp,
uart1_3_grp, uart1_4_grp, uart1_5_grp,
uart1_6_grp, uart1_7_grp, uart1_8_grp,
uart1_9_grp, uart1_10_grp, uart1_11_grp,
uart1_12_grp, uart1_13_grp, uart1_14_grp,
uart1_15_grp, uart1_16_grp, uart1_17_grp,
uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
csu0_0_grp, csu0_1_grp, csu0_2_grp,
csu0_3_grp, csu0_4_grp, csu0_5_grp,
csu0_6_grp, csu0_7_grp, csu0_8_grp,
csu0_9_grp, csu0_10_grp, csu0_11_grp,
dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
trace0_clk_2_grp, testscan0_0_grp]
maxItems: 78
function:
description:
Specify the alternative function to be configured for the
given pin groups.
enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
required:
- groups
- function
additionalProperties: false
'^conf':
type: object
description:
Pinctrl node's client devices use subnodes for pin configurations,
which in turn use the standard properties below.
$ref: pincfg-node.yaml#
properties:
groups:
description:
List of pin groups as mentioned above.
pins:
description:
List of pin names to select in this subnode.
items:
pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
maxItems: 78
bias-pull-up: true
bias-pull-down: true
bias-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
bias-high-impedance: true
low-power-enable: true
low-power-disable: true
slew-rate:
enum: [0, 1]
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.
enum: [2, 4, 8, 12]
power-source:
enum: [0, 1]
oneOf:
- required: [ groups ]
- required: [ pins ]
additionalProperties: false
additionalProperties: false
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
zynqmp_firmware: zynqmp-firmware {
pinctrl0: pinctrl {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp", "uart0_5_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-pull-up;
};
conf-tx {
pins = "MIO19";
bias-disable;
input-schmitt-disable;
};
};
};
};
uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
...

2
Documentation/driver-api/gpio/legacy.rst
View File

@ -461,7 +461,7 @@ pin controller?
This is done by registering "ranges" of pins, which are essentially
cross-reference tables. These are described in
Documentation/driver-api/pinctl.rst
Documentation/driver-api/pin-control.rst
While the pin allocation is totally managed by the pinctrl subsystem,
gpio (under gpiolib) is still maintained by gpio drivers. It may happen

2
Documentation/driver-api/index.rst
View File

@ -62,7 +62,7 @@ available subsections can be seen below.
80211/index
uio-howto
firmware/index
pinctl
pin-control
gpio/index
md/index
media/index

39
Documentation/driver-api/pinctl.rst → Documentation/driver-api/pin-control.rst
View File

@ -1235,7 +1235,7 @@ default state like this::
foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
if (IS_ERR(foo->s)) {
/* FIXME: clean up "foo" here */
return PTR_ERR(s);
return PTR_ERR(foo->s);
}
ret = pinctrl_select_state(foo->s);
@ -1428,3 +1428,40 @@ on the pins defined by group B::
The above has to be done from process context. The reservation of the pins
will be done when the state is activated, so in effect one specific pin
can be used by different functions at different times on a running system.
Debugfs files
=============
These files are created in ``/sys/kernel/debug/pinctrl``:
- ``pinctrl-devices``: prints each pin controller device along with columns to
indicate support for pinmux and pinconf
- ``pinctrl-handles``: prints each configured pin controller handle and the
corresponding pinmux maps
- ``pinctrl-maps``: print all pinctrl maps
A sub-directory is created inside of ``/sys/kernel/debug/pinctrl`` for each pin
controller device containing these files:
- ``pins``: prints a line for each pin registered on the pin controller. The
pinctrl driver may add additional information such as register contents.
- ``gpio-ranges``: print ranges that map gpio lines to pins on the controller
- ``pingroups``: print all pin groups registered on the pin controller
- ``pinconf-pins``: print pin config settings for each pin
- ``pinconf-groups``: print pin config settings per pin group
- ``pinmux-functions``: print each pin function along with the pin groups that
map to the pin function
- ``pinmux-pins``: iterate through all pins and print mux owner, gpio owner
and if the pin is a hog
- ``pinmux-select``: write to this file to activate a pin function for a group::
echo "<group-name function-name>" > pinmux-select

2
MAINTAINERS
View File

@ -14371,7 +14371,7 @@ L: linux-gpio@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
F: Documentation/devicetree/bindings/pinctrl/
F: Documentation/driver-api/pinctl.rst
F: Documentation/driver-api/pin-control.rst
F: drivers/pinctrl/
F: include/linux/pinctrl/

2
arch/arm64/Kconfig.platforms
View File

@ -232,9 +232,7 @@ config ARCH_RENESAS
config ARCH_ROCKCHIP
bool "Rockchip Platforms"
select ARCH_HAS_RESET_CONTROLLER
select GPIOLIB
select PINCTRL
select PINCTRL_ROCKCHIP
select PM
select ROCKCHIP_TIMER
help

114
drivers/firmware/xilinx/zynqmp.c
View File

@ -811,6 +811,120 @@ int zynqmp_pm_fpga_get_status(u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
/**
* zynqmp_pm_pinctrl_request - Request Pin from firmware
* @pin: Pin number to request
*
* This function requests pin from firmware.
*
* Return: Returns status, either success or error+reason.
*/
int zynqmp_pm_pinctrl_request(const u32 pin)
{
return zynqmp_pm_invoke_fn(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_request);
/**
* zynqmp_pm_pinctrl_release - Inform firmware that Pin control is released
* @pin: Pin number to release
*
* This function release pin from firmware.
*
* Return: Returns status, either success or error+reason.
*/
int zynqmp_pm_pinctrl_release(const u32 pin)
{
return zynqmp_pm_invoke_fn(PM_PINCTRL_RELEASE, pin, 0, 0, 0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_release);
/**
* zynqmp_pm_pinctrl_get_function - Read function id set for the given pin
* @pin: Pin number
* @id: Buffer to store function ID
*
* This function provides the function currently set for the given pin.
*
* Return: Returns status, either success or error+reason
*/
int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
if (!id)
return -EINVAL;
ret = zynqmp_pm_invoke_fn(PM_PINCTRL_GET_FUNCTION, pin, 0,
0, 0, ret_payload);
*id = ret_payload[1];
return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_function);
/**
* zynqmp_pm_pinctrl_set_function - Set requested function for the pin
* @pin: Pin number
* @id: Function ID to set
*
* This function sets requested function for the given pin.
*
* Return: Returns status, either success or error+reason.
*/
int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
{
return zynqmp_pm_invoke_fn(PM_PINCTRL_SET_FUNCTION, pin, id,
0, 0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_function);
/**
* zynqmp_pm_pinctrl_get_config - Get configuration parameter for the pin
* @pin: Pin number
* @param: Parameter to get
* @value: Buffer to store parameter value
*
* This function gets requested configuration parameter for the given pin.
*
* Return: Returns status, either success or error+reason.
*/
int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
if (!value)
return -EINVAL;
ret = zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_GET, pin, param,
0, 0, ret_payload);
*value = ret_payload[1];
return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config);
/**
* zynqmp_pm_pinctrl_set_config - Set configuration parameter for the pin
* @pin: Pin number
* @param: Parameter to set
* @value: Parameter value to set
*
* This function sets requested configuration parameter for the given pin.
*
* Return: Returns status, either success or error+reason.
*/
int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
u32 value)
{
return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin,
param, value, 0, NULL);
}
EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);
/**
* zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
* master has initialized its own power management

5
drivers/gpio/gpio-regmap.c
View File

@ -254,6 +254,11 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
chip->names = config->names;
chip->label = config->label ?: dev_name(config->parent);
#if defined(CONFIG_OF_GPIO)
/* gpiolib will use of_node of the parent if chip->of_node is NULL */
chip->of_node = to_of_node(config->fwnode);
#endif /* CONFIG_OF_GPIO */
/*
* If our regmap is fast_io we should probably set can_sleep to false.
* Right now, the regmap doesn't save this property, nor is there any

21
drivers/pinctrl/Kconfig
View File

@ -208,13 +208,18 @@ config PINCTRL_OXNAS
select MFD_SYSCON
config PINCTRL_ROCKCHIP
bool
tristate "Rockchip gpio and pinctrl driver"
depends on ARCH_ROCKCHIP || COMPILE_TEST
depends on OF
select GPIOLIB
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
select MFD_SYSCON
select OF_GPIO
default ARCH_ROCKCHIP
help
This support pinctrl and gpio driver for Rockchip SoCs.
config PINCTRL_SINGLE
tristate "One-register-per-pin type device tree based pinctrl driver"
@ -318,6 +323,20 @@ config PINCTRL_ZYNQ
help
This selects the pinctrl driver for Xilinx Zynq.
config PINCTRL_ZYNQMP
tristate "Pinctrl driver for Xilinx ZynqMP"
depends on ZYNQMP_FIRMWARE
select PINMUX
select GENERIC_PINCONF
default ZYNQMP_FIRMWARE
help
This selects the pinctrl driver for Xilinx ZynqMP platform.
This driver will query the pin information from the firmware
and allow configuring the pins.
Configuration can include the mux function to select on those
pin(s)/group(s), and various pin configuration parameters
such as pull-up, slew rate, etc.
config PINCTRL_INGENIC
bool "Pinctrl driver for the Ingenic JZ47xx SoCs"
default MACH_INGENIC

1
drivers/pinctrl/Makefile
View File

@ -40,6 +40,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o

62
drivers/pinctrl/bcm/Kconfig
View File

@ -29,6 +29,68 @@ config PINCTRL_BCM2835
help
Say Y here to enable the Broadcom BCM2835 GPIO driver.
config PINCTRL_BCM63XX
bool
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GPIOLIB
select GPIO_REGMAP
config PINCTRL_BCM6318
bool "Broadcom BCM6318 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM6318 GPIO driver.
config PINCTRL_BCM6328
bool "Broadcom BCM6328 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM6328 GPIO driver.
config PINCTRL_BCM6358
bool "Broadcom BCM6358 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM6358 GPIO driver.
config PINCTRL_BCM6362
bool "Broadcom BCM6362 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM6362 GPIO driver.
config PINCTRL_BCM6368
bool "Broadcom BCM6368 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM6368 GPIO driver.
config PINCTRL_BCM63268
bool "Broadcom BCM63268 GPIO driver"
depends on (BMIPS_GENERIC || COMPILE_TEST)
depends on OF
select PINCTRL_BCM63XX
default BMIPS_GENERIC
help
Say Y here to enable the Broadcom BCM63268 GPIO driver.
config PINCTRL_IPROC_GPIO
bool "Broadcom iProc GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)

7
drivers/pinctrl/bcm/Makefile
View File

@ -3,6 +3,13 @@
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o

498
drivers/pinctrl/bcm/pinctrl-bcm6318.c Normal file
View File

@ -0,0 +1,498 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6318 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6318_NUM_GPIOS 50
#define BCM6318_NUM_MUX 48
#define BCM6318_MODE_REG 0x18
#define BCM6318_MUX_REG 0x1c
#define BCM6328_MUX_MASK GENMASK(1, 0)
#define BCM6318_PAD_REG 0x54
#define BCM6328_PAD_MASK GENMASK(3, 0)
struct bcm6318_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6318_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned mode_val:1;
unsigned mux_val:2;
};
static const struct pinctrl_pin_desc bcm6318_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
PINCTRL_PIN(48, "gpio48"),
PINCTRL_PIN(49, "gpio49"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
#define BCM6318_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6318_pingroup bcm6318_groups[] = {
BCM6318_GROUP(gpio0),
BCM6318_GROUP(gpio1),
BCM6318_GROUP(gpio2),
BCM6318_GROUP(gpio3),
BCM6318_GROUP(gpio4),
BCM6318_GROUP(gpio5),
BCM6318_GROUP(gpio6),
BCM6318_GROUP(gpio7),
BCM6318_GROUP(gpio8),
BCM6318_GROUP(gpio9),
BCM6318_GROUP(gpio10),
BCM6318_GROUP(gpio11),
BCM6318_GROUP(gpio12),
BCM6318_GROUP(gpio13),
BCM6318_GROUP(gpio14),
BCM6318_GROUP(gpio15),
BCM6318_GROUP(gpio16),
BCM6318_GROUP(gpio17),
BCM6318_GROUP(gpio18),
BCM6318_GROUP(gpio19),
BCM6318_GROUP(gpio20),
BCM6318_GROUP(gpio21),
BCM6318_GROUP(gpio22),
BCM6318_GROUP(gpio23),
BCM6318_GROUP(gpio24),
BCM6318_GROUP(gpio25),
BCM6318_GROUP(gpio26),
BCM6318_GROUP(gpio27),
BCM6318_GROUP(gpio28),
BCM6318_GROUP(gpio29),
BCM6318_GROUP(gpio30),
BCM6318_GROUP(gpio31),
BCM6318_GROUP(gpio32),
BCM6318_GROUP(gpio33),
BCM6318_GROUP(gpio34),
BCM6318_GROUP(gpio35),
BCM6318_GROUP(gpio36),
BCM6318_GROUP(gpio37),
BCM6318_GROUP(gpio38),
BCM6318_GROUP(gpio39),
BCM6318_GROUP(gpio40),
BCM6318_GROUP(gpio41),
BCM6318_GROUP(gpio42),
BCM6318_GROUP(gpio43),
BCM6318_GROUP(gpio44),
BCM6318_GROUP(gpio45),
BCM6318_GROUP(gpio46),
BCM6318_GROUP(gpio47),
BCM6318_GROUP(gpio48),
BCM6318_GROUP(gpio49),
};
/* GPIO_MODE */
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
/* PINMUX_SEL */
static const char * const ephy0_spd_led_groups[] = {
"gpio0",
};
static const char * const ephy1_spd_led_groups[] = {
"gpio1",
};
static const char * const ephy2_spd_led_groups[] = {
"gpio2",
};
static const char * const ephy3_spd_led_groups[] = {
"gpio3",
};
static const char * const ephy0_act_led_groups[] = {
"gpio4",
};
static const char * const ephy1_act_led_groups[] = {
"gpio5",
};
static const char * const ephy2_act_led_groups[] = {
"gpio6",
};
static const char * const ephy3_act_led_groups[] = {
"gpio7",
};
static const char * const serial_led_data_groups[] = {
"gpio6",
};
static const char * const serial_led_clk_groups[] = {
"gpio7",
};
static const char * const inet_act_led_groups[] = {
"gpio8",
};
static const char * const inet_fail_led_groups[] = {
"gpio9",
};
static const char * const dsl_led_groups[] = {
"gpio10",
};
static const char * const post_fail_led_groups[] = {
"gpio11",
};
static const char * const wlan_wps_led_groups[] = {
"gpio12",
};
static const char * const usb_pwron_groups[] = {
"gpio13",
};
static const char * const usb_device_led_groups[] = {
"gpio13",
};
static const char * const usb_active_groups[] = {
"gpio40",
};
#define BCM6318_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mode_val = 1, \
}
#define BCM6318_MUX_FUN(n, mux) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mux_val = mux, \
}
static const struct bcm6318_function bcm6318_funcs[] = {
BCM6318_MODE_FUN(led),
BCM6318_MUX_FUN(ephy0_spd_led, 1),
BCM6318_MUX_FUN(ephy1_spd_led, 1),
BCM6318_MUX_FUN(ephy2_spd_led, 1),
BCM6318_MUX_FUN(ephy3_spd_led, 1),
BCM6318_MUX_FUN(ephy0_act_led, 1),
BCM6318_MUX_FUN(ephy1_act_led, 1),
BCM6318_MUX_FUN(ephy2_act_led, 1),
BCM6318_MUX_FUN(ephy3_act_led, 1),
BCM6318_MUX_FUN(serial_led_data, 3),
BCM6318_MUX_FUN(serial_led_clk, 3),
BCM6318_MUX_FUN(inet_act_led, 1),
BCM6318_MUX_FUN(inet_fail_led, 1),
BCM6318_MUX_FUN(dsl_led, 1),
BCM6318_MUX_FUN(post_fail_led, 1),
BCM6318_MUX_FUN(wlan_wps_led, 1),
BCM6318_MUX_FUN(usb_pwron, 1),
BCM6318_MUX_FUN(usb_device_led, 2),
BCM6318_MUX_FUN(usb_active, 2),
};
static inline unsigned int bcm6318_mux_off(unsigned int pin)
{
return BCM6318_MUX_REG + (pin / 16) * 4;
}
static inline unsigned int bcm6318_pad_off(unsigned int pin)
{
return BCM6318_PAD_REG + (pin / 8) * 4;
}
static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6318_groups);
}
static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6318_groups[group].name;
}
static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm6318_groups[group].pins;
*num_pins = bcm6318_groups[group].num_pins;
return 0;
}
static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6318_funcs);
}
static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6318_funcs[selector].name;
}
static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6318_funcs[selector].groups;
*num_groups = bcm6318_funcs[selector].num_groups;
return 0;
}
static inline void bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,
unsigned int mode, unsigned int mux)
{
if (pin < BCM63XX_BANK_GPIOS)
regmap_update_bits(pc->regs, BCM6318_MODE_REG, BIT(pin),
mode ? BIT(pin) : 0);
if (pin < BCM6318_NUM_MUX)
regmap_update_bits(pc->regs,
bcm6318_mux_off(pin),
BCM6328_MUX_MASK << ((pin % 16) * 2),
mux << ((pin % 16) * 2));
}
static inline void bcm6318_set_pad(struct bcm63xx_pinctrl *pc, unsigned pin,
uint8_t val)
{
regmap_update_bits(pc->regs, bcm6318_pad_off(pin),
BCM6328_PAD_MASK << ((pin % 8) * 4),
val << ((pin % 8) * 4));
}
static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6318_pingroup *pg = &bcm6318_groups[group];
const struct bcm6318_function *f = &bcm6318_funcs[selector];
bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
return 0;
}
static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
if (offset < 13) {
/* GPIOs 0-12 use mux 0 as GPIO function */
bcm6318_rmw_mux(pc, offset, 0, 0);
} else if (offset < 42) {
/* GPIOs 13-41 use mux 3 as GPIO function */
bcm6318_rmw_mux(pc, offset, 0, 3);
bcm6318_set_pad(pc, offset, 0);
}
return 0;
}
static struct pinctrl_ops bcm6318_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6318_pinctrl_get_group_name,
.get_group_pins = bcm6318_pinctrl_get_group_pins,
.get_groups_count = bcm6318_pinctrl_get_group_count,
};
static struct pinmux_ops bcm6318_pmx_ops = {
.get_function_groups = bcm6318_pinctrl_get_groups,
.get_function_name = bcm6318_pinctrl_get_func_name,
.get_functions_count = bcm6318_pinctrl_get_func_count,
.gpio_request_enable = bcm6318_gpio_request_enable,
.set_mux = bcm6318_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6318_soc = {
.ngpios = BCM6318_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6318_pins),
.pctl_ops = &bcm6318_pctl_ops,
.pins = bcm6318_pins,
.pmx_ops = &bcm6318_pmx_ops,
};
static int bcm6318_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6318_soc, NULL);
}
static const struct of_device_id bcm6318_pinctrl_match[] = {
{ .compatible = "brcm,bcm6318-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6318_pinctrl_driver = {
.probe = bcm6318_pinctrl_probe,
.driver = {
.name = "bcm6318-pinctrl",
.of_match_table = bcm6318_pinctrl_match,
},
};
builtin_platform_driver(bcm6318_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm63268.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM63268 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM63268_NUM_GPIOS 52
#define BCM63268_NUM_LEDS 24
#define BCM63268_LED_REG 0x10
#define BCM63268_MODE_REG 0x18
#define BCM63268_CTRL_REG 0x1c
#define BCM63268_BASEMODE_REG 0x38
#define BCM63268_BASEMODE_NAND BIT(2) /* GPIOs 2-7, 24-31 */
#define BCM63268_BASEMODE_GPIO35 BIT(4) /* GPIO 35 */
#define BCM63268_BASEMODE_DECTPD BIT(5) /* GPIOs 8/9 */
#define BCM63268_BASEMODE_VDSL_PHY_0 BIT(6) /* GPIOs 10/11 */
#define BCM63268_BASEMODE_VDSL_PHY_1 BIT(7) /* GPIOs 12/13 */
#define BCM63268_BASEMODE_VDSL_PHY_2 BIT(8) /* GPIOs 24/25 */
#define BCM63268_BASEMODE_VDSL_PHY_3 BIT(9) /* GPIOs 26/27 */
enum bcm63268_pinctrl_reg {
BCM63268_LEDCTRL,
BCM63268_MODE,
BCM63268_CTRL,
BCM63268_BASEMODE,
};
struct bcm63268_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm63268_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
enum bcm63268_pinctrl_reg reg;
uint32_t mask;
};
#define BCM63268_PIN(a, b, basemode) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(basemode) \
}
static const struct pinctrl_pin_desc bcm63268_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
BCM63268_PIN(2, "gpio2", BCM63268_BASEMODE_NAND),
BCM63268_PIN(3, "gpio3", BCM63268_BASEMODE_NAND),
BCM63268_PIN(4, "gpio4", BCM63268_BASEMODE_NAND),
BCM63268_PIN(5, "gpio5", BCM63268_BASEMODE_NAND),
BCM63268_PIN(6, "gpio6", BCM63268_BASEMODE_NAND),
BCM63268_PIN(7, "gpio7", BCM63268_BASEMODE_NAND),
BCM63268_PIN(8, "gpio8", BCM63268_BASEMODE_DECTPD),
BCM63268_PIN(9, "gpio9", BCM63268_BASEMODE_DECTPD),
BCM63268_PIN(10, "gpio10", BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_PIN(11, "gpio11", BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_PIN(12, "gpio12", BCM63268_BASEMODE_VDSL_PHY_1),
BCM63268_PIN(13, "gpio13", BCM63268_BASEMODE_VDSL_PHY_1),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
BCM63268_PIN(24, "gpio24",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_PIN(25, "gpio25",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_PIN(26, "gpio26",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
BCM63268_PIN(27, "gpio27",
BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),
BCM63268_PIN(28, "gpio28", BCM63268_BASEMODE_NAND),
BCM63268_PIN(29, "gpio29", BCM63268_BASEMODE_NAND),
BCM63268_PIN(30, "gpio30", BCM63268_BASEMODE_NAND),
BCM63268_PIN(31, "gpio31", BCM63268_BASEMODE_NAND),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
PINCTRL_PIN(48, "gpio48"),
PINCTRL_PIN(49, "gpio49"),
PINCTRL_PIN(50, "gpio50"),
PINCTRL_PIN(51, "gpio51"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
static unsigned gpio50_pins[] = { 50 };
static unsigned gpio51_pins[] = { 51 };
static unsigned nand_grp_pins[] = {
2, 3, 4, 5, 6, 7, 24,
25, 26, 27, 28, 29, 30, 31,
};
static unsigned dectpd_grp_pins[] = { 8, 9 };
static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };
static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
#define BCM63268_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm63268_pingroup bcm63268_groups[] = {
BCM63268_GROUP(gpio0),
BCM63268_GROUP(gpio1),
BCM63268_GROUP(gpio2),
BCM63268_GROUP(gpio3),
BCM63268_GROUP(gpio4),
BCM63268_GROUP(gpio5),
BCM63268_GROUP(gpio6),
BCM63268_GROUP(gpio7),
BCM63268_GROUP(gpio8),
BCM63268_GROUP(gpio9),
BCM63268_GROUP(gpio10),
BCM63268_GROUP(gpio11),
BCM63268_GROUP(gpio12),
BCM63268_GROUP(gpio13),
BCM63268_GROUP(gpio14),
BCM63268_GROUP(gpio15),
BCM63268_GROUP(gpio16),
BCM63268_GROUP(gpio17),
BCM63268_GROUP(gpio18),
BCM63268_GROUP(gpio19),
BCM63268_GROUP(gpio20),
BCM63268_GROUP(gpio21),
BCM63268_GROUP(gpio22),
BCM63268_GROUP(gpio23),
BCM63268_GROUP(gpio24),
BCM63268_GROUP(gpio25),
BCM63268_GROUP(gpio26),
BCM63268_GROUP(gpio27),
BCM63268_GROUP(gpio28),
BCM63268_GROUP(gpio29),
BCM63268_GROUP(gpio30),
BCM63268_GROUP(gpio31),
BCM63268_GROUP(gpio32),
BCM63268_GROUP(gpio33),
BCM63268_GROUP(gpio34),
BCM63268_GROUP(gpio35),
BCM63268_GROUP(gpio36),
BCM63268_GROUP(gpio37),
BCM63268_GROUP(gpio38),
BCM63268_GROUP(gpio39),
BCM63268_GROUP(gpio40),
BCM63268_GROUP(gpio41),
BCM63268_GROUP(gpio42),
BCM63268_GROUP(gpio43),
BCM63268_GROUP(gpio44),
BCM63268_GROUP(gpio45),
BCM63268_GROUP(gpio46),
BCM63268_GROUP(gpio47),
BCM63268_GROUP(gpio48),
BCM63268_GROUP(gpio49),
BCM63268_GROUP(gpio50),
BCM63268_GROUP(gpio51),
/* multi pin groups */
BCM63268_GROUP(nand_grp),
BCM63268_GROUP(dectpd_grp),
BCM63268_GROUP(vdsl_phy0_grp),
BCM63268_GROUP(vdsl_phy1_grp),
BCM63268_GROUP(vdsl_phy2_grp),
BCM63268_GROUP(vdsl_phy3_grp),
};
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
static const char * const serial_led_clk_groups[] = {
"gpio0",
};
static const char * const serial_led_data_groups[] = {
"gpio1",
};
static const char * const hsspi_cs4_groups[] = {
"gpio16",
};
static const char * const hsspi_cs5_groups[] = {
"gpio17",
};
static const char * const hsspi_cs6_groups[] = {
"gpio8",
};
static const char * const hsspi_cs7_groups[] = {
"gpio9",
};
static const char * const uart1_scts_groups[] = {
"gpio10",
"gpio24",
};
static const char * const uart1_srts_groups[] = {
"gpio11",
"gpio25",
};
static const char * const uart1_sdin_groups[] = {
"gpio12",
"gpio26",
};
static const char * const uart1_sdout_groups[] = {
"gpio13",
"gpio27",
};
static const char * const ntr_pulse_in_groups[] = {
"gpio14",
"gpio28",
};
static const char * const dsl_ntr_pulse_out_groups[] = {
"gpio15",
"gpio29",
};
static const char * const adsl_spi_miso_groups[] = {
"gpio18",
};
static const char * const adsl_spi_mosi_groups[] = {
"gpio19",
};
static const char * const vreg_clk_groups[] = {
"gpio22",
};
static const char * const pcie_clkreq_b_groups[] = {
"gpio23",
};
static const char * const switch_led_clk_groups[] = {
"gpio30",
};
static const char * const switch_led_data_groups[] = {
"gpio31",
};
static const char * const wifi_groups[] = {
"gpio32",
"gpio33",
"gpio34",
"gpio35",
"gpio36",
"gpio37",
"gpio38",
"gpio39",
"gpio40",
"gpio41",
"gpio42",
"gpio43",
"gpio44",
"gpio45",
"gpio46",
"gpio47",
"gpio48",
"gpio49",
"gpio50",
"gpio51",
};
static const char * const nand_groups[] = {
"nand_grp",
};
static const char * const dectpd_groups[] = {
"dectpd_grp",
};
static const char * const vdsl_phy_override_0_groups[] = {
"vdsl_phy_override_0_grp",
};
static const char * const vdsl_phy_override_1_groups[] = {
"vdsl_phy_override_1_grp",
};
static const char * const vdsl_phy_override_2_groups[] = {
"vdsl_phy_override_2_grp",
};
static const char * const vdsl_phy_override_3_groups[] = {
"vdsl_phy_override_3_grp",
};
#define BCM63268_LED_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_LEDCTRL, \
}
#define BCM63268_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_MODE, \
}
#define BCM63268_CTRL_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_CTRL, \
}
#define BCM63268_BASEMODE_FUN(n, val) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM63268_BASEMODE, \
.mask = val, \
}
static const struct bcm63268_function bcm63268_funcs[] = {
BCM63268_LED_FUN(led),
BCM63268_MODE_FUN(serial_led_clk),
BCM63268_MODE_FUN(serial_led_data),
BCM63268_MODE_FUN(hsspi_cs6),
BCM63268_MODE_FUN(hsspi_cs7),
BCM63268_MODE_FUN(uart1_scts),
BCM63268_MODE_FUN(uart1_srts),
BCM63268_MODE_FUN(uart1_sdin),
BCM63268_MODE_FUN(uart1_sdout),
BCM63268_MODE_FUN(ntr_pulse_in),
BCM63268_MODE_FUN(dsl_ntr_pulse_out),
BCM63268_MODE_FUN(hsspi_cs4),
BCM63268_MODE_FUN(hsspi_cs5),
BCM63268_MODE_FUN(adsl_spi_miso),
BCM63268_MODE_FUN(adsl_spi_mosi),
BCM63268_MODE_FUN(vreg_clk),
BCM63268_MODE_FUN(pcie_clkreq_b),
BCM63268_MODE_FUN(switch_led_clk),
BCM63268_MODE_FUN(switch_led_data),
BCM63268_CTRL_FUN(wifi),
BCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),
BCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),
BCM63268_BASEMODE_FUN(vdsl_phy_override_0,
BCM63268_BASEMODE_VDSL_PHY_0),
BCM63268_BASEMODE_FUN(vdsl_phy_override_1,
BCM63268_BASEMODE_VDSL_PHY_1),
BCM63268_BASEMODE_FUN(vdsl_phy_override_2,
BCM63268_BASEMODE_VDSL_PHY_2),
BCM63268_BASEMODE_FUN(vdsl_phy_override_3,
BCM63268_BASEMODE_VDSL_PHY_3),
};
static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm63268_groups);
}
static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm63268_groups[group].name;
}
static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm63268_groups[group].pins;
*num_pins = bcm63268_groups[group].num_pins;
return 0;
}
static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm63268_funcs);
}
static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm63268_funcs[selector].name;
}
static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm63268_funcs[selector].groups;
*num_groups = bcm63268_funcs[selector].num_groups;
return 0;
}
static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
{
const struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];
unsigned int basemode = (unsigned long) desc->drv_data;
unsigned int mask = BIT(bcm63xx_bank_pin(pin));
if (basemode)
regmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,
0);
if (pin < BCM63XX_BANK_GPIOS) {
/* base mode: 0 => gpio, 1 => mux function */
regmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);
/* pins 0-23 might be muxed to led */
if (pin < BCM63268_NUM_LEDS)
regmap_update_bits(pc->regs, BCM63268_LED_REG, mask,
0);
} else if (pin < BCM63268_NUM_GPIOS) {
/* ctrl reg: 0 => wifi function, 1 => gpio */
regmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);
}
}
static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
const struct bcm63268_function *f = &bcm63268_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
bcm63268_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
case BCM63268_LEDCTRL:
reg = BCM63268_LED_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM63268_MODE:
reg = BCM63268_MODE_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM63268_CTRL:
reg = BCM63268_CTRL_REG;
mask = BIT(pg->pins[0]);
val = 0;
break;
case BCM63268_BASEMODE:
reg = BCM63268_BASEMODE_REG;
mask = f->mask;
val = f->mask;
break;
default:
WARN_ON(1);
return -EINVAL;
}
regmap_update_bits(pc->regs, reg, mask, val);
return 0;
}
static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm63268_set_gpio(pc, offset);
return 0;
}
static struct pinctrl_ops bcm63268_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm63268_pinctrl_get_group_name,
.get_group_pins = bcm63268_pinctrl_get_group_pins,
.get_groups_count = bcm63268_pinctrl_get_group_count,
};
static struct pinmux_ops bcm63268_pmx_ops = {
.get_function_groups = bcm63268_pinctrl_get_groups,
.get_function_name = bcm63268_pinctrl_get_func_name,
.get_functions_count = bcm63268_pinctrl_get_func_count,
.gpio_request_enable = bcm63268_gpio_request_enable,
.set_mux = bcm63268_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm63268_soc = {
.ngpios = BCM63268_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm63268_pins),
.pctl_ops = &bcm63268_pctl_ops,
.pins = bcm63268_pins,
.pmx_ops = &bcm63268_pmx_ops,
};
static int bcm63268_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);
}
static const struct of_device_id bcm63268_pinctrl_match[] = {
{ .compatible = "brcm,bcm63268-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm63268_pinctrl_driver = {
.probe = bcm63268_pinctrl_probe,
.driver = {
.name = "bcm63268-pinctrl",
.of_match_table = bcm63268_pinctrl_match,
},
};
builtin_platform_driver(bcm63268_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm6328.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6328 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6328_NUM_GPIOS 32
#define BCM6328_MODE_REG 0x18
#define BCM6328_MUX_HI_REG 0x1c
#define BCM6328_MUX_LO_REG 0x20
#define BCM6328_MUX_OTHER_REG 0x24
#define BCM6328_MUX_MASK GENMASK(1, 0)
struct bcm6328_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6328_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned mode_val:1;
unsigned mux_val:2;
};
static const unsigned int bcm6328_mux[] = {
BCM6328_MUX_LO_REG,
BCM6328_MUX_HI_REG,
BCM6328_MUX_OTHER_REG
};
static const struct pinctrl_pin_desc bcm6328_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
/*
* No idea where they really are; so let's put them according
* to their mux offsets.
*/
PINCTRL_PIN(36, "hsspi_cs1"),
PINCTRL_PIN(38, "usb_p2"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned hsspi_cs1_pins[] = { 36 };
static unsigned usb_port1_pins[] = { 38 };
#define BCM6328_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6328_pingroup bcm6328_groups[] = {
BCM6328_GROUP(gpio0),
BCM6328_GROUP(gpio1),
BCM6328_GROUP(gpio2),
BCM6328_GROUP(gpio3),
BCM6328_GROUP(gpio4),
BCM6328_GROUP(gpio5),
BCM6328_GROUP(gpio6),
BCM6328_GROUP(gpio7),
BCM6328_GROUP(gpio8),
BCM6328_GROUP(gpio9),
BCM6328_GROUP(gpio10),
BCM6328_GROUP(gpio11),
BCM6328_GROUP(gpio12),
BCM6328_GROUP(gpio13),
BCM6328_GROUP(gpio14),
BCM6328_GROUP(gpio15),
BCM6328_GROUP(gpio16),
BCM6328_GROUP(gpio17),
BCM6328_GROUP(gpio18),
BCM6328_GROUP(gpio19),
BCM6328_GROUP(gpio20),
BCM6328_GROUP(gpio21),
BCM6328_GROUP(gpio22),
BCM6328_GROUP(gpio23),
BCM6328_GROUP(gpio24),
BCM6328_GROUP(gpio25),
BCM6328_GROUP(gpio26),
BCM6328_GROUP(gpio27),
BCM6328_GROUP(gpio28),
BCM6328_GROUP(gpio29),
BCM6328_GROUP(gpio30),
BCM6328_GROUP(gpio31),
BCM6328_GROUP(hsspi_cs1),
BCM6328_GROUP(usb_port1),
};
/* GPIO_MODE */
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
/* PINMUX_SEL */
static const char * const serial_led_data_groups[] = {
"gpio6",
};
static const char * const serial_led_clk_groups[] = {
"gpio7",
};
static const char * const inet_act_led_groups[] = {
"gpio11",
};
static const char * const pcie_clkreq_groups[] = {
"gpio16",
};
static const char * const ephy0_act_led_groups[] = {
"gpio25",
};
static const char * const ephy1_act_led_groups[] = {
"gpio26",
};
static const char * const ephy2_act_led_groups[] = {
"gpio27",
};
static const char * const ephy3_act_led_groups[] = {
"gpio28",
};
static const char * const hsspi_cs1_groups[] = {
"hsspi_cs1"
};
static const char * const usb_host_port_groups[] = {
"usb_port1",
};
static const char * const usb_device_port_groups[] = {
"usb_port1",
};
#define BCM6328_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mode_val = 1, \
}
#define BCM6328_MUX_FUN(n, mux) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.mux_val = mux, \
}
static const struct bcm6328_function bcm6328_funcs[] = {
BCM6328_MODE_FUN(led),
BCM6328_MUX_FUN(serial_led_data, 2),
BCM6328_MUX_FUN(serial_led_clk, 2),
BCM6328_MUX_FUN(inet_act_led, 1),
BCM6328_MUX_FUN(pcie_clkreq, 2),
BCM6328_MUX_FUN(ephy0_act_led, 1),
BCM6328_MUX_FUN(ephy1_act_led, 1),
BCM6328_MUX_FUN(ephy2_act_led, 1),
BCM6328_MUX_FUN(ephy3_act_led, 1),
BCM6328_MUX_FUN(hsspi_cs1, 2),
BCM6328_MUX_FUN(usb_host_port, 1),
BCM6328_MUX_FUN(usb_device_port, 2),
};
static inline unsigned int bcm6328_mux_off(unsigned int pin)
{
return bcm6328_mux[pin / 16];
}
static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6328_groups);
}
static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6328_groups[group].name;
}
static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm6328_groups[group].pins;
*num_pins = bcm6328_groups[group].num_pins;
return 0;
}
static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6328_funcs);
}
static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6328_funcs[selector].name;
}
static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6328_funcs[selector].groups;
*num_groups = bcm6328_funcs[selector].num_groups;
return 0;
}
static void bcm6328_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,
unsigned int mode, unsigned int mux)
{
if (pin < BCM6328_NUM_GPIOS)
regmap_update_bits(pc->regs, BCM6328_MODE_REG, BIT(pin),
mode ? BIT(pin) : 0);
regmap_update_bits(pc->regs, bcm6328_mux_off(pin),
BCM6328_MUX_MASK << ((pin % 16) * 2),
mux << ((pin % 16) * 2));
}
static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6328_pingroup *pg = &bcm6328_groups[group];
const struct bcm6328_function *f = &bcm6328_funcs[selector];
bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
return 0;
}
static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm6328_rmw_mux(pc, offset, 0, 0);
return 0;
}
static struct pinctrl_ops bcm6328_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6328_pinctrl_get_group_name,
.get_group_pins = bcm6328_pinctrl_get_group_pins,
.get_groups_count = bcm6328_pinctrl_get_group_count,
};
static struct pinmux_ops bcm6328_pmx_ops = {
.get_function_groups = bcm6328_pinctrl_get_groups,
.get_function_name = bcm6328_pinctrl_get_func_name,
.get_functions_count = bcm6328_pinctrl_get_func_count,
.gpio_request_enable = bcm6328_gpio_request_enable,
.set_mux = bcm6328_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6328_soc = {
.ngpios = BCM6328_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6328_pins),
.pctl_ops = &bcm6328_pctl_ops,
.pins = bcm6328_pins,
.pmx_ops = &bcm6328_pmx_ops,
};
static int bcm6328_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6328_soc, NULL);
}
static const struct of_device_id bcm6328_pinctrl_match[] = {
{ .compatible = "brcm,bcm6328-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6328_pinctrl_driver = {
.probe = bcm6328_pinctrl_probe,
.driver = {
.name = "bcm6328-pinctrl",
.of_match_table = bcm6328_pinctrl_match,
},
};
builtin_platform_driver(bcm6328_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm6358.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6358 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6358_NUM_GPIOS 40
#define BCM6358_MODE_REG 0x18
#define BCM6358_MODE_MUX_NONE 0
#define BCM6358_MODE_MUX_EBI_CS BIT(5)
#define BCM6358_MODE_MUX_UART1 BIT(6)
#define BCM6358_MODE_MUX_SPI_CS BIT(7)
#define BCM6358_MODE_MUX_ASYNC_MODEM BIT(8)
#define BCM6358_MODE_MUX_LEGACY_LED BIT(9)
#define BCM6358_MODE_MUX_SERIAL_LED BIT(10)
#define BCM6358_MODE_MUX_LED BIT(11)
#define BCM6358_MODE_MUX_UTOPIA BIT(12)
#define BCM6358_MODE_MUX_CLKRST BIT(13)
#define BCM6358_MODE_MUX_PWM_SYN_CLK BIT(14)
#define BCM6358_MODE_MUX_SYS_IRQ BIT(15)
struct bcm6358_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
const uint16_t mode_val;
/* non-GPIO function muxes require the gpio direction to be set */
const uint16_t direction;
};
struct bcm6358_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
};
struct bcm6358_priv {
struct regmap_field *overlays;
};
#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(BCM6358_MODE_MUX_##bit1 | \
BCM6358_MODE_MUX_##bit2 | \
BCM6358_MODE_MUX_##bit3), \
}
static const struct pinctrl_pin_desc bcm6358_pins[] = {
BCM6358_GPIO_PIN(0, "gpio0", LED, NONE, NONE),
BCM6358_GPIO_PIN(1, "gpio1", LED, NONE, NONE),
BCM6358_GPIO_PIN(2, "gpio2", LED, NONE, NONE),
BCM6358_GPIO_PIN(3, "gpio3", LED, NONE, NONE),
PINCTRL_PIN(4, "gpio4"),
BCM6358_GPIO_PIN(5, "gpio5", SYS_IRQ, NONE, NONE),
BCM6358_GPIO_PIN(6, "gpio6", SERIAL_LED, NONE, NONE),
BCM6358_GPIO_PIN(7, "gpio7", SERIAL_LED, NONE, NONE),
BCM6358_GPIO_PIN(8, "gpio8", PWM_SYN_CLK, NONE, NONE),
BCM6358_GPIO_PIN(9, "gpio09", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(10, "gpio10", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(11, "gpio11", LEGACY_LED, NONE, NONE),
BCM6358_GPIO_PIN(12, "gpio12", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(13, "gpio13", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(14, "gpio14", LEGACY_LED, ASYNC_MODEM, UTOPIA),
BCM6358_GPIO_PIN(15, "gpio15", LEGACY_LED, ASYNC_MODEM, UTOPIA),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
BCM6358_GPIO_PIN(22, "gpio22", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(23, "gpio23", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(24, "gpio24", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(25, "gpio25", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(26, "gpio26", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(27, "gpio27", UTOPIA, NONE, NONE),
BCM6358_GPIO_PIN(28, "gpio28", UTOPIA, UART1, NONE),
BCM6358_GPIO_PIN(29, "gpio29", UTOPIA, UART1, NONE),
BCM6358_GPIO_PIN(30, "gpio30", UTOPIA, UART1, EBI_CS),
BCM6358_GPIO_PIN(31, "gpio31", UTOPIA, UART1, EBI_CS),
BCM6358_GPIO_PIN(32, "gpio32", SPI_CS, NONE, NONE),
BCM6358_GPIO_PIN(33, "gpio33", SPI_CS, NONE, NONE),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
};
static unsigned ebi_cs_grp_pins[] = { 30, 31 };
static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 };
static unsigned spi_cs_grp_pins[] = { 32, 33 };
static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 };
static unsigned serial_led_grp_pins[] = { 6, 7 };
static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 };
static unsigned led_grp_pins[] = { 0, 1, 2, 3 };
static unsigned utopia_grp_pins[] = {
12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
};
static unsigned pwm_syn_clk_grp_pins[] = { 8 };
static unsigned sys_irq_grp_pins[] = { 5 };
#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
.mode_val = BCM6358_MODE_MUX_##bit, \
.direction = dir, \
}
static const struct bcm6358_pingroup bcm6358_groups[] = {
BCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3),
BCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2),
BCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6),
BCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6),
BCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f),
BCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3),
BCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf),
BCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f),
BCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1),
BCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1),
};
static const char * const ebi_cs_groups[] = {
"ebi_cs_grp"
};
static const char * const uart1_groups[] = {
"uart1_grp"
};
static const char * const spi_cs_2_3_groups[] = {
"spi_cs_2_3_grp"
};
static const char * const async_modem_groups[] = {
"async_modem_grp"
};
static const char * const legacy_led_groups[] = {
"legacy_led_grp",
};
static const char * const serial_led_groups[] = {
"serial_led_grp",
};
static const char * const led_groups[] = {
"led_grp",
};
static const char * const clkrst_groups[] = {
"clkrst_grp",
};
static const char * const pwm_syn_clk_groups[] = {
"pwm_syn_clk_grp",
};
static const char * const sys_irq_groups[] = {
"sys_irq_grp",
};
#define BCM6358_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
}
static const struct bcm6358_function bcm6358_funcs[] = {
BCM6358_FUN(ebi_cs),
BCM6358_FUN(uart1),
BCM6358_FUN(spi_cs_2_3),
BCM6358_FUN(async_modem),
BCM6358_FUN(legacy_led),
BCM6358_FUN(serial_led),
BCM6358_FUN(led),
BCM6358_FUN(clkrst),
BCM6358_FUN(pwm_syn_clk),
BCM6358_FUN(sys_irq),
};
static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6358_groups);
}
static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6358_groups[group].name;
}
static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm6358_groups[group].pins;
*num_pins = bcm6358_groups[group].num_pins;
return 0;
}
static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6358_funcs);
}
static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6358_funcs[selector].name;
}
static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6358_funcs[selector].groups;
*num_groups = bcm6358_funcs[selector].num_groups;
return 0;
}
static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6358_priv *priv = pc->driver_data;
const struct bcm6358_pingroup *pg = &bcm6358_groups[group];
unsigned int val = pg->mode_val;
unsigned int mask = val;
unsigned pin;
for (pin = 0; pin < pg->num_pins; pin++)
mask |= (unsigned long)bcm6358_pins[pin].drv_data;
regmap_field_update_bits(priv->overlays, mask, val);
for (pin = 0; pin < pg->num_pins; pin++) {
struct pinctrl_gpio_range *range;
unsigned int hw_gpio = bcm6358_pins[pin].number;
range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);
if (range) {
struct gpio_chip *gc = range->gc;
if (pg->direction & BIT(pin))
gc->direction_output(gc, hw_gpio, 0);
else
gc->direction_input(gc, hw_gpio);
}
}
return 0;
}
static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6358_priv *priv = pc->driver_data;
unsigned int mask;
mask = (unsigned long) bcm6358_pins[offset].drv_data;
if (!mask)
return 0;
/* disable all functions using this pin */
return regmap_field_update_bits(priv->overlays, mask, 0);
}
static struct pinctrl_ops bcm6358_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6358_pinctrl_get_group_name,
.get_group_pins = bcm6358_pinctrl_get_group_pins,
.get_groups_count = bcm6358_pinctrl_get_group_count,
};
static struct pinmux_ops bcm6358_pmx_ops = {
.get_function_groups = bcm6358_pinctrl_get_groups,
.get_function_name = bcm6358_pinctrl_get_func_name,
.get_functions_count = bcm6358_pinctrl_get_func_count,
.gpio_request_enable = bcm6358_gpio_request_enable,
.set_mux = bcm6358_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6358_soc = {
.ngpios = BCM6358_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6358_pins),
.pctl_ops = &bcm6358_pctl_ops,
.pins = bcm6358_pins,
.pmx_ops = &bcm6358_pmx_ops,
};
static int bcm6358_pinctrl_probe(struct platform_device *pdev)
{
struct reg_field overlays = REG_FIELD(BCM6358_MODE_REG, 0, 15);
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct bcm6358_priv *priv;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
err = bcm63xx_pinctrl_probe(pdev, &bcm6358_soc, (void *) priv);
if (err)
return err;
pc = platform_get_drvdata(pdev);
priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
if (IS_ERR(priv->overlays))
return PTR_ERR(priv->overlays);
return 0;
}
static const struct of_device_id bcm6358_pinctrl_match[] = {
{ .compatible = "brcm,bcm6358-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6358_pinctrl_driver = {
.probe = bcm6358_pinctrl_probe,
.driver = {
.name = "bcm6358-pinctrl",
.of_match_table = bcm6358_pinctrl_match,
},
};
builtin_platform_driver(bcm6358_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm6362.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6362 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6362_BANK_GPIOS 32
#define BCM6362_NUM_GPIOS 48
#define BCM6362_NUM_LEDS 24
#define BCM6362_LED_REG 0x10
#define BCM6362_MODE_REG 0x18
#define BCM6362_CTRL_REG 0x1c
#define BCM6362_BASEMODE_REG 0x38
#define BASEMODE_NAND BIT(2)
enum bcm6362_pinctrl_reg {
BCM6362_LEDCTRL,
BCM6362_MODE,
BCM6362_CTRL,
BCM6362_BASEMODE,
};
struct bcm6362_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6362_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
enum bcm6362_pinctrl_reg reg;
uint32_t basemode_mask;
};
#define BCM6362_PIN(a, b, mask) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)(mask), \
}
static const struct pinctrl_pin_desc bcm6362_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
BCM6362_PIN(8, "gpio8", BASEMODE_NAND),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
BCM6362_PIN(12, "gpio12", BASEMODE_NAND),
BCM6362_PIN(13, "gpio13", BASEMODE_NAND),
BCM6362_PIN(14, "gpio14", BASEMODE_NAND),
BCM6362_PIN(15, "gpio15", BASEMODE_NAND),
BCM6362_PIN(16, "gpio16", BASEMODE_NAND),
BCM6362_PIN(17, "gpio17", BASEMODE_NAND),
BCM6362_PIN(18, "gpio18", BASEMODE_NAND),
BCM6362_PIN(19, "gpio19", BASEMODE_NAND),
BCM6362_PIN(20, "gpio20", BASEMODE_NAND),
BCM6362_PIN(21, "gpio21", BASEMODE_NAND),
BCM6362_PIN(22, "gpio22", BASEMODE_NAND),
BCM6362_PIN(23, "gpio23", BASEMODE_NAND),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
BCM6362_PIN(27, "gpio27", BASEMODE_NAND),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
PINCTRL_PIN(30, "gpio30"),
PINCTRL_PIN(31, "gpio31"),
PINCTRL_PIN(32, "gpio32"),
PINCTRL_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
PINCTRL_PIN(38, "gpio38"),
PINCTRL_PIN(39, "gpio39"),
PINCTRL_PIN(40, "gpio40"),
PINCTRL_PIN(41, "gpio41"),
PINCTRL_PIN(42, "gpio42"),
PINCTRL_PIN(43, "gpio43"),
PINCTRL_PIN(44, "gpio44"),
PINCTRL_PIN(45, "gpio45"),
PINCTRL_PIN(46, "gpio46"),
PINCTRL_PIN(47, "gpio47"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned gpio32_pins[] = { 32 };
static unsigned gpio33_pins[] = { 33 };
static unsigned gpio34_pins[] = { 34 };
static unsigned gpio35_pins[] = { 35 };
static unsigned gpio36_pins[] = { 36 };
static unsigned gpio37_pins[] = { 37 };
static unsigned gpio38_pins[] = { 38 };
static unsigned gpio39_pins[] = { 39 };
static unsigned gpio40_pins[] = { 40 };
static unsigned gpio41_pins[] = { 41 };
static unsigned gpio42_pins[] = { 42 };
static unsigned gpio43_pins[] = { 43 };
static unsigned gpio44_pins[] = { 44 };
static unsigned gpio45_pins[] = { 45 };
static unsigned gpio46_pins[] = { 46 };
static unsigned gpio47_pins[] = { 47 };
static unsigned nand_grp_pins[] = {
8, 12, 13, 14, 15, 16, 17,
18, 19, 20, 21, 22, 23, 27,
};
#define BCM6362_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6362_pingroup bcm6362_groups[] = {
BCM6362_GROUP(gpio0),
BCM6362_GROUP(gpio1),
BCM6362_GROUP(gpio2),
BCM6362_GROUP(gpio3),
BCM6362_GROUP(gpio4),
BCM6362_GROUP(gpio5),
BCM6362_GROUP(gpio6),
BCM6362_GROUP(gpio7),
BCM6362_GROUP(gpio8),
BCM6362_GROUP(gpio9),
BCM6362_GROUP(gpio10),
BCM6362_GROUP(gpio11),
BCM6362_GROUP(gpio12),
BCM6362_GROUP(gpio13),
BCM6362_GROUP(gpio14),
BCM6362_GROUP(gpio15),
BCM6362_GROUP(gpio16),
BCM6362_GROUP(gpio17),
BCM6362_GROUP(gpio18),
BCM6362_GROUP(gpio19),
BCM6362_GROUP(gpio20),
BCM6362_GROUP(gpio21),
BCM6362_GROUP(gpio22),
BCM6362_GROUP(gpio23),
BCM6362_GROUP(gpio24),
BCM6362_GROUP(gpio25),
BCM6362_GROUP(gpio26),
BCM6362_GROUP(gpio27),
BCM6362_GROUP(gpio28),
BCM6362_GROUP(gpio29),
BCM6362_GROUP(gpio30),
BCM6362_GROUP(gpio31),
BCM6362_GROUP(gpio32),
BCM6362_GROUP(gpio33),
BCM6362_GROUP(gpio34),
BCM6362_GROUP(gpio35),
BCM6362_GROUP(gpio36),
BCM6362_GROUP(gpio37),
BCM6362_GROUP(gpio38),
BCM6362_GROUP(gpio39),
BCM6362_GROUP(gpio40),
BCM6362_GROUP(gpio41),
BCM6362_GROUP(gpio42),
BCM6362_GROUP(gpio43),
BCM6362_GROUP(gpio44),
BCM6362_GROUP(gpio45),
BCM6362_GROUP(gpio46),
BCM6362_GROUP(gpio47),
BCM6362_GROUP(nand_grp),
};
static const char * const led_groups[] = {
"gpio0",
"gpio1",
"gpio2",
"gpio3",
"gpio4",
"gpio5",
"gpio6",
"gpio7",
"gpio8",
"gpio9",
"gpio10",
"gpio11",
"gpio12",
"gpio13",
"gpio14",
"gpio15",
"gpio16",
"gpio17",
"gpio18",
"gpio19",
"gpio20",
"gpio21",
"gpio22",
"gpio23",
};
static const char * const usb_device_led_groups[] = {
"gpio0",
};
static const char * const sys_irq_groups[] = {
"gpio1",
};
static const char * const serial_led_clk_groups[] = {
"gpio2",
};
static const char * const serial_led_data_groups[] = {
"gpio3",
};
static const char * const robosw_led_data_groups[] = {
"gpio4",
};
static const char * const robosw_led_clk_groups[] = {
"gpio5",
};
static const char * const robosw_led0_groups[] = {
"gpio6",
};
static const char * const robosw_led1_groups[] = {
"gpio7",
};
static const char * const inet_led_groups[] = {
"gpio8",
};
static const char * const spi_cs2_groups[] = {
"gpio9",
};
static const char * const spi_cs3_groups[] = {
"gpio10",
};
static const char * const ntr_pulse_groups[] = {
"gpio11",
};
static const char * const uart1_scts_groups[] = {
"gpio12",
};
static const char * const uart1_srts_groups[] = {
"gpio13",
};
static const char * const uart1_sdin_groups[] = {
"gpio14",
};
static const char * const uart1_sdout_groups[] = {
"gpio15",
};
static const char * const adsl_spi_miso_groups[] = {
"gpio16",
};
static const char * const adsl_spi_mosi_groups[] = {
"gpio17",
};
static const char * const adsl_spi_clk_groups[] = {
"gpio18",
};
static const char * const adsl_spi_cs_groups[] = {
"gpio19",
};
static const char * const ephy0_led_groups[] = {
"gpio20",
};
static const char * const ephy1_led_groups[] = {
"gpio21",
};
static const char * const ephy2_led_groups[] = {
"gpio22",
};
static const char * const ephy3_led_groups[] = {
"gpio23",
};
static const char * const ext_irq0_groups[] = {
"gpio24",
};
static const char * const ext_irq1_groups[] = {
"gpio25",
};
static const char * const ext_irq2_groups[] = {
"gpio26",
};
static const char * const ext_irq3_groups[] = {
"gpio27",
};
static const char * const wifi_groups[] = {
"gpio32",
"gpio33",
"gpio34",
"gpio35",
"gpio36",
"gpio37",
"gpio38",
"gpio39",
"gpio40",
"gpio41",
"gpio42",
"gpio43",
"gpio44",
"gpio45",
"gpio46",
"gpio47",
};
static const char * const nand_groups[] = {
"nand_grp",
};
#define BCM6362_LED_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_LEDCTRL, \
}
#define BCM6362_MODE_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_MODE, \
}
#define BCM6362_CTRL_FUN(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_CTRL, \
}
#define BCM6362_BASEMODE_FUN(n, mask) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.reg = BCM6362_BASEMODE, \
.basemode_mask = (mask), \
}
static const struct bcm6362_function bcm6362_funcs[] = {
BCM6362_LED_FUN(led),
BCM6362_MODE_FUN(usb_device_led),
BCM6362_MODE_FUN(sys_irq),
BCM6362_MODE_FUN(serial_led_clk),
BCM6362_MODE_FUN(serial_led_data),
BCM6362_MODE_FUN(robosw_led_data),
BCM6362_MODE_FUN(robosw_led_clk),
BCM6362_MODE_FUN(robosw_led0),
BCM6362_MODE_FUN(robosw_led1),
BCM6362_MODE_FUN(inet_led),
BCM6362_MODE_FUN(spi_cs2),
BCM6362_MODE_FUN(spi_cs3),
BCM6362_MODE_FUN(ntr_pulse),
BCM6362_MODE_FUN(uart1_scts),
BCM6362_MODE_FUN(uart1_srts),
BCM6362_MODE_FUN(uart1_sdin),
BCM6362_MODE_FUN(uart1_sdout),
BCM6362_MODE_FUN(adsl_spi_miso),
BCM6362_MODE_FUN(adsl_spi_mosi),
BCM6362_MODE_FUN(adsl_spi_clk),
BCM6362_MODE_FUN(adsl_spi_cs),
BCM6362_MODE_FUN(ephy0_led),
BCM6362_MODE_FUN(ephy1_led),
BCM6362_MODE_FUN(ephy2_led),
BCM6362_MODE_FUN(ephy3_led),
BCM6362_MODE_FUN(ext_irq0),
BCM6362_MODE_FUN(ext_irq1),
BCM6362_MODE_FUN(ext_irq2),
BCM6362_MODE_FUN(ext_irq3),
BCM6362_CTRL_FUN(wifi),
BCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),
};
static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6362_groups);
}
static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6362_groups[group].name;
}
static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm6362_groups[group].pins;
*num_pins = bcm6362_groups[group].num_pins;
return 0;
}
static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6362_funcs);
}
static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6362_funcs[selector].name;
}
static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6362_funcs[selector].groups;
*num_groups = bcm6362_funcs[selector].num_groups;
return 0;
}
static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)
{
const struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];
unsigned int basemode = (uintptr_t)desc->drv_data;
unsigned int mask = bcm63xx_bank_pin(pin);
if (basemode)
regmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, basemode, 0);
if (pin < BCM63XX_BANK_GPIOS) {
/* base mode 0 => gpio 1 => mux function */
regmap_update_bits(pc->regs, BCM6362_MODE_REG, mask, 0);
/* pins 0-23 might be muxed to led */
if (pin < BCM6362_NUM_LEDS)
regmap_update_bits(pc->regs, BCM6362_LED_REG, mask, 0);
} else {
/* ctrl reg 0 => wifi function 1 => gpio */
regmap_update_bits(pc->regs, BCM6362_CTRL_REG, mask, mask);
}
}
static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6362_pingroup *pg = &bcm6362_groups[group];
const struct bcm6362_function *f = &bcm6362_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
bcm6362_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
case BCM6362_LEDCTRL:
reg = BCM6362_LED_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM6362_MODE:
reg = BCM6362_MODE_REG;
mask = BIT(pg->pins[0]);
val = BIT(pg->pins[0]);
break;
case BCM6362_CTRL:
reg = BCM6362_CTRL_REG;
mask = BIT(pg->pins[0]);
val = 0;
break;
case BCM6362_BASEMODE:
reg = BCM6362_BASEMODE_REG;
mask = f->basemode_mask;
val = f->basemode_mask;
break;
default:
WARN_ON(1);
return -EINVAL;
}
regmap_update_bits(pc->regs, reg, mask, val);
return 0;
}
static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
/* disable all functions using this pin */
bcm6362_set_gpio(pc, offset);
return 0;
}
static struct pinctrl_ops bcm6362_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6362_pinctrl_get_group_name,
.get_group_pins = bcm6362_pinctrl_get_group_pins,
.get_groups_count = bcm6362_pinctrl_get_group_count,
};
static struct pinmux_ops bcm6362_pmx_ops = {
.get_function_groups = bcm6362_pinctrl_get_groups,
.get_function_name = bcm6362_pinctrl_get_func_name,
.get_functions_count = bcm6362_pinctrl_get_func_count,
.gpio_request_enable = bcm6362_gpio_request_enable,
.set_mux = bcm6362_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6362_soc = {
.ngpios = BCM6362_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6362_pins),
.pctl_ops = &bcm6362_pctl_ops,
.pins = bcm6362_pins,
.pmx_ops = &bcm6362_pmx_ops,
};
static int bcm6362_pinctrl_probe(struct platform_device *pdev)
{
return bcm63xx_pinctrl_probe(pdev, &bcm6362_soc, NULL);
}
static const struct of_device_id bcm6362_pinctrl_match[] = {
{ .compatible = "brcm,bcm6362-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6362_pinctrl_driver = {
.probe = bcm6362_pinctrl_probe,
.driver = {
.name = "bcm6362-pinctrl",
.of_match_table = bcm6362_pinctrl_match,
},
};
builtin_platform_driver(bcm6362_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm6368.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM6368 GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include "../pinctrl-utils.h"
#include "pinctrl-bcm63xx.h"
#define BCM6368_NUM_GPIOS 38
#define BCM6368_MODE_REG 0x18
#define BCM6368_BASEMODE_REG 0x38
#define BCM6368_BASEMODE_MASK 0x7
#define BCM6368_BASEMODE_GPIO 0x0
#define BCM6368_BASEMODE_UART1 0x1
struct bcm6368_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6368_function {
const char *name;
const char * const *groups;
const unsigned num_groups;
unsigned dir_out:16;
unsigned basemode:3;
};
struct bcm6368_priv {
struct regmap_field *overlays;
};
#define BCM6368_BASEMODE_PIN(a, b) \
{ \
.number = a, \
.name = b, \
.drv_data = (void *)true \
}
static const struct pinctrl_pin_desc bcm6368_pins[] = {
PINCTRL_PIN(0, "gpio0"),
PINCTRL_PIN(1, "gpio1"),
PINCTRL_PIN(2, "gpio2"),
PINCTRL_PIN(3, "gpio3"),
PINCTRL_PIN(4, "gpio4"),
PINCTRL_PIN(5, "gpio5"),
PINCTRL_PIN(6, "gpio6"),
PINCTRL_PIN(7, "gpio7"),
PINCTRL_PIN(8, "gpio8"),
PINCTRL_PIN(9, "gpio9"),
PINCTRL_PIN(10, "gpio10"),
PINCTRL_PIN(11, "gpio11"),
PINCTRL_PIN(12, "gpio12"),
PINCTRL_PIN(13, "gpio13"),
PINCTRL_PIN(14, "gpio14"),
PINCTRL_PIN(15, "gpio15"),
PINCTRL_PIN(16, "gpio16"),
PINCTRL_PIN(17, "gpio17"),
PINCTRL_PIN(18, "gpio18"),
PINCTRL_PIN(19, "gpio19"),
PINCTRL_PIN(20, "gpio20"),
PINCTRL_PIN(21, "gpio21"),
PINCTRL_PIN(22, "gpio22"),
PINCTRL_PIN(23, "gpio23"),
PINCTRL_PIN(24, "gpio24"),
PINCTRL_PIN(25, "gpio25"),
PINCTRL_PIN(26, "gpio26"),
PINCTRL_PIN(27, "gpio27"),
PINCTRL_PIN(28, "gpio28"),
PINCTRL_PIN(29, "gpio29"),
BCM6368_BASEMODE_PIN(30, "gpio30"),
BCM6368_BASEMODE_PIN(31, "gpio31"),
BCM6368_BASEMODE_PIN(32, "gpio32"),
BCM6368_BASEMODE_PIN(33, "gpio33"),
PINCTRL_PIN(34, "gpio34"),
PINCTRL_PIN(35, "gpio35"),
PINCTRL_PIN(36, "gpio36"),
PINCTRL_PIN(37, "gpio37"),
};
static unsigned gpio0_pins[] = { 0 };
static unsigned gpio1_pins[] = { 1 };
static unsigned gpio2_pins[] = { 2 };
static unsigned gpio3_pins[] = { 3 };
static unsigned gpio4_pins[] = { 4 };
static unsigned gpio5_pins[] = { 5 };
static unsigned gpio6_pins[] = { 6 };
static unsigned gpio7_pins[] = { 7 };
static unsigned gpio8_pins[] = { 8 };
static unsigned gpio9_pins[] = { 9 };
static unsigned gpio10_pins[] = { 10 };
static unsigned gpio11_pins[] = { 11 };
static unsigned gpio12_pins[] = { 12 };
static unsigned gpio13_pins[] = { 13 };
static unsigned gpio14_pins[] = { 14 };
static unsigned gpio15_pins[] = { 15 };
static unsigned gpio16_pins[] = { 16 };
static unsigned gpio17_pins[] = { 17 };
static unsigned gpio18_pins[] = { 18 };
static unsigned gpio19_pins[] = { 19 };
static unsigned gpio20_pins[] = { 20 };
static unsigned gpio21_pins[] = { 21 };
static unsigned gpio22_pins[] = { 22 };
static unsigned gpio23_pins[] = { 23 };
static unsigned gpio24_pins[] = { 24 };
static unsigned gpio25_pins[] = { 25 };
static unsigned gpio26_pins[] = { 26 };
static unsigned gpio27_pins[] = { 27 };
static unsigned gpio28_pins[] = { 28 };
static unsigned gpio29_pins[] = { 29 };
static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
#define BCM6368_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6368_pingroup bcm6368_groups[] = {
BCM6368_GROUP(gpio0),
BCM6368_GROUP(gpio1),
BCM6368_GROUP(gpio2),
BCM6368_GROUP(gpio3),
BCM6368_GROUP(gpio4),
BCM6368_GROUP(gpio5),
BCM6368_GROUP(gpio6),
BCM6368_GROUP(gpio7),
BCM6368_GROUP(gpio8),
BCM6368_GROUP(gpio9),
BCM6368_GROUP(gpio10),
BCM6368_GROUP(gpio11),
BCM6368_GROUP(gpio12),
BCM6368_GROUP(gpio13),
BCM6368_GROUP(gpio14),
BCM6368_GROUP(gpio15),
BCM6368_GROUP(gpio16),
BCM6368_GROUP(gpio17),
BCM6368_GROUP(gpio18),
BCM6368_GROUP(gpio19),
BCM6368_GROUP(gpio20),
BCM6368_GROUP(gpio21),
BCM6368_GROUP(gpio22),
BCM6368_GROUP(gpio23),
BCM6368_GROUP(gpio24),
BCM6368_GROUP(gpio25),
BCM6368_GROUP(gpio26),
BCM6368_GROUP(gpio27),
BCM6368_GROUP(gpio28),
BCM6368_GROUP(gpio29),
BCM6368_GROUP(gpio30),
BCM6368_GROUP(gpio31),
BCM6368_GROUP(uart1_grp),
};
static const char * const analog_afe_0_groups[] = {
"gpio0",
};
static const char * const analog_afe_1_groups[] = {
"gpio1",
};
static const char * const sys_irq_groups[] = {
"gpio2",
};
static const char * const serial_led_data_groups[] = {
"gpio3",
};
static const char * const serial_led_clk_groups[] = {
"gpio4",
};
static const char * const inet_led_groups[] = {
"gpio5",
};
static const char * const ephy0_led_groups[] = {
"gpio6",
};
static const char * const ephy1_led_groups[] = {
"gpio7",
};
static const char * const ephy2_led_groups[] = {
"gpio8",
};
static const char * const ephy3_led_groups[] = {
"gpio9",
};
static const char * const robosw_led_data_groups[] = {
"gpio10",
};
static const char * const robosw_led_clk_groups[] = {
"gpio11",
};
static const char * const robosw_led0_groups[] = {
"gpio12",
};
static const char * const robosw_led1_groups[] = {
"gpio13",
};
static const char * const usb_device_led_groups[] = {
"gpio14",
};
static const char * const pci_req1_groups[] = {
"gpio16",
};
static const char * const pci_gnt1_groups[] = {
"gpio17",
};
static const char * const pci_intb_groups[] = {
"gpio18",
};
static const char * const pci_req0_groups[] = {
"gpio19",
};
static const char * const pci_gnt0_groups[] = {
"gpio20",
};
static const char * const pcmcia_cd1_groups[] = {
"gpio22",
};
static const char * const pcmcia_cd2_groups[] = {
"gpio23",
};
static const char * const pcmcia_vs1_groups[] = {
"gpio24",
};
static const char * const pcmcia_vs2_groups[] = {
"gpio25",
};
static const char * const ebi_cs2_groups[] = {
"gpio26",
};
static const char * const ebi_cs3_groups[] = {
"gpio27",
};
static const char * const spi_cs2_groups[] = {
"gpio28",
};
static const char * const spi_cs3_groups[] = {
"gpio29",
};
static const char * const spi_cs4_groups[] = {
"gpio30",
};
static const char * const spi_cs5_groups[] = {
"gpio31",
};
static const char * const uart1_groups[] = {
"uart1_grp",
};
#define BCM6368_FUN(n, out) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.dir_out = out, \
}
#define BCM6368_BASEMODE_FUN(n, val, out) \
{ \
.name = #n, \
.groups = n##_groups, \
.num_groups = ARRAY_SIZE(n##_groups), \
.basemode = BCM6368_BASEMODE_##val, \
.dir_out = out, \
}
static const struct bcm6368_function bcm6368_funcs[] = {
BCM6368_FUN(analog_afe_0, 1),
BCM6368_FUN(analog_afe_1, 1),
BCM6368_FUN(sys_irq, 1),
BCM6368_FUN(serial_led_data, 1),
BCM6368_FUN(serial_led_clk, 1),
BCM6368_FUN(inet_led, 1),
BCM6368_FUN(ephy0_led, 1),
BCM6368_FUN(ephy1_led, 1),
BCM6368_FUN(ephy2_led, 1),
BCM6368_FUN(ephy3_led, 1),
BCM6368_FUN(robosw_led_data, 1),
BCM6368_FUN(robosw_led_clk, 1),
BCM6368_FUN(robosw_led0, 1),
BCM6368_FUN(robosw_led1, 1),
BCM6368_FUN(usb_device_led, 1),
BCM6368_FUN(pci_req1, 0),
BCM6368_FUN(pci_gnt1, 0),
BCM6368_FUN(pci_intb, 0),
BCM6368_FUN(pci_req0, 0),
BCM6368_FUN(pci_gnt0, 0),
BCM6368_FUN(pcmcia_cd1, 0),
BCM6368_FUN(pcmcia_cd2, 0),
BCM6368_FUN(pcmcia_vs1, 0),
BCM6368_FUN(pcmcia_vs2, 0),
BCM6368_FUN(ebi_cs2, 1),
BCM6368_FUN(ebi_cs3, 1),
BCM6368_FUN(spi_cs2, 1),
BCM6368_FUN(spi_cs3, 1),
BCM6368_FUN(spi_cs4, 1),
BCM6368_FUN(spi_cs5, 1),
BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
};
static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6368_groups);
}
static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6368_groups[group].name;
}
static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
{
*pins = bcm6368_groups[group].pins;
*num_pins = bcm6368_groups[group].num_pins;
return 0;
}
static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(bcm6368_funcs);
}
static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return bcm6368_funcs[selector].name;
}
static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = bcm6368_funcs[selector].groups;
*num_groups = bcm6368_funcs[selector].num_groups;
return 0;
}
static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
const struct bcm6368_pingroup *pg = &bcm6368_groups[group];
const struct bcm6368_function *fun = &bcm6368_funcs[selector];
int i, pin;
if (fun->basemode) {
unsigned int mask = 0;
for (i = 0; i < pg->num_pins; i++) {
pin = pg->pins[i];
if (pin < BCM63XX_BANK_GPIOS)
mask |= BIT(pin);
}
regmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0);
regmap_field_write(priv->overlays, fun->basemode);
} else {
pin = pg->pins[0];
if (bcm6368_pins[pin].drv_data)
regmap_field_write(priv->overlays,
BCM6368_BASEMODE_GPIO);
regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin),
BIT(pin));
}
for (pin = 0; pin < pg->num_pins; pin++) {
struct pinctrl_gpio_range *range;
int hw_gpio = bcm6368_pins[pin].number;
range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);
if (range) {
struct gpio_chip *gc = range->gc;
if (fun->dir_out & BIT(pin))
gc->direction_output(gc, hw_gpio, 0);
else
gc->direction_input(gc, hw_gpio);
}
}
return 0;
}
static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
if (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data)
return 0;
/* disable all functions using this pin */
if (offset < BCM63XX_BANK_GPIOS)
regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0);
if (bcm6368_pins[offset].drv_data)
regmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO);
return 0;
}
static struct pinctrl_ops bcm6368_pctl_ops = {
.dt_free_map = pinctrl_utils_free_map,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.get_group_name = bcm6368_pinctrl_get_group_name,
.get_group_pins = bcm6368_pinctrl_get_group_pins,
.get_groups_count = bcm6368_pinctrl_get_group_count,
};
static struct pinmux_ops bcm6368_pmx_ops = {
.get_function_groups = bcm6368_pinctrl_get_groups,
.get_function_name = bcm6368_pinctrl_get_func_name,
.get_functions_count = bcm6368_pinctrl_get_func_count,
.gpio_request_enable = bcm6368_gpio_request_enable,
.set_mux = bcm6368_pinctrl_set_mux,
.strict = true,
};
static const struct bcm63xx_pinctrl_soc bcm6368_soc = {
.ngpios = BCM6368_NUM_GPIOS,
.npins = ARRAY_SIZE(bcm6368_pins),
.pctl_ops = &bcm6368_pctl_ops,
.pins = bcm6368_pins,
.pmx_ops = &bcm6368_pmx_ops,
};
static int bcm6368_pinctrl_probe(struct platform_device *pdev)
{
struct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15);
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct bcm6368_priv *priv;
int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
err = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv);
if (err)
return err;
pc = platform_get_drvdata(pdev);
priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
if (IS_ERR(priv->overlays))
return PTR_ERR(priv->overlays);
return 0;
}
static const struct of_device_id bcm6368_pinctrl_match[] = {
{ .compatible = "brcm,bcm6368-pinctrl", },
{ /* sentinel */ }
};
static struct platform_driver bcm6368_pinctrl_driver = {
.probe = bcm6368_pinctrl_probe,
.driver = {
.name = "bcm6368-pinctrl",
.of_match_table = bcm6368_pinctrl_match,
},
};
builtin_platform_driver(bcm6368_pinctrl_driver);

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drivers/pinctrl/bcm/pinctrl-bcm63xx.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Driver for BCM63xx GPIO unit (pinctrl + GPIO)
*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/gpio/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include "pinctrl-bcm63xx.h"
#define BCM63XX_BANK_SIZE 4
#define BCM63XX_DIROUT_REG 0x04
#define BCM63XX_DATA_REG 0x0c
static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,
unsigned int base, unsigned int offset,
unsigned int *reg, unsigned int *mask)
{
unsigned int line = offset % BCM63XX_BANK_GPIOS;
unsigned int stride = offset / BCM63XX_BANK_GPIOS;
*reg = base - stride * BCM63XX_BANK_SIZE;
*mask = BIT(line);
return 0;
}
static const struct of_device_id bcm63xx_gpio_of_match[] = {
{ .compatible = "brcm,bcm6318-gpio", },
{ .compatible = "brcm,bcm6328-gpio", },
{ .compatible = "brcm,bcm6358-gpio", },
{ .compatible = "brcm,bcm6362-gpio", },
{ .compatible = "brcm,bcm6368-gpio", },
{ .compatible = "brcm,bcm63268-gpio", },
{ /* sentinel */ }
};
static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node,
const struct bcm63xx_pinctrl_soc *soc,
struct bcm63xx_pinctrl *pc)
{
struct gpio_regmap_config grc = {0};
grc.parent = dev;
grc.fwnode = &node->fwnode;
grc.ngpio = soc->ngpios;
grc.ngpio_per_reg = BCM63XX_BANK_GPIOS;
grc.regmap = pc->regs;
grc.reg_dat_base = BCM63XX_DATA_REG;
grc.reg_dir_out_base = BCM63XX_DIROUT_REG;
grc.reg_set_base = BCM63XX_DATA_REG;
grc.reg_mask_xlate = bcm63xx_reg_mask_xlate;
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc));
}
int bcm63xx_pinctrl_probe(struct platform_device *pdev,
const struct bcm63xx_pinctrl_soc *soc,
void *driver_data)
{
struct device *dev = &pdev->dev;
struct bcm63xx_pinctrl *pc;
struct device_node *node;
int err;
pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
if (!pc)
return -ENOMEM;
platform_set_drvdata(pdev, pc);
pc->dev = dev;
pc->driver_data = driver_data;
pc->regs = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
pc->pctl_desc.name = dev_name(dev);
pc->pctl_desc.pins = soc->pins;
pc->pctl_desc.npins = soc->npins;
pc->pctl_desc.pctlops = soc->pctl_ops;
pc->pctl_desc.pmxops = soc->pmx_ops;
pc->pctl_desc.owner = THIS_MODULE;
pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
if (IS_ERR(pc->pctl_dev))
return PTR_ERR(pc->pctl_dev);
for_each_child_of_node(dev->parent->of_node, node) {
if (of_match_node(bcm63xx_gpio_of_match, node)) {
err = bcm63xx_gpio_probe(dev, node, soc, pc);
if (err) {
dev_err(dev, "could not add GPIO chip\n");
of_node_put(node);
return err;
}
}
}
return 0;
}

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drivers/pinctrl/bcm/pinctrl-bcm63xx.h Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
*/
#ifndef __PINCTRL_BCM63XX_H__
#define __PINCTRL_BCM63XX_H__
#include <linux/pinctrl/pinctrl.h>
#define BCM63XX_BANK_GPIOS 32
struct bcm63xx_pinctrl_soc {
struct pinctrl_ops *pctl_ops;
struct pinmux_ops *pmx_ops;
const struct pinctrl_pin_desc *pins;
unsigned npins;
unsigned int ngpios;
};
struct bcm63xx_pinctrl {
struct device *dev;
struct regmap *regs;
struct pinctrl_desc pctl_desc;
struct pinctrl_dev *pctl_dev;
void *driver_data;
};
static inline unsigned int bcm63xx_bank_pin(unsigned int pin)
{
return pin % BCM63XX_BANK_GPIOS;
}
int bcm63xx_pinctrl_probe(struct platform_device *pdev,
const struct bcm63xx_pinctrl_soc *soc,
void *driver_data);
#endif /* __PINCTRL_BCM63XX_H__ */

39
drivers/pinctrl/core.c
View File

@ -160,7 +160,7 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
}
/**
* pin_get_name_from_id() - look up a pin name from a pin id
* pin_get_name() - look up a pin name from a pin id
* @pctldev: the pin control device to lookup the pin on
* @pin: pin number/id to look up
*/
@ -1258,13 +1258,36 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
p->state = NULL;
/* Apply all the settings for the new state */
/* Apply all the settings for the new state - pinmux first */
list_for_each_entry(setting, &state->settings, node) {
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = pinmux_enable_setting(setting);
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = 0;
break;
default:
ret = -EINVAL;
break;
}
if (ret < 0)
goto unapply_new_state;
/* Do not link hogs (circular dependency) */
if (p != setting->pctldev->p)
pinctrl_link_add(setting->pctldev, p->dev);
}
/* Apply all the settings for the new state - pinconf after */
list_for_each_entry(setting, &state->settings, node) {
switch (setting->type) {
case PIN_MAP_TYPE_MUX_GROUP:
ret = 0;
break;
case PIN_MAP_TYPE_CONFIGS_PIN:
case PIN_MAP_TYPE_CONFIGS_GROUP:
ret = pinconf_apply_setting(setting);
break;
@ -1892,11 +1915,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
dev_name(pctldev->dev));
return;
}
debugfs_create_file("pins", S_IFREG | S_IRUGO,
debugfs_create_file("pins", 0444,
device_root, pctldev, &pinctrl_pins_fops);
debugfs_create_file("pingroups", S_IFREG | S_IRUGO,
debugfs_create_file("pingroups", 0444,
device_root, pctldev, &pinctrl_groups_fops);
debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
debugfs_create_file("gpio-ranges", 0444,
device_root, pctldev, &pinctrl_gpioranges_fops);
if (pctldev->desc->pmxops)
pinmux_init_device_debugfs(device_root, pctldev);
@ -1918,11 +1941,11 @@ static void pinctrl_init_debugfs(void)
return;
}
debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
debugfs_create_file("pinctrl-devices", 0444,
debugfs_root, NULL, &pinctrl_devices_fops);
debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO,
debugfs_create_file("pinctrl-maps", 0444,
debugfs_root, NULL, &pinctrl_maps_fops);
debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO,
debugfs_create_file("pinctrl-handles", 0444,
debugfs_root, NULL, &pinctrl_fops);
}

1
drivers/pinctrl/freescale/pinctrl-imx1.c
View File

@ -262,6 +262,7 @@ static struct platform_driver imx1_pinctrl_driver = {
.driver = {
.name = "imx1-pinctrl",
.of_match_table = imx1_pinctrl_of_match,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);

3
drivers/pinctrl/freescale/pinctrl-imx25.c
View File

@ -323,7 +323,8 @@ static int imx25_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx25_pinctrl_driver = {
.driver = {
.name = "imx25-pinctrl",
.of_match_table = of_match_ptr(imx25_pinctrl_of_match),
.of_match_table = imx25_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx25_pinctrl_probe,
};

3
drivers/pinctrl/freescale/pinctrl-imx27.c
View File

@ -396,7 +396,8 @@ static int imx27_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx27_pinctrl_driver = {
.driver = {
.name = "imx27-pinctrl",
.of_match_table = of_match_ptr(imx27_pinctrl_of_match),
.of_match_table = imx27_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx27_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx35.c
View File

@ -1014,6 +1014,7 @@ static struct platform_driver imx35_pinctrl_driver = {
.driver = {
.name = "imx35-pinctrl",
.of_match_table = imx35_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx35_pinctrl_probe,
};

3
drivers/pinctrl/freescale/pinctrl-imx50.c
View File

@ -399,7 +399,8 @@ static int imx50_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx50_pinctrl_driver = {
.driver = {
.name = "imx50-pinctrl",
.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
.of_match_table = imx50_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx50_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx51.c
View File

@ -776,6 +776,7 @@ static struct platform_driver imx51_pinctrl_driver = {
.driver = {
.name = "imx51-pinctrl",
.of_match_table = imx51_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx51_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx53.c
View File

@ -463,6 +463,7 @@ static struct platform_driver imx53_pinctrl_driver = {
.driver = {
.name = "imx53-pinctrl",
.of_match_table = imx53_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx53_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx6dl.c
View File

@ -473,6 +473,7 @@ static struct platform_driver imx6dl_pinctrl_driver = {
.driver = {
.name = "imx6dl-pinctrl",
.of_match_table = imx6dl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6dl_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx6q.c
View File

@ -475,6 +475,7 @@ static struct platform_driver imx6q_pinctrl_driver = {
.driver = {
.name = "imx6q-pinctrl",
.of_match_table = imx6q_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6q_pinctrl_probe,
};

1
drivers/pinctrl/freescale/pinctrl-imx6sl.c
View File

@ -379,6 +379,7 @@ static struct platform_driver imx6sl_pinctrl_driver = {
.driver = {
.name = "imx6sl-pinctrl",
.of_match_table = imx6sl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sl_pinctrl_probe,
};

2
drivers/pinctrl/freescale/pinctrl-imx6sll.c
View File

@ -345,7 +345,7 @@ static int imx6sll_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx6sll_pinctrl_driver = {
.driver = {
.name = "imx6sll-pinctrl",
.of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
.of_match_table = imx6sll_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sll_pinctrl_probe,

3
drivers/pinctrl/freescale/pinctrl-imx6sx.c
View File

@ -382,7 +382,8 @@ static int imx6sx_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx6sx_pinctrl_driver = {
.driver = {
.name = "imx6sx-pinctrl",
.of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
.of_match_table = imx6sx_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6sx_pinctrl_probe,
};

3
drivers/pinctrl/freescale/pinctrl-imx6ul.c
View File

@ -342,7 +342,8 @@ static int imx6ul_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx6ul_pinctrl_driver = {
.driver = {
.name = "imx6ul-pinctrl",
.of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
.of_match_table = imx6ul_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx6ul_pinctrl_probe,
};

3
drivers/pinctrl/freescale/pinctrl-imx7d.c
View File

@ -386,7 +386,8 @@ static int imx7d_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx7d_pinctrl_driver = {
.driver = {
.name = "imx7d-pinctrl",
.of_match_table = of_match_ptr(imx7d_pinctrl_of_match),
.of_match_table = imx7d_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx7d_pinctrl_probe,
};

2
drivers/pinctrl/freescale/pinctrl-imx7ulp.c
View File

@ -303,7 +303,7 @@ static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx7ulp_pinctrl_driver = {
.driver = {
.name = "imx7ulp-pinctrl",
.of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match),
.of_match_table = imx7ulp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx7ulp_pinctrl_probe,

2
drivers/pinctrl/freescale/pinctrl-imx8dxl.c
View File

@ -184,7 +184,7 @@ static int imx8dxl_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8dxl_pinctrl_driver = {
.driver = {
.name = "fsl,imx8dxl-iomuxc",
.of_match_table = of_match_ptr(imx8dxl_pinctrl_of_match),
.of_match_table = imx8dxl_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8dxl_pinctrl_probe,

2
drivers/pinctrl/freescale/pinctrl-imx8mm.c
View File

@ -337,7 +337,7 @@ static int imx8mm_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8mm_pinctrl_driver = {
.driver = {
.name = "imx8mm-pinctrl",
.of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
.of_match_table = imx8mm_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mm_pinctrl_probe,

2
drivers/pinctrl/freescale/pinctrl-imx8mn.c
View File

@ -337,7 +337,7 @@ static int imx8mn_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8mn_pinctrl_driver = {
.driver = {
.name = "imx8mn-pinctrl",
.of_match_table = of_match_ptr(imx8mn_pinctrl_of_match),
.of_match_table = imx8mn_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mn_pinctrl_probe,

3
drivers/pinctrl/freescale/pinctrl-imx8mp.c
View File

@ -335,7 +335,8 @@ static int imx8mp_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8mp_pinctrl_driver = {
.driver = {
.name = "imx8mp-pinctrl",
.of_match_table = of_match_ptr(imx8mp_pinctrl_of_match),
.of_match_table = imx8mp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8mp_pinctrl_probe,
};

2
drivers/pinctrl/freescale/pinctrl-imx8mq.c
View File

@ -340,7 +340,7 @@ static int imx8mq_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8mq_pinctrl_driver = {
.driver = {
.name = "imx8mq-pinctrl",
.of_match_table = of_match_ptr(imx8mq_pinctrl_of_match),
.of_match_table = imx8mq_pinctrl_of_match,
.pm = &imx_pinctrl_pm_ops,
.suppress_bind_attrs = true,
},

2
drivers/pinctrl/freescale/pinctrl-imx8qm.c
View File

@ -317,7 +317,7 @@ static int imx8qm_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8qm_pinctrl_driver = {
.driver = {
.name = "imx8qm-pinctrl",
.of_match_table = of_match_ptr(imx8qm_pinctrl_of_match),
.of_match_table = imx8qm_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8qm_pinctrl_probe,

2
drivers/pinctrl/freescale/pinctrl-imx8qxp.c
View File

@ -223,7 +223,7 @@ static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
static struct platform_driver imx8qxp_pinctrl_driver = {
.driver = {
.name = "imx8qxp-pinctrl",
.of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
.of_match_table = imx8qxp_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = imx8qxp_pinctrl_probe,

1
drivers/pinctrl/freescale/pinctrl-vf610.c
View File

@ -336,6 +336,7 @@ static struct platform_driver vf610_pinctrl_driver = {
.driver = {
.name = "vf610-pinctrl",
.of_match_table = vf610_pinctrl_of_match,
.suppress_bind_attrs = true,
},
.probe = vf610_pinctrl_probe,
};

5
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -1173,16 +1173,15 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
for (gpp = 0; gpp < community->ngpps; gpp++) {
const struct intel_padgroup *padgrp = &community->gpps[gpp];
unsigned long pending, enabled, gpp_offset;
unsigned long flags;
raw_spin_lock_irqsave(&pctrl->lock, flags);
raw_spin_lock(&pctrl->lock);
pending = readl(community->regs + community->is_offset +
padgrp->reg_num * 4);
enabled = readl(community->regs + community->ie_offset +
padgrp->reg_num * 4);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
raw_spin_unlock(&pctrl->lock);
/* Only interrupts that are enabled */
pending &= enabled;

6
drivers/pinctrl/mediatek/Kconfig
View File

@ -147,6 +147,12 @@ config PINCTRL_MT8192
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8195
bool "Mediatek MT8195 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
select PINCTRL_MTK_PARIS
config PINCTRL_MT8516
bool "Mediatek MT8516 pin control"
depends on OF

1
drivers/pinctrl/mediatek/Makefile
View File

@ -21,5 +21,6 @@ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

2
drivers/pinctrl/mediatek/pinctrl-moore.c
View File

@ -619,6 +619,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev,
hw->nbase = hw->soc->nbase_names;
spin_lock_init(&hw->lock);
/* Copy from internal struct mtk_pin_desc to register to the core */
pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
GFP_KERNEL);

850
drivers/pinctrl/mediatek/pinctrl-mt8195.c Normal file
View File

@ -0,0 +1,850 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 MediaTek Inc.
*
* Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
*
*/
#include "pinctrl-mtk-mt8195.h"
#include "pinctrl-paris.h"
/* MT8195 have multiple bases to program pin configuration listed as the below:
* iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
* iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
* iocfg[6]:0x11f40000.
* _i_based could be used to indicate what base the pin should be mapped into.
*/
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 0)
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
32, 1)
static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = {
PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
};
static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = {
PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_di_range[] = {
PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_do_range[] = {
PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x040, 0x10, 5, 1),
PIN_FIELD_BASE(6, 6, 4, 0x040, 0x10, 6, 1),
PIN_FIELD_BASE(7, 7, 4, 0x040, 0x10, 7, 1),
PIN_FIELD_BASE(8, 8, 4, 0x040, 0x10, 13, 1),
PIN_FIELD_BASE(9, 9, 4, 0x040, 0x10, 8, 1),
PIN_FIELD_BASE(10, 10, 4, 0x040, 0x10, 14, 1),
PIN_FIELD_BASE(11, 11, 4, 0x040, 0x10, 9, 1),
PIN_FIELD_BASE(12, 12, 4, 0x040, 0x10, 15, 1),
PIN_FIELD_BASE(13, 13, 4, 0x040, 0x10, 10, 1),
PIN_FIELD_BASE(14, 14, 4, 0x040, 0x10, 16, 1),
PIN_FIELD_BASE(15, 15, 4, 0x040, 0x10, 11, 1),
PIN_FIELD_BASE(16, 16, 4, 0x040, 0x10, 17, 1),
PIN_FIELD_BASE(17, 17, 4, 0x040, 0x10, 12, 1),
PIN_FIELD_BASE(18, 18, 2, 0x040, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x040, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x040, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x040, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x040, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x040, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x040, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x040, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x060, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x060, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x060, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x060, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x060, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x070, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x070, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x070, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x070, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x070, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x070, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x070, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x070, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x070, 0x10, 20, 1),
PIN_FIELD_BASE(45, 45, 1, 0x070, 0x10, 21, 1),
PIN_FIELD_BASE(46, 46, 1, 0x060, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x060, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x060, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x060, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x060, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x060, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x060, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x060, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x060, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x060, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x060, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x060, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x060, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x060, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x060, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x060, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x060, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x060, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x060, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x070, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x060, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x070, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x070, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x060, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x060, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x060, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x060, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x060, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x060, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x060, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x070, 0x10, 11, 1),
PIN_FIELD_BASE(77, 77, 3, 0x030, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x030, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x030, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x030, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x030, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x030, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x030, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x030, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x030, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x030, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x030, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x030, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x030, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x030, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x030, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x030, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x030, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x030, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x030, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x030, 0x10, 0, 1),
PIN_FIELD_BASE(97, 97, 3, 0x030, 0x10, 20, 1),
PIN_FIELD_BASE(98, 98, 3, 0x030, 0x10, 28, 1),
PIN_FIELD_BASE(99, 99, 3, 0x030, 0x10, 27, 1),
PIN_FIELD_BASE(100, 100, 3, 0x030, 0x10, 30, 1),
PIN_FIELD_BASE(101, 101, 3, 0x030, 0x10, 29, 1),
PIN_FIELD_BASE(102, 102, 3, 0x040, 0x10, 0, 1),
PIN_FIELD_BASE(103, 103, 3, 0x030, 0x10, 31, 1),
PIN_FIELD_BASE(104, 104, 3, 0x030, 0x10, 25, 1),
PIN_FIELD_BASE(105, 105, 3, 0x030, 0x10, 26, 1),
PIN_FIELD_BASE(106, 106, 3, 0x030, 0x10, 23, 1),
PIN_FIELD_BASE(107, 107, 3, 0x030, 0x10, 24, 1),
PIN_FIELD_BASE(108, 108, 3, 0x030, 0x10, 22, 1),
PIN_FIELD_BASE(109, 109, 3, 0x030, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x010, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x010, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x010, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x010, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x010, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x010, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x030, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x030, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x030, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x030, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x030, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x030, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x030, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x030, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x030, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x030, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x030, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x030, 0x10, 10, 1),
PIN_FIELD_BASE(128, 128, 3, 0x040, 0x10, 3, 1),
PIN_FIELD_BASE(129, 129, 3, 0x040, 0x10, 1, 1),
PIN_FIELD_BASE(130, 130, 3, 0x040, 0x10, 4, 1),
PIN_FIELD_BASE(131, 131, 3, 0x040, 0x10, 2, 1),
PIN_FIELD_BASE(132, 132, 6, 0x030, 0x10, 13, 1),
PIN_FIELD_BASE(133, 133, 6, 0x030, 0x10, 12, 1),
PIN_FIELD_BASE(134, 134, 6, 0x030, 0x10, 15, 1),
PIN_FIELD_BASE(135, 135, 6, 0x030, 0x10, 14, 1),
PIN_FIELD_BASE(136, 136, 1, 0x070, 0x10, 13, 1),
PIN_FIELD_BASE(137, 137, 1, 0x070, 0x10, 12, 1),
PIN_FIELD_BASE(138, 138, 1, 0x070, 0x10, 15, 1),
PIN_FIELD_BASE(139, 139, 1, 0x070, 0x10, 14, 1),
PIN_FIELD_BASE(140, 140, 1, 0x070, 0x10, 17, 1),
PIN_FIELD_BASE(141, 141, 1, 0x070, 0x10, 16, 1),
PIN_FIELD_BASE(142, 142, 1, 0x070, 0x10, 19, 1),
PIN_FIELD_BASE(143, 143, 1, 0x070, 0x10, 18, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0d0, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0d0, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0d0, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0d0, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0d0, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0d0, 0x10, 5, 1),
PINS_FIELD_BASE(6, 7, 4, 0x0d0, 0x10, 6, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0d0, 0x10, 12, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0d0, 0x10, 7, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0d0, 0x10, 13, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0d0, 0x10, 8, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0d0, 0x10, 14, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0d0, 0x10, 9, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0d0, 0x10, 15, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0d0, 0x10, 10, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0d0, 0x10, 16, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0d0, 0x10, 11, 1),
PIN_FIELD_BASE(18, 18, 2, 0x090, 0x10, 11, 1),
PIN_FIELD_BASE(19, 19, 2, 0x090, 0x10, 10, 1),
PIN_FIELD_BASE(20, 20, 2, 0x090, 0x10, 9, 1),
PIN_FIELD_BASE(21, 21, 2, 0x090, 0x10, 11, 1),
PIN_FIELD_BASE(22, 22, 2, 0x090, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x090, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x090, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x090, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x090, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x090, 0x10, 5, 1),
PIN_FIELD_BASE(28, 28, 2, 0x090, 0x10, 6, 1),
PIN_FIELD_BASE(29, 29, 2, 0x090, 0x10, 7, 1),
PIN_FIELD_BASE(30, 30, 2, 0x090, 0x10, 8, 1),
PINS_FIELD_BASE(31, 33, 1, 0x0f0, 0x10, 4, 1),
PIN_FIELD_BASE(34, 34, 1, 0x0f0, 0x10, 0, 1),
PIN_FIELD_BASE(35, 35, 1, 0x0f0, 0x10, 1, 1),
PIN_FIELD_BASE(36, 36, 1, 0x0f0, 0x10, 4, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0f0, 0x10, 2, 1),
PINS_FIELD_BASE(38, 39, 1, 0x0f0, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0f0, 0x10, 14, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0f0, 0x10, 13, 1),
PIN_FIELD_BASE(42, 42, 1, 0x0f0, 0x10, 16, 1),
PIN_FIELD_BASE(43, 43, 1, 0x0f0, 0x10, 15, 1),
PIN_FIELD_BASE(44, 44, 1, 0x0f0, 0x10, 25, 1),
PIN_FIELD_BASE(45, 45, 1, 0x0f0, 0x10, 26, 1),
PINS_FIELD_BASE(46, 47, 1, 0x0f0, 0x10, 5, 1),
PINS_FIELD_BASE(48, 51, 1, 0x0f0, 0x10, 6, 1),
PINS_FIELD_BASE(52, 55, 1, 0x0f0, 0x10, 7, 1),
PINS_FIELD_BASE(56, 59, 1, 0x0f0, 0x10, 8, 1),
PINS_FIELD_BASE(60, 63, 1, 0x0f0, 0x10, 9, 1),
PIN_FIELD_BASE(64, 64, 1, 0x0f0, 0x10, 10, 1),
PINS_FIELD_BASE(65, 68, 1, 0x0f0, 0x10, 3, 1),
PINS_FIELD_BASE(69, 71, 1, 0x0f0, 0x10, 10, 1),
PINS_FIELD_BASE(72, 75, 1, 0x0f0, 0x10, 11, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0f0, 0x10, 12, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0e0, 0x10, 0, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0e0, 0x10, 1, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0e0, 0x10, 6, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0e0, 0x10, 7, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0e0, 0x10, 8, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0e0, 0x10, 9, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0e0, 0x10, 10, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0e0, 0x10, 11, 1),
PINS_FIELD_BASE(85, 88, 3, 0x0e0, 0x10, 14, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0e0, 0x10, 2, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0e0, 0x10, 3, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0e0, 0x10, 4, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0e0, 0x10, 5, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0e0, 0x10, 12, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0e0, 0x10, 13, 1),
PINS_FIELD_BASE(95, 98, 3, 0x0e0, 0x10, 15, 1),
PINS_FIELD_BASE(99, 102, 3, 0x0e0, 0x10, 16, 1),
PINS_FIELD_BASE(103, 104, 3, 0x0e0, 0x10, 17, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0e0, 0x10, 18, 1),
PINS_FIELD_BASE(106, 107, 3, 0x0e0, 0x10, 17, 1),
PINS_FIELD_BASE(108, 109, 3, 0x0e0, 0x10, 18, 1),
PIN_FIELD_BASE(110, 110, 5, 0x070, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x070, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x070, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x070, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x070, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x070, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0c0, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0c0, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0c0, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0c0, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0c0, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0c0, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0c0, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0c0, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0c0, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0c0, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0c0, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0c0, 0x10, 10, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0e0, 0x10, 18, 1),
PINS_FIELD_BASE(129, 131, 3, 0x0e0, 0x10, 19, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0c0, 0x10, 13, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0c0, 0x10, 12, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0c0, 0x10, 15, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0c0, 0x10, 14, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0f0, 0x10, 18, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0f0, 0x10, 17, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0f0, 0x10, 20, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0f0, 0x10, 19, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0f0, 0x10, 22, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0f0, 0x10, 21, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0f0, 0x10, 24, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0f0, 0x10, 23, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = {
PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(18, 18, 2, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x00a0, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x00a0, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x00a0, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x00a0, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x00a0, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x00b0, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x00b0, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x00b0, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x00b0, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x00b0, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x00b0, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x00b0, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x00b0, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x00b0, 0x10, 21, 1),
PIN_FIELD_BASE(45, 45, 1, 0x00b0, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 1, 0x00a0, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x00a0, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x00a0, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x00a0, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x00a0, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x00a0, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x00a0, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x00a0, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x00a0, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x00a0, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x00a0, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x00a0, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x00a0, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x00a0, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x00a0, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x00a0, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x00a0, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x00a0, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x00a0, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x00b0, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x00a0, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x00b0, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x00b0, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x00b0, 0x10, 11, 1),
PIN_FIELD_BASE(97, 97, 3, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 3, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(99, 99, 3, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(100, 100, 3, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(101, 101, 3, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(102, 102, 3, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(103, 103, 3, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(108, 108, 3, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(109, 109, 3, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(129, 129, 3, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(130, 130, 3, 0x0070, 0x10, 12, 1),
PIN_FIELD_BASE(131, 131, 3, 0x0070, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(136, 136, 1, 0x00b0, 0x10, 14, 1),
PIN_FIELD_BASE(137, 137, 1, 0x00b0, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x00b0, 0x10, 16, 1),
PIN_FIELD_BASE(139, 139, 1, 0x00b0, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x00b0, 0x10, 18, 1),
PIN_FIELD_BASE(141, 141, 1, 0x00b0, 0x10, 17, 1),
PIN_FIELD_BASE(142, 142, 1, 0x00b0, 0x10, 20, 1),
PIN_FIELD_BASE(143, 143, 1, 0x00b0, 0x10, 19, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = {
PIN_FIELD_BASE(6, 6, 4, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(7, 7, 4, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(8, 8, 4, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(9, 9, 4, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(10, 10, 4, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(11, 11, 4, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(12, 12, 4, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(13, 13, 4, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(14, 14, 4, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(15, 15, 4, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(16, 16, 4, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(17, 17, 4, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(18, 18, 2, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, 2, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(20, 20, 2, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(21, 21, 2, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(26, 26, 2, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(27, 27, 2, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(28, 28, 2, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(29, 29, 2, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(30, 30, 2, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(31, 31, 1, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(32, 32, 1, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(36, 36, 1, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(37, 37, 1, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(38, 38, 1, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(39, 39, 1, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(40, 40, 1, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(41, 41, 1, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(42, 42, 1, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(43, 43, 1, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(44, 44, 1, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 25, 1),
PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 26, 1),
PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 24, 1),
PIN_FIELD_BASE(57, 57, 1, 0x0080, 0x10, 29, 1),
PIN_FIELD_BASE(58, 58, 1, 0x0080, 0x10, 27, 1),
PIN_FIELD_BASE(59, 59, 1, 0x0080, 0x10, 30, 1),
PIN_FIELD_BASE(60, 60, 1, 0x0080, 0x10, 28, 1),
PIN_FIELD_BASE(61, 61, 1, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(62, 62, 1, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(63, 63, 1, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(64, 64, 1, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(65, 65, 1, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(66, 66, 1, 0x0080, 0x10, 31, 1),
PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(69, 69, 1, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(70, 70, 1, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(71, 71, 1, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(72, 72, 1, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(73, 73, 1, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(74, 74, 1, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(75, 75, 1, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(97, 97, 3, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(98, 98, 3, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(99, 99, 3, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(100, 100, 3, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(101, 101, 3, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(102, 102, 3, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(103, 103, 3, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(108, 108, 3, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(109, 109, 3, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(128, 128, 3, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(129, 129, 3, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(130, 130, 3, 0x0050, 0x10, 12, 1),
PIN_FIELD_BASE(131, 131, 3, 0x0050, 0x10, 10, 1),
PIN_FIELD_BASE(132, 132, 6, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(133, 133, 6, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(134, 134, 6, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(136, 136, 1, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(137, 137, 1, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(138, 138, 1, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(139, 139, 1, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(140, 140, 1, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(141, 141, 1, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(142, 142, 1, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(143, 143, 1, 0x0090, 0x10, 19, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0060, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0060, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0060, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0060, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0060, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0060, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0060, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0060, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0060, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0060, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0060, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0060, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0060, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0060, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0060, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0060, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0060, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0020, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0020, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0020, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0020, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0020, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0020, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0050, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0050, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0050, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0050, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0050, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0050, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0050, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0050, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0050, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0050, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0050, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0050, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0080, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0080, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0080, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0080, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0080, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0080, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0080, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0080, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0080, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0030, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0030, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0030, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0030, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0030, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0030, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0070, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0070, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0070, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0070, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0070, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0070, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0070, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0070, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0070, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0070, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0070, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0070, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(77, 77, 3, 0x0090, 0x10, 1, 1),
PIN_FIELD_BASE(78, 78, 3, 0x0090, 0x10, 2, 1),
PIN_FIELD_BASE(79, 79, 3, 0x0090, 0x10, 9, 1),
PIN_FIELD_BASE(80, 80, 3, 0x0090, 0x10, 10, 1),
PIN_FIELD_BASE(81, 81, 3, 0x0090, 0x10, 11, 1),
PIN_FIELD_BASE(82, 82, 3, 0x0090, 0x10, 12, 1),
PIN_FIELD_BASE(83, 83, 3, 0x0090, 0x10, 13, 1),
PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 14, 1),
PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 15, 1),
PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 16, 1),
PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1),
PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1),
PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1),
PIN_FIELD_BASE(90, 90, 3, 0x0090, 0x10, 6, 1),
PIN_FIELD_BASE(91, 91, 3, 0x0090, 0x10, 7, 1),
PIN_FIELD_BASE(92, 92, 3, 0x0090, 0x10, 8, 1),
PIN_FIELD_BASE(93, 93, 3, 0x0090, 0x10, 18, 1),
PIN_FIELD_BASE(94, 94, 3, 0x0090, 0x10, 19, 1),
PIN_FIELD_BASE(95, 95, 3, 0x0090, 0x10, 17, 1),
PIN_FIELD_BASE(96, 96, 3, 0x0090, 0x10, 0, 1),
PIN_FIELD_BASE(104, 104, 3, 0x0090, 0x10, 22, 1),
PIN_FIELD_BASE(105, 105, 3, 0x0090, 0x10, 23, 1),
PIN_FIELD_BASE(106, 106, 3, 0x0090, 0x10, 20, 1),
PIN_FIELD_BASE(107, 107, 3, 0x0090, 0x10, 21, 1),
PIN_FIELD_BASE(110, 110, 5, 0x0040, 0x10, 1, 1),
PIN_FIELD_BASE(111, 111, 5, 0x0040, 0x10, 0, 1),
PIN_FIELD_BASE(112, 112, 5, 0x0040, 0x10, 2, 1),
PIN_FIELD_BASE(113, 113, 5, 0x0040, 0x10, 3, 1),
PIN_FIELD_BASE(114, 114, 5, 0x0040, 0x10, 4, 1),
PIN_FIELD_BASE(115, 115, 5, 0x0040, 0x10, 5, 1),
PIN_FIELD_BASE(116, 116, 6, 0x0080, 0x10, 9, 1),
PIN_FIELD_BASE(117, 117, 6, 0x0080, 0x10, 8, 1),
PIN_FIELD_BASE(118, 118, 6, 0x0080, 0x10, 7, 1),
PIN_FIELD_BASE(119, 119, 6, 0x0080, 0x10, 6, 1),
PIN_FIELD_BASE(120, 120, 6, 0x0080, 0x10, 11, 1),
PIN_FIELD_BASE(121, 121, 6, 0x0080, 0x10, 1, 1),
PIN_FIELD_BASE(122, 122, 6, 0x0080, 0x10, 0, 1),
PIN_FIELD_BASE(123, 123, 6, 0x0080, 0x10, 5, 1),
PIN_FIELD_BASE(124, 124, 6, 0x0080, 0x10, 4, 1),
PIN_FIELD_BASE(125, 125, 6, 0x0080, 0x10, 3, 1),
PIN_FIELD_BASE(126, 126, 6, 0x0080, 0x10, 2, 1),
PIN_FIELD_BASE(127, 127, 6, 0x0080, 0x10, 10, 1),
};
static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = {
PIN_FIELD_BASE(0, 0, 4, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(1, 1, 4, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(2, 2, 4, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(3, 3, 4, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(4, 4, 4, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(5, 5, 4, 0x000, 0x10, 15, 3),
PINS_FIELD_BASE(6, 7, 4, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(8, 8, 4, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(9, 9, 4, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(10, 10, 4, 0x010, 0x10, 9, 3),
PIN_FIELD_BASE(11, 11, 4, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(12, 12, 4, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(13, 13, 4, 0x010, 0x10, 27, 3),
PIN_FIELD_BASE(14, 14, 4, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(15, 15, 4, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(16, 16, 4, 0x010, 0x10, 18, 3),
PIN_FIELD_BASE(17, 17, 4, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(18, 18, 2, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(19, 19, 2, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(20, 20, 2, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(21, 21, 2, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(22, 22, 2, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(23, 23, 2, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(24, 24, 2, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(25, 25, 2, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(26, 26, 2, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(27, 27, 2, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(28, 28, 2, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(29, 29, 2, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(30, 30, 2, 0x000, 0x10, 24, 3),
PINS_FIELD_BASE(31, 33, 1, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(34, 34, 1, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(35, 35, 1, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(36, 36, 1, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(37, 37, 1, 0x010, 0x10, 21, 3),
PINS_FIELD_BASE(38, 39, 1, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(40, 40, 1, 0x010, 0x10, 27, 3),
PIN_FIELD_BASE(41, 41, 1, 0x010, 0x10, 24, 3),
PIN_FIELD_BASE(42, 42, 1, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(43, 43, 1, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(44, 44, 1, 0x030, 0x10, 0, 3),
PIN_FIELD_BASE(45, 45, 1, 0x030, 0x10, 3, 3),
PINS_FIELD_BASE(46, 47, 1, 0x010, 0x10, 3, 3),
PINS_FIELD_BASE(48, 51, 1, 0x010, 0x10, 6, 3),
PINS_FIELD_BASE(52, 55, 1, 0x010, 0x10, 9, 3),
PINS_FIELD_BASE(56, 59, 1, 0x010, 0x10, 12, 3),
PINS_FIELD_BASE(60, 63, 1, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(64, 64, 1, 0x010, 0x10, 18, 3),
PINS_FIELD_BASE(65, 68, 1, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(69, 69, 1, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(70, 70, 1, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(71, 71, 1, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(72, 72, 1, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(73, 73, 1, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(74, 74, 1, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(75, 75, 1, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(76, 76, 1, 0x010, 0x10, 18, 3),
PIN_FIELD_BASE(77, 77, 3, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(78, 78, 3, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(79, 79, 3, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(80, 80, 3, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(81, 81, 3, 0x000, 0x10, 28, 3),
PIN_FIELD_BASE(82, 82, 3, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(83, 83, 3, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(84, 84, 3, 0x010, 0x10, 3, 3),
PINS_FIELD_BASE(85, 88, 3, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(89, 89, 3, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(90, 90, 3, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(91, 91, 3, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(92, 92, 3, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(93, 93, 3, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(94, 94, 3, 0x010, 0x10, 9, 3),
PINS_FIELD_BASE(95, 98, 3, 0x010, 0x10, 18, 3),
PINS_FIELD_BASE(99, 102, 3, 0x010, 0x10, 21, 3),
PINS_FIELD_BASE(103, 104, 3, 0x010, 0x10, 24, 3),
PIN_FIELD_BASE(105, 105, 3, 0x010, 0x10, 27, 3),
PINS_FIELD_BASE(106, 107, 3, 0x010, 0x10, 24, 3),
PINS_FIELD_BASE(108, 109, 3, 0x010, 0x10, 27, 3),
PIN_FIELD_BASE(110, 110, 5, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(111, 111, 5, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(112, 112, 5, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(113, 113, 5, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(114, 114, 5, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(115, 115, 5, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(116, 116, 6, 0x000, 0x10, 27, 3),
PIN_FIELD_BASE(117, 117, 6, 0x000, 0x10, 24, 3),
PIN_FIELD_BASE(118, 118, 6, 0x000, 0x10, 21, 3),
PIN_FIELD_BASE(119, 119, 6, 0x000, 0x10, 18, 3),
PIN_FIELD_BASE(120, 120, 6, 0x010, 0x10, 3, 3),
PIN_FIELD_BASE(121, 121, 6, 0x000, 0x10, 3, 3),
PIN_FIELD_BASE(122, 122, 6, 0x000, 0x10, 0, 3),
PIN_FIELD_BASE(123, 123, 6, 0x000, 0x10, 15, 3),
PIN_FIELD_BASE(124, 124, 6, 0x000, 0x10, 12, 3),
PIN_FIELD_BASE(125, 125, 6, 0x000, 0x10, 9, 3),
PIN_FIELD_BASE(126, 126, 6, 0x000, 0x10, 6, 3),
PIN_FIELD_BASE(127, 127, 6, 0x010, 0x10, 0, 3),
PIN_FIELD_BASE(128, 128, 3, 0x010, 0x10, 27, 3),
PINS_FIELD_BASE(129, 130, 3, 0x020, 0x10, 0, 3),
PINS_FIELD_BASE(131, 131, 3, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(132, 132, 6, 0x010, 0x10, 9, 3),
PIN_FIELD_BASE(133, 133, 6, 0x010, 0x10, 6, 3),
PIN_FIELD_BASE(134, 134, 6, 0x010, 0x10, 15, 3),
PIN_FIELD_BASE(135, 135, 6, 0x010, 0x10, 12, 3),
PIN_FIELD_BASE(136, 136, 1, 0x020, 0x10, 9, 3),
PIN_FIELD_BASE(137, 137, 1, 0x020, 0x10, 6, 3),
PIN_FIELD_BASE(138, 138, 1, 0x020, 0x10, 15, 3),
PIN_FIELD_BASE(139, 139, 1, 0x020, 0x10, 12, 3),
PIN_FIELD_BASE(140, 140, 1, 0x020, 0x10, 21, 3),
PIN_FIELD_BASE(141, 141, 1, 0x020, 0x10, 18, 3),
PIN_FIELD_BASE(142, 142, 1, 0x020, 0x10, 27, 3),
PIN_FIELD_BASE(143, 143, 1, 0x020, 0x10, 24, 3),
};
static const struct mtk_pin_field_calc mt8195_pin_drv_adv_range[] = {
PIN_FIELD_BASE(8, 8, 4, 0x020, 0x10, 15, 3),
PIN_FIELD_BASE(9, 9, 4, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(10, 10, 4, 0x020, 0x10, 18, 3),
PIN_FIELD_BASE(11, 11, 4, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(12, 12, 4, 0x020, 0x10, 21, 3),
PIN_FIELD_BASE(13, 13, 4, 0x020, 0x10, 6, 3),
PIN_FIELD_BASE(14, 14, 4, 0x020, 0x10, 24, 3),
PIN_FIELD_BASE(15, 15, 4, 0x020, 0x10, 9, 3),
PIN_FIELD_BASE(16, 16, 4, 0x020, 0x10, 27, 3),
PIN_FIELD_BASE(17, 17, 4, 0x020, 0x10, 12, 3),
PIN_FIELD_BASE(29, 29, 2, 0x020, 0x10, 0, 3),
PIN_FIELD_BASE(30, 30, 2, 0x020, 0x10, 3, 3),
PIN_FIELD_BASE(34, 34, 1, 0x040, 0x10, 0, 3),
PIN_FIELD_BASE(35, 35, 1, 0x040, 0x10, 3, 3),
PIN_FIELD_BASE(44, 44, 1, 0x040, 0x10, 6, 3),
PIN_FIELD_BASE(45, 45, 1, 0x040, 0x10, 9, 3),
};
static const struct mtk_pin_reg_calc mt8195_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range),
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range),
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range),
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range),
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range),
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range),
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range),
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range),
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range),
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8195_pin_drv_adv_range),
};
static const char * const mt8195_pinctrl_register_base_names[] = {
"iocfg0", "iocfg_bm", "iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_rb", "iocfg_tl",
};
static const struct mtk_eint_hw mt8195_eint_hw = {
.port_mask = 0xf,
.ports = 7,
.ap_num = 225,
.db_cnt = 32,
};
static const struct mtk_pin_soc mt8195_data = {
.reg_cal = mt8195_reg_cals,
.pins = mtk_pins_mt8195,
.npins = ARRAY_SIZE(mtk_pins_mt8195),
.ngrps = ARRAY_SIZE(mtk_pins_mt8195),
.eint_hw = &mt8195_eint_hw,
.nfuncs = 8,
.gpio_m = 0,
.base_names = mt8195_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names),
.bias_set_combo = mtk_pinconf_bias_set_combo,
.bias_get_combo = mtk_pinconf_bias_get_combo,
.drive_set = mtk_pinconf_drive_set_rev1,
.drive_get = mtk_pinconf_drive_get_rev1,
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
};
static const struct of_device_id mt8195_pinctrl_of_match[] = {
{ .compatible = "mediatek,mt8195-pinctrl", },
{ }
};
static int mt8195_pinctrl_probe(struct platform_device *pdev)
{
return mtk_paris_pinctrl_probe(pdev, &mt8195_data);
}
static struct platform_driver mt8195_pinctrl_driver = {
.driver = {
.name = "mt8195-pinctrl",
.of_match_table = mt8195_pinctrl_of_match,
},
.probe = mt8195_pinctrl_probe,
};
static int __init mt8195_pinctrl_init(void)
{
return platform_driver_register(&mt8195_pinctrl_driver);
}
arch_initcall(mt8195_pinctrl_init);

19
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
View File

@ -57,11 +57,16 @@ static u32 mtk_r32(struct mtk_pinctrl *pctl, u8 i, u32 reg)
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set)
{
u32 val;
unsigned long flags;
spin_lock_irqsave(&pctl->lock, flags);
val = mtk_r32(pctl, i, reg);
val &= ~mask;
val |= set;
mtk_w32(pctl, i, reg, val);
spin_unlock_irqrestore(&pctl->lock, flags);
}
static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw,
@ -1027,6 +1032,20 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get);
int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg)
{
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, arg);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set_raw);
int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val)
{
return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV_ADV, val);
}
EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get_raw);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs");

7
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
View File

@ -66,6 +66,7 @@ enum {
PINCTRL_PIN_REG_DRV_EN,
PINCTRL_PIN_REG_DRV_E0,
PINCTRL_PIN_REG_DRV_E1,
PINCTRL_PIN_REG_DRV_ADV,
PINCTRL_PIN_REG_MAX,
};
@ -251,6 +252,8 @@ struct mtk_pinctrl {
struct mtk_eint *eint;
struct mtk_pinctrl_group *groups;
const char **grp_names;
/* lock pin's register resource to avoid multiple threads issue*/
spinlock_t lock;
};
void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
@ -314,6 +317,10 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
int mtk_pinconf_adv_drive_set_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 arg);
int mtk_pinconf_adv_drive_get_raw(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */

1669
drivers/pinctrl/mediatek/pinctrl-mtk-mt8195.h Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -970,6 +970,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev,
hw->nbase = hw->soc->nbase_names;
spin_lock_init(&hw->lock);
err = mtk_pctrl_build_state(pdev);
if (err) {
dev_err(&pdev->dev, "build state failed: %d\n", err);

4
drivers/pinctrl/mvebu/pinctrl-armada-cp110.c
View File

@ -519,13 +519,13 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = {
MPP_FUNCTION(4, "synce1", "clk"),
MPP_FUNCTION(8, "led", "data"),
MPP_FUNCTION(10, "sdio", "hw_rst"),
MPP_FUNCTION(11, "sdio", "wr_protect")),
MPP_FUNCTION(11, "sdio_wp", "wr_protect")),
MPP_MODE(55,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(1, "ge1", "rxctl_rxdv"),
MPP_FUNCTION(3, "ptp", "pulse"),
MPP_FUNCTION(10, "sdio", "led"),
MPP_FUNCTION(11, "sdio", "card_detect")),
MPP_FUNCTION(11, "sdio_cd", "card_detect")),
MPP_MODE(56,
MPP_FUNCTION(0, "gpio", NULL),
MPP_FUNCTION(4, "tdm", "drx"),

6
drivers/pinctrl/pinconf-generic.c
View File

@ -43,7 +43,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_MODE_LOW_POWER, "pin low power", "mode", true),
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
@ -174,8 +174,8 @@ static const struct pinconf_generic_params dt_params[] = {
{ "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
{ "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
{ "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
{ "low-power-disable", PIN_CONFIG_MODE_LOW_POWER, 0 },
{ "low-power-enable", PIN_CONFIG_MODE_LOW_POWER, 1 },
{ "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 },
{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
{ "output-high", PIN_CONFIG_OUTPUT, 1, },

4
drivers/pinctrl/pinconf.c
View File

@ -370,9 +370,9 @@ DEFINE_SHOW_ATTRIBUTE(pinconf_groups);
void pinconf_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinconf-pins", S_IFREG | S_IRUGO,
debugfs_create_file("pinconf-pins", 0444,
devroot, pctldev, &pinconf_pins_fops);
debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO,
debugfs_create_file("pinconf-groups", 0444,
devroot, pctldev, &pinconf_groups_fops);
}

8
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
conf = atmel_pin_config_read(pctldev, pin_id);
/* Keep slew rate enabled by default. */
if (atmel_pioctrl->slew_rate_support)
conf |= ATMEL_PIO_SR_MASK;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
__func__, pin_id, configs[i]);
/* Keep slew rate enabled by default. */
if (atmel_pioctrl->slew_rate_support)
conf |= ATMEL_PIO_SR_MASK;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
conf &= (~ATMEL_PIO_PUEN_MASK);

16
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -628,7 +628,8 @@ static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
break;
default:
return -EINVAL;
of_node_put(np);
return -EINVAL;
}
i++;
}
@ -707,34 +708,42 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
group.num_pins = of_property_count_u32_elems(np, "pins");
if (group.num_pins < 0) {
dev_err(dev, "No pins in the group: %s\n", prop->name);
of_node_put(np);
return -EINVAL;
}
group.name = prop->value;
group.pins = devm_kcalloc(dev, group.num_pins,
sizeof(*(group.pins)), GFP_KERNEL);
if (!group.pins)
if (!group.pins) {
of_node_put(np);
return -ENOMEM;
}
pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
GFP_KERNEL);
if (!pinmux)
if (!pinmux) {
of_node_put(np);
return -ENOMEM;
}
for (j = 0; j < group.num_pins; j++) {
if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
dev_err(dev, "Group %s: Read intel pins id failed\n",
group.name);
of_node_put(np);
return -EINVAL;
}
if (pin_id >= drvdata->pctl_desc.npins) {
dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
group.name, j, pin_id);
of_node_put(np);
return -EINVAL;
}
group.pins[j] = pin_id;
if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
dev_err(dev, "Group %s: Read intel pinmux id failed\n",
group.name);
of_node_put(np);
return -EINVAL;
}
pinmux[j] = pinmux_id;
@ -745,6 +754,7 @@ static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
pinmux);
if (err < 0) {
dev_err(dev, "Failed to register group %s\n", group.name);
of_node_put(np);
return err;
}
memset(&group, 0, sizeof(group));

1639
drivers/pinctrl/pinctrl-ingenic.c
View File

File diff suppressed because it is too large Load Diff

1
drivers/pinctrl/pinctrl-k210.c
View File

@ -15,7 +15,6 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/io.h>
#include <dt-bindings/pinctrl/k210-fpioa.h>

4
drivers/pinctrl/pinctrl-lpc18xx.c
View File

@ -646,7 +646,7 @@ static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params
static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
{
switch (param) {
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
if (reg & LPC18XX_SCU_USB1_EPWR)
*arg = 0;
else
@ -904,7 +904,7 @@ static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
u32 param_val, u32 *reg)
{
switch (param) {
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
if (param_val)
*reg &= ~LPC18XX_SCU_USB1_EPWR;
else

956
drivers/pinctrl/pinctrl-rockchip.c
View File

File diff suppressed because it is too large Load Diff

71
drivers/pinctrl/pinctrl-single.c
View File

@ -270,20 +270,44 @@ static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
writel(val, reg);
}
static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
unsigned int pin)
{
unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
if (pcs->bits_per_mux) {
unsigned int pin_offset_bytes;
pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
return (pin_offset_bytes / mux_bytes) * mux_bytes;
}
return pin * mux_bytes;
}
static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
unsigned int pin)
{
return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
}
static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s,
unsigned pin)
{
struct pcs_device *pcs;
unsigned val, mux_bytes;
unsigned int val;
unsigned long offset;
size_t pa;
pcs = pinctrl_dev_get_drvdata(pctldev);
mux_bytes = pcs->width / BITS_PER_BYTE;
offset = pin * mux_bytes;
offset = pcs_pin_reg_offset_get(pcs, pin);
val = pcs->read(pcs->base + offset);
if (pcs->bits_per_mux)
val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
pa = pcs->res->start + offset;
seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
@ -384,7 +408,6 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
struct pcs_gpiofunc_range *frange = NULL;
struct list_head *pos, *tmp;
int mux_bytes = 0;
unsigned data;
/* If function mask is null, return directly. */
@ -392,29 +415,27 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
u32 offset;
frange = list_entry(pos, struct pcs_gpiofunc_range, node);
if (pin >= frange->offset + frange->npins
|| pin < frange->offset)
continue;
mux_bytes = pcs->width / BITS_PER_BYTE;
offset = pcs_pin_reg_offset_get(pcs, pin);
if (pcs->bits_per_mux) {
int byte_num, offset, pin_shift;
byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
offset = (byte_num / mux_bytes) * mux_bytes;
pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
pcs->bits_per_pin;
int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
data = pcs->read(pcs->base + offset);
data &= ~(pcs->fmask << pin_shift);
data |= frange->gpiofunc << pin_shift;
pcs->write(data, pcs->base + offset);
} else {
data = pcs->read(pcs->base + pin * mux_bytes);
data = pcs->read(pcs->base + offset);
data &= ~pcs->fmask;
data |= frange->gpiofunc;
pcs->write(data, pcs->base + pin * mux_bytes);
pcs->write(data, pcs->base + offset);
}
break;
}
@ -512,7 +533,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
default:
*config = data;
break;
@ -550,7 +571,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_INPUT_SCHMITT:
case PIN_CONFIG_DRIVE_STRENGTH:
case PIN_CONFIG_SLEW_RATE:
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
shift = ffs(func->conf[i].mask) - 1;
data &= ~func->conf[i].mask;
data |= (arg << shift) & func->conf[i].mask;
@ -656,10 +677,8 @@ static const struct pinconf_ops pcs_pinconf_ops = {
* pcs_add_pin() - add a pin to the static per controller pin array
* @pcs: pcs driver instance
* @offset: register offset from base
* @pin_pos: unused
*/
static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
unsigned pin_pos)
static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
{
struct pcs_soc_data *pcs_soc = &pcs->socdata;
struct pinctrl_pin_desc *pin;
@ -703,14 +722,12 @@ static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
static int pcs_allocate_pin_table(struct pcs_device *pcs)
{
int mux_bytes, nr_pins, i;
int num_pins_in_register = 0;
mux_bytes = pcs->width / BITS_PER_BYTE;
if (pcs->bits_per_mux) {
pcs->bits_per_pin = fls(pcs->fmask);
nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
num_pins_in_register = pcs->width / pcs->bits_per_pin;
} else {
nr_pins = pcs->size / mux_bytes;
}
@ -728,17 +745,9 @@ static int pcs_allocate_pin_table(struct pcs_device *pcs)
for (i = 0; i < pcs->desc.npins; i++) {
unsigned offset;
int res;
int byte_num;
int pin_pos = 0;
if (pcs->bits_per_mux) {
byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
offset = (byte_num / mux_bytes) * mux_bytes;
pin_pos = i % num_pins_in_register;
} else {
offset = i * mux_bytes;
}
res = pcs_add_pin(pcs, offset, pin_pos);
offset = pcs_pin_reg_offset_get(pcs, i);
res = pcs_add_pin(pcs, offset);
if (res < 0) {
dev_err(pcs->dev, "error adding pins: %i\n", res);
return res;
@ -910,7 +919,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
{ "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
{ "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
{ "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
{ "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
{ "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, },
};
static const struct pcs_conf_type prop4[] = {
{ "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },

4
drivers/pinctrl/pinctrl-zynq.c
View File

@ -1016,7 +1016,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
case PIN_CONFIG_SLEW_RATE:
arg = !!(reg & ZYNQ_PINCONF_SPEED);
break;
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
{
enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
@ -1087,7 +1087,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
break;
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
if (arg)
reg |= ZYNQ_PINCONF_DISABLE_RECVR;
else

906
drivers/pinctrl/pinctrl-zynqmp.c Normal file
View File

@ -0,0 +1,906 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ZynqMP pin controller
*
* Copyright (C) 2020 Xilinx, Inc.
*
* Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
* Rajan Vaja <rajan.vaja@xilinx.com>
*/
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/firmware/xlnx-zynqmp.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "pinctrl-utils.h"
#define ZYNQMP_PIN_PREFIX "MIO"
#define PINCTRL_GET_FUNC_NAME_RESP_LEN 16
#define MAX_FUNC_NAME_LEN 16
#define MAX_GROUP_PIN 50
#define MAX_PIN_GROUPS 50
#define END_OF_FUNCTIONS "END_OF_FUNCTIONS"
#define NUM_GROUPS_PER_RESP 6
#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12
#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12
#define NA_GROUP 0xFFFF
#define RESERVED_GROUP 0xFFFE
#define DRIVE_STRENGTH_2MA 2
#define DRIVE_STRENGTH_4MA 4
#define DRIVE_STRENGTH_8MA 8
#define DRIVE_STRENGTH_12MA 12
/**
* struct zynqmp_pmux_function - a pinmux function
* @name: Name of the pin mux function
* @groups: List of pin groups for this function
* @ngroups: Number of entries in @groups
* @node: Firmware node matching with the function
*
* This structure holds information about pin control function
* and function group names supporting that function.
*/
struct zynqmp_pmux_function {
char name[MAX_FUNC_NAME_LEN];
const char * const *groups;
unsigned int ngroups;
};
/**
* struct zynqmp_pinctrl - driver data
* @pctrl: Pin control device
* @groups: Pin groups
* @ngroups: Number of @groups
* @funcs: Pin mux functions
* @nfuncs: Number of @funcs
*
* This struct is stored as driver data and used to retrieve
* information regarding pin control functions, groups and
* group pins.
*/
struct zynqmp_pinctrl {
struct pinctrl_dev *pctrl;
const struct zynqmp_pctrl_group *groups;
unsigned int ngroups;
const struct zynqmp_pmux_function *funcs;
unsigned int nfuncs;
};
/**
* struct zynqmp_pctrl_group - Pin control group info
* @name: Group name
* @pins: Group pin numbers
* @npins: Number of pins in the group
*/
struct zynqmp_pctrl_group {
const char *name;
unsigned int pins[MAX_GROUP_PIN];
unsigned int npins;
};
static struct pinctrl_desc zynqmp_desc;
static int zynqmp_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->ngroups;
}
static const char *zynqmp_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->groups[selector].name;
}
static int zynqmp_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int selector,
const unsigned int **pins,
unsigned int *npins)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*pins = pctrl->groups[selector].pins;
*npins = pctrl->groups[selector].npins;
return 0;
}
static const struct pinctrl_ops zynqmp_pctrl_ops = {
.get_groups_count = zynqmp_pctrl_get_groups_count,
.get_group_name = zynqmp_pctrl_get_group_name,
.get_group_pins = zynqmp_pctrl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
};
static int zynqmp_pinmux_request_pin(struct pinctrl_dev *pctldev,
unsigned int pin)
{
int ret;
ret = zynqmp_pm_pinctrl_request(pin);
if (ret) {
dev_err(pctldev->dev, "request failed for pin %u\n", pin);
return ret;
}
return 0;
}
static int zynqmp_pmux_get_functions_count(struct pinctrl_dev *pctldev)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->nfuncs;
}
static const char *zynqmp_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned int selector)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
return pctrl->funcs[selector].name;
}
/**
* zynqmp_pmux_get_function_groups() - Get groups for the function
* @pctldev: Pincontrol device pointer.
* @selector: Function ID
* @groups: Group names.
* @num_groups: Number of function groups.
*
* Get function's group count and group names.
*/
static int zynqmp_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctrl->funcs[selector].groups;
*num_groups = pctrl->funcs[selector].ngroups;
return 0;
}
/**
* zynqmp_pinmux_set_mux() - Set requested function for the group
* @pctldev: Pincontrol device pointer.
* @function: Function ID.
* @group: Group ID.
*
* Loop through all pins of the group and call firmware API
* to set requested function for all pins in the group.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[group];
int ret, i;
for (i = 0; i < pgrp->npins; i++) {
unsigned int pin = pgrp->pins[i];
ret = zynqmp_pm_pinctrl_set_function(pin, function);
if (ret) {
dev_err(pctldev->dev, "set mux failed for pin %u\n",
pin);
return ret;
}
}
return 0;
}
static int zynqmp_pinmux_release_pin(struct pinctrl_dev *pctldev,
unsigned int pin)
{
int ret;
ret = zynqmp_pm_pinctrl_release(pin);
if (ret) {
dev_err(pctldev->dev, "free pin failed for pin %u\n",
pin);
return ret;
}
return 0;
}
static const struct pinmux_ops zynqmp_pinmux_ops = {
.request = zynqmp_pinmux_request_pin,
.get_functions_count = zynqmp_pmux_get_functions_count,
.get_function_name = zynqmp_pmux_get_function_name,
.get_function_groups = zynqmp_pmux_get_function_groups,
.set_mux = zynqmp_pinmux_set_mux,
.free = zynqmp_pinmux_release_pin,
};
/**
* zynqmp_pinconf_cfg_get() - get config value for the pin
* @pctldev: Pin control device pointer.
* @pin: Pin number.
* @config: Value of config param.
*
* Get value of the requested configuration parameter for the
* given pin.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_cfg_get(struct pinctrl_dev *pctldev,
unsigned int pin,
unsigned long *config)
{
unsigned int arg, param = pinconf_to_config_param(*config);
int ret;
if (pin >= zynqmp_desc.npins)
return -EOPNOTSUPP;
switch (param) {
case PIN_CONFIG_SLEW_RATE:
param = PM_PINCTRL_CONFIG_SLEW_RATE;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_PULL_UP)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_PULL_DOWN)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_BIAS_DISABLE:
param = PM_PINCTRL_CONFIG_BIAS_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
if (arg != PM_PINCTRL_BIAS_DISABLE)
return -EINVAL;
arg = 1;
break;
case PIN_CONFIG_POWER_SOURCE:
param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &arg);
switch (arg) {
case PM_PINCTRL_DRIVE_STRENGTH_2MA:
arg = DRIVE_STRENGTH_2MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_4MA:
arg = DRIVE_STRENGTH_4MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_8MA:
arg = DRIVE_STRENGTH_8MA;
break;
case PM_PINCTRL_DRIVE_STRENGTH_12MA:
arg = DRIVE_STRENGTH_12MA;
break;
default:
/* Invalid drive strength */
dev_warn(pctldev->dev,
"Invalid drive strength for pin %d\n",
pin);
return -EINVAL;
}
break;
default:
ret = -EOPNOTSUPP;
break;
}
if (ret)
return ret;
param = pinconf_to_config_param(*config);
*config = pinconf_to_config_packed(param, arg);
return 0;
}
/**
* zynqmp_pinconf_cfg_set() - Set requested config for the pin
* @pctldev: Pincontrol device pointer.
* @pin: Pin number.
* @configs: Configuration to set.
* @num_configs: Number of configurations.
*
* Loop through all configurations and call firmware API
* to set requested configurations for the pin.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
if (pin >= zynqmp_desc.npins)
return -EOPNOTSUPP;
for (i = 0; i < num_configs; i++) {
unsigned int param = pinconf_to_config_param(configs[i]);
unsigned int arg = pinconf_to_config_argument(configs[i]);
unsigned int value;
switch (param) {
case PIN_CONFIG_SLEW_RATE:
param = PM_PINCTRL_CONFIG_SLEW_RATE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
arg = PM_PINCTRL_BIAS_PULL_UP;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
param = PM_PINCTRL_CONFIG_PULL_CTRL;
arg = PM_PINCTRL_BIAS_PULL_DOWN;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_BIAS_DISABLE:
param = PM_PINCTRL_CONFIG_BIAS_STATUS;
arg = PM_PINCTRL_BIAS_DISABLE;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
param = PM_PINCTRL_CONFIG_SCHMITT_CMOS;
ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
switch (arg) {
case DRIVE_STRENGTH_2MA:
value = PM_PINCTRL_DRIVE_STRENGTH_2MA;
break;
case DRIVE_STRENGTH_4MA:
value = PM_PINCTRL_DRIVE_STRENGTH_4MA;
break;
case DRIVE_STRENGTH_8MA:
value = PM_PINCTRL_DRIVE_STRENGTH_8MA;
break;
case DRIVE_STRENGTH_12MA:
value = PM_PINCTRL_DRIVE_STRENGTH_12MA;
break;
default:
/* Invalid drive strength */
dev_warn(pctldev->dev,
"Invalid drive strength for pin %d\n",
pin);
return -EINVAL;
}
param = PM_PINCTRL_CONFIG_DRIVE_STRENGTH;
ret = zynqmp_pm_pinctrl_set_config(pin, param, value);
break;
case PIN_CONFIG_POWER_SOURCE:
param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS;
ret = zynqmp_pm_pinctrl_get_config(pin, param, &value);
if (arg != value)
dev_warn(pctldev->dev,
"Invalid IO Standard requested for pin %d\n",
pin);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
case PIN_CONFIG_MODE_LOW_POWER:
/*
* These cases are mentioned in dts but configurable
* registers are unknown. So falling through to ignore
* boot time warnings as of now.
*/
ret = 0;
break;
default:
dev_warn(pctldev->dev,
"unsupported configuration parameter '%u'\n",
param);
ret = -EOPNOTSUPP;
break;
}
param = pinconf_to_config_param(configs[i]);
arg = pinconf_to_config_argument(configs[i]);
if (ret)
dev_warn(pctldev->dev,
"failed to set: pin %u param %u value %u\n",
pin, param, arg);
}
return 0;
}
/**
* zynqmp_pinconf_group_set() - Set requested config for the group
* @pctldev: Pincontrol device pointer.
* @selector: Group ID.
* @configs: Configuration to set.
* @num_configs: Number of configurations.
*
* Call function to set configs for each pin in the group.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned int selector,
unsigned long *configs,
unsigned int num_configs)
{
int i, ret;
struct zynqmp_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct zynqmp_pctrl_group *pgrp = &pctrl->groups[selector];
for (i = 0; i < pgrp->npins; i++) {
ret = zynqmp_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
num_configs);
if (ret)
return ret;
}
return 0;
}
static const struct pinconf_ops zynqmp_pinconf_ops = {
.is_generic = true,
.pin_config_get = zynqmp_pinconf_cfg_get,
.pin_config_set = zynqmp_pinconf_cfg_set,
.pin_config_group_set = zynqmp_pinconf_group_set,
};
static struct pinctrl_desc zynqmp_desc = {
.name = "zynqmp_pinctrl",
.owner = THIS_MODULE,
.pctlops = &zynqmp_pctrl_ops,
.pmxops = &zynqmp_pinmux_ops,
.confops = &zynqmp_pinconf_ops,
};
static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_GROUPS;
qdata.arg1 = fid;
qdata.arg2 = index;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
memcpy(groups, &payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN);
return ret;
}
static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS;
qdata.arg1 = fid;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*ngroups = payload[1];
return ret;
}
/**
* zynqmp_pinctrl_prepare_func_groups() - prepare function and groups data
* @dev: Device pointer.
* @fid: Function ID.
* @func: Function data.
* @groups: Groups data.
*
* Query firmware to get group IDs for each function. Firmware returns
* group IDs. Based on group index for the function, group names in
* the function are stored. For example, the first group in "eth0" function
* is named as "eth0_0" and second group as "eth0_1" and so on.
*
* Based on the group ID received from the firmware, function stores name of
* the group for that group ID. For example, if "eth0" first group ID
* is x, groups[x] name will be stored as "eth0_0".
*
* Once done for each function, each function would have its group names
* and each groups would also have their names.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid,
struct zynqmp_pmux_function *func,
struct zynqmp_pctrl_group *groups)
{
u16 resp[NUM_GROUPS_PER_RESP] = {0};
const char **fgroups;
int ret = 0, index, i;
fgroups = devm_kzalloc(dev, sizeof(*fgroups) * func->ngroups, GFP_KERNEL);
if (!fgroups)
return -ENOMEM;
for (index = 0; index < func->ngroups; index += NUM_GROUPS_PER_RESP) {
ret = zynqmp_pinctrl_get_function_groups(fid, index, resp);
if (ret)
return ret;
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
if (resp[i] == NA_GROUP)
goto done;
if (resp[i] == RESERVED_GROUP)
continue;
fgroups[index + i] = devm_kasprintf(dev, GFP_KERNEL,
"%s_%d_grp",
func->name,
index + i);
if (!fgroups[index + i])
return -ENOMEM;
groups[resp[i]].name = devm_kasprintf(dev, GFP_KERNEL,
"%s_%d_grp",
func->name,
index + i);
if (!groups[resp[i]].name)
return -ENOMEM;
}
}
done:
func->groups = fgroups;
return ret;
}
static void zynqmp_pinctrl_get_function_name(u32 fid, char *name)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
qdata.qid = PM_QID_PINCTRL_GET_FUNCTION_NAME;
qdata.arg1 = fid;
/*
* Name of the function is maximum 16 bytes and cannot
* accommodate the return value in SMC buffers, hence ignoring
* the return value for this specific qid.
*/
zynqmp_pm_query_data(qdata, payload);
memcpy(name, payload, PINCTRL_GET_FUNC_NAME_RESP_LEN);
}
static int zynqmp_pinctrl_get_num_functions(unsigned int *nfuncs)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_FUNCTIONS;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*nfuncs = payload[1];
return ret;
}
static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_PIN_GROUPS;
qdata.arg1 = pin;
qdata.arg2 = index;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
memcpy(groups, &payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN);
return ret;
}
static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group,
unsigned int pin)
{
group->pins[group->npins++] = pin;
}
/**
* zynqmp_pinctrl_create_pin_groups() - assign pins to respective groups
* @dev: Device pointer.
* @groups: Groups data.
* @pin: Pin number.
*
* Query firmware to get groups available for the given pin.
* Based on the firmware response(group IDs for the pin), add
* pin number to the respective group's pin array.
*
* Once all pins are queries, each groups would have its number
* of pins and pin numbers data.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_create_pin_groups(struct device *dev,
struct zynqmp_pctrl_group *groups,
unsigned int pin)
{
u16 resp[NUM_GROUPS_PER_RESP] = {0};
int ret, i, index = 0;
do {
ret = zynqmp_pinctrl_get_pin_groups(pin, index, resp);
if (ret)
return ret;
for (i = 0; i < NUM_GROUPS_PER_RESP; i++) {
if (resp[i] == NA_GROUP)
return ret;
if (resp[i] == RESERVED_GROUP)
continue;
zynqmp_pinctrl_group_add_pin(&groups[resp[i]], pin);
}
index += NUM_GROUPS_PER_RESP;
} while (index <= MAX_PIN_GROUPS);
return ret;
}
/**
* zynqmp_pinctrl_prepare_group_pins() - prepare each group's pin data
* @dev: Device pointer.
* @groups: Groups data.
* @ngroups: Number of groups.
*
* Prepare pin number and number of pins data for each pins.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_group_pins(struct device *dev,
struct zynqmp_pctrl_group *groups,
unsigned int ngroups)
{
unsigned int pin;
int ret;
for (pin = 0; pin < zynqmp_desc.npins; pin++) {
ret = zynqmp_pinctrl_create_pin_groups(dev, groups, pin);
if (ret)
return ret;
}
return 0;
}
/**
* zynqmp_pinctrl_prepare_function_info() - prepare function info
* @dev: Device pointer.
* @pctrl: Pin control driver data.
*
* Query firmware for functions, groups and pin information and
* prepare pin control driver data.
*
* Query number of functions and number of function groups (number
* of groups in given function) to allocate required memory buffers
* for functions and groups. Once buffers are allocated to store
* functions and groups data, query and store required information
* (number of groups and group names for each function, number of
* pins and pin numbers for each group).
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_function_info(struct device *dev,
struct zynqmp_pinctrl *pctrl)
{
struct zynqmp_pmux_function *funcs;
struct zynqmp_pctrl_group *groups;
int ret, i;
ret = zynqmp_pinctrl_get_num_functions(&pctrl->nfuncs);
if (ret)
return ret;
funcs = devm_kzalloc(dev, sizeof(*funcs) * pctrl->nfuncs, GFP_KERNEL);
if (!funcs)
return -ENOMEM;
for (i = 0; i < pctrl->nfuncs; i++) {
zynqmp_pinctrl_get_function_name(i, funcs[i].name);
ret = zynqmp_pinctrl_get_func_num_groups(i, &funcs[i].ngroups);
if (ret)
return ret;
pctrl->ngroups += funcs[i].ngroups;
}
groups = devm_kzalloc(dev, sizeof(*groups) * pctrl->ngroups, GFP_KERNEL);
if (!groups)
return -ENOMEM;
for (i = 0; i < pctrl->nfuncs; i++) {
ret = zynqmp_pinctrl_prepare_func_groups(dev, i, &funcs[i],
groups);
if (ret)
return ret;
}
ret = zynqmp_pinctrl_prepare_group_pins(dev, groups, pctrl->ngroups);
if (ret)
return ret;
pctrl->funcs = funcs;
pctrl->groups = groups;
return ret;
}
static int zynqmp_pinctrl_get_num_pins(unsigned int *npins)
{
struct zynqmp_pm_query_data qdata = {0};
u32 payload[PAYLOAD_ARG_CNT];
int ret;
qdata.qid = PM_QID_PINCTRL_GET_NUM_PINS;
ret = zynqmp_pm_query_data(qdata, payload);
if (ret)
return ret;
*npins = payload[1];
return ret;
}
/**
* zynqmp_pinctrl_prepare_pin_desc() - prepare pin description info
* @dev: Device pointer.
* @zynqmp_pins: Pin information.
* @npins: Number of pins.
*
* Query number of pins information from firmware and prepare pin
* description containing pin number and pin name.
*
* Return: 0 on success else error code.
*/
static int zynqmp_pinctrl_prepare_pin_desc(struct device *dev,
const struct pinctrl_pin_desc
**zynqmp_pins,
unsigned int *npins)
{
struct pinctrl_pin_desc *pins, *pin;
int ret;
int i;
ret = zynqmp_pinctrl_get_num_pins(npins);
if (ret)
return ret;
pins = devm_kzalloc(dev, sizeof(*pins) * *npins, GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < *npins; i++) {
pin = &pins[i];
pin->number = i;
pin->name = devm_kasprintf(dev, GFP_KERNEL, "%s%d",
ZYNQMP_PIN_PREFIX, i);
if (!pin->name)
return -ENOMEM;
}
*zynqmp_pins = pins;
return 0;
}
static int zynqmp_pinctrl_probe(struct platform_device *pdev)
{
struct zynqmp_pinctrl *pctrl;
int ret;
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
if (!pctrl)
return -ENOMEM;
ret = zynqmp_pinctrl_prepare_pin_desc(&pdev->dev,
&zynqmp_desc.pins,
&zynqmp_desc.npins);
if (ret) {
dev_err(&pdev->dev, "pin desc prepare fail with %d\n",
ret);
return ret;
}
ret = zynqmp_pinctrl_prepare_function_info(&pdev->dev, pctrl);
if (ret) {
dev_err(&pdev->dev, "function info prepare fail with %d\n",
ret);
return ret;
}
pctrl->pctrl = pinctrl_register(&zynqmp_desc, &pdev->dev, pctrl);
if (IS_ERR(pctrl->pctrl))
return PTR_ERR(pctrl->pctrl);
platform_set_drvdata(pdev, pctrl);
return ret;
}
static int zynqmp_pinctrl_remove(struct platform_device *pdev)
{
struct zynqmp_pinctrl *pctrl = platform_get_drvdata(pdev);
pinctrl_unregister(pctrl->pctrl);
return 0;
}
static const struct of_device_id zynqmp_pinctrl_of_match[] = {
{ .compatible = "xlnx,zynqmp-pinctrl" },
{ }
};
MODULE_DEVICE_TABLE(of, zynqmp_pinctrl_of_match);
static struct platform_driver zynqmp_pinctrl_driver = {
.driver = {
.name = "zynqmp-pinctrl",
.of_match_table = zynqmp_pinctrl_of_match,
},
.probe = zynqmp_pinctrl_probe,
.remove = zynqmp_pinctrl_remove,
};
module_platform_driver(zynqmp_pinctrl_driver);
MODULE_AUTHOR("Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>");
MODULE_DESCRIPTION("ZynqMP Pin Controller Driver");
MODULE_LICENSE("GPL v2");

106
drivers/pinctrl/pinmux.c
View File

@ -12,6 +12,7 @@
*/
#define pr_fmt(fmt) "pinmux core: " fmt
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
@ -673,13 +674,114 @@ void pinmux_show_setting(struct seq_file *s,
DEFINE_SHOW_ATTRIBUTE(pinmux_functions);
DEFINE_SHOW_ATTRIBUTE(pinmux_pins);
#define PINMUX_SELECT_MAX 128
static ssize_t pinmux_select(struct file *file, const char __user *user_buf,
size_t len, loff_t *ppos)
{
struct seq_file *sfile = file->private_data;
struct pinctrl_dev *pctldev = sfile->private;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
const char *const *groups;
char *buf, *gname, *fname;
unsigned int num_groups;
int fsel, gsel, ret;
if (len > PINMUX_SELECT_MAX)
return -ENOMEM;
buf = kzalloc(PINMUX_SELECT_MAX, GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = strncpy_from_user(buf, user_buf, PINMUX_SELECT_MAX);
if (ret < 0)
goto exit_free_buf;
buf[len-1] = '\0';
/* remove leading and trailing spaces of input buffer */
gname = strstrip(buf);
if (*gname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
/* find a separator which is a spacelike character */
for (fname = gname; !isspace(*fname); fname++) {
if (*fname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
}
*fname = '\0';
/* drop extra spaces between function and group names */
fname = skip_spaces(fname + 1);
if (*fname == '\0') {
ret = -EINVAL;
goto exit_free_buf;
}
ret = pinmux_func_name_to_selector(pctldev, fname);
if (ret < 0) {
dev_err(pctldev->dev, "invalid function %s in map table\n", fname);
goto exit_free_buf;
}
fsel = ret;
ret = pmxops->get_function_groups(pctldev, fsel, &groups, &num_groups);
if (ret) {
dev_err(pctldev->dev, "no groups for function %d (%s)", fsel, fname);
goto exit_free_buf;
}
ret = match_string(groups, num_groups, gname);
if (ret < 0) {
dev_err(pctldev->dev, "invalid group %s", gname);
goto exit_free_buf;
}
ret = pinctrl_get_group_selector(pctldev, gname);
if (ret < 0) {
dev_err(pctldev->dev, "failed to get group selector for %s", gname);
goto exit_free_buf;
}
gsel = ret;
ret = pmxops->set_mux(pctldev, fsel, gsel);
if (ret) {
dev_err(pctldev->dev, "set_mux() failed: %d", ret);
goto exit_free_buf;
}
ret = len;
exit_free_buf:
kfree(buf);
return ret;
}
static int pinmux_select_open(struct inode *inode, struct file *file)
{
return single_open(file, NULL, inode->i_private);
}
static const struct file_operations pinmux_select_ops = {
.owner = THIS_MODULE,
.open = pinmux_select_open,
.write = pinmux_select,
.llseek = no_llseek,
.release = single_release,
};
void pinmux_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev)
{
debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO,
debugfs_create_file("pinmux-functions", 0444,
devroot, pctldev, &pinmux_functions_fops);
debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO,
debugfs_create_file("pinmux-pins", 0444,
devroot, pctldev, &pinmux_pins_fops);
debugfs_create_file("pinmux-select", 0200,
devroot, pctldev, &pinmux_select_ops);
}
#endif /* CONFIG_DEBUG_FS */

4
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
View File

@ -194,7 +194,7 @@ static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pctl->lock, flags);
val = readl_relaxed(pgsr) & BIT(pin % 32);
*config = val ? PIN_CONFIG_LOW_POWER_MODE : 0;
*config = val ? PIN_CONFIG_MODE_LOW_POWER : 0;
spin_unlock_irqrestore(&pctl->lock, flags);
dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
@ -217,7 +217,7 @@ static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev,
for (i = 0; i < num_configs; i++) {
switch (pinconf_to_config_param(configs[i])) {
case PIN_CONFIG_LOW_POWER_MODE:
case PIN_CONFIG_MODE_LOW_POWER:
is_set = pinconf_to_config_argument(configs[i]);
break;
default:

4
drivers/pinctrl/qcom/Kconfig
View File

@ -3,7 +3,7 @@ if (ARCH_QCOM || COMPILE_TEST)
config PINCTRL_MSM
tristate "Qualcomm core pin controller driver"
depends on QCOM_SCM || !QCOM_SCM #if QCOM_SCM=m this can't be =y
depends on GPIOLIB && (QCOM_SCM || !QCOM_SCM) #if QCOM_SCM=m this can't be =y
select PINMUX
select PINCONF
select GENERIC_PINCONF
@ -222,7 +222,7 @@ config PINCTRL_SC7280
config PINCTRL_SC8180X
tristate "Qualcomm Technologies Inc SC8180x pin controller driver"
depends on GPIOLIB && OF
depends on GPIOLIB && (OF || ACPI)
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the

24
drivers/pinctrl/qcom/pinctrl-sc7280.c
View File

@ -1449,6 +1449,28 @@ static const struct msm_pingroup sc7280_groups[] = {
[182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0),
};
static const struct msm_gpio_wakeirq_map sc7280_pdc_map[] = {
{ 0, 134 }, { 3, 131 }, { 4, 121 }, { 7, 103 }, { 8, 155 },
{ 11, 93 }, { 12, 78 }, { 15, 79 }, { 16, 80 }, { 18, 81 },
{ 19, 107 }, { 20, 82 }, { 21, 83 }, { 23, 99 }, { 24, 86 },
{ 25, 95 }, { 27, 158 }, { 28, 159 }, { 31, 90 }, { 32, 144 },
{ 34, 77 }, { 35, 92 }, { 36, 157 }, { 39, 73 }, { 40, 97 },
{ 41, 98 }, { 43, 85 }, { 44, 100 }, { 45, 101 }, { 47, 102 },
{ 48, 74 }, { 51, 112 }, { 52, 156 }, { 54, 117 }, { 55, 84 },
{ 56, 108 }, { 59, 110 }, { 60, 111 }, { 61, 123 }, { 63, 104 },
{ 68, 127 }, { 72, 150 }, { 75, 133 }, { 77, 125 }, { 78, 105 },
{ 79, 106 }, { 80, 118 }, { 81, 119 }, { 82, 162 }, { 83, 122 },
{ 86, 75 }, { 88, 154 }, { 89, 124 }, { 90, 149 }, { 91, 76 },
{ 93, 128 }, { 95, 160 }, { 101, 126 }, { 102, 96 }, { 103, 116 },
{ 104, 114 }, { 112, 72 }, { 116, 135 }, { 117, 163 }, { 119, 137 },
{ 121, 138 }, { 123, 139 }, { 125, 140 }, { 127, 141 }, { 128, 165 },
{ 129, 143 }, { 130, 94 }, { 131, 145 }, { 133, 146 }, { 136, 147 },
{ 140, 148 }, { 141, 115 }, { 142, 113 }, { 145, 130 }, { 148, 132 },
{ 150, 87 }, { 151, 88 }, { 153, 89 }, { 155, 164 }, { 156, 129 },
{ 157, 161 }, { 158, 120 }, { 161, 136 }, { 163, 142 }, { 172, 166 },
{ 174, 167 },
};
static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
.pins = sc7280_pins,
.npins = ARRAY_SIZE(sc7280_pins),
@ -1457,6 +1479,8 @@ static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
.groups = sc7280_groups,
.ngroups = ARRAY_SIZE(sc7280_groups),
.ngpios = 176,
.wakeirq_map = sc7280_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map),
};
static int sc7280_pinctrl_probe(struct platform_device *pdev)

125
drivers/pinctrl/qcom/pinctrl-sc8180x.c
View File

@ -23,6 +23,21 @@ enum {
WEST
};
/*
* ACPI DSDT has one single memory resource for TLMM. The offsets below are
* used to locate different tiles for ACPI probe.
*/
struct tile_info {
u32 offset;
u32 size;
};
static const struct tile_info sc8180x_tile_info[] = {
{ 0x00d00000, 0x00300000, },
{ 0x00500000, 0x00700000, },
{ 0x00100000, 0x00300000, },
};
#define FUNCTION(fname) \
[msm_mux_##fname] = { \
.name = #fname, \
@ -1557,6 +1572,13 @@ static const struct msm_pingroup sc8180x_groups[] = {
[193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0),
};
static const int sc8180x_acpi_reserved_gpios[] = {
0, 1, 2, 3,
47, 48, 49, 50,
126, 127, 128, 129,
-1 /* terminator */
};
static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = {
{ 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 },
{ 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 },
@ -1588,13 +1610,109 @@ static struct msm_pinctrl_soc_data sc8180x_pinctrl = {
.nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map),
};
static int sc8180x_pinctrl_probe(struct platform_device *pdev)
static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = {
.tiles = sc8180x_tiles,
.ntiles = ARRAY_SIZE(sc8180x_tiles),
.pins = sc8180x_pins,
.npins = ARRAY_SIZE(sc8180x_pins),
.groups = sc8180x_groups,
.ngroups = ARRAY_SIZE(sc8180x_groups),
.reserved_gpios = sc8180x_acpi_reserved_gpios,
.ngpios = 190,
};
/*
* ACPI DSDT has one single memory resource for TLMM, which voilates the
* hardware layout of 3 sepearte tiles. Let's split the memory resource into
* 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the
* same way as for DT probe.
*/
static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &sc8180x_pinctrl);
int nres_num = pdev->num_resources + ARRAY_SIZE(sc8180x_tiles) - 1;
struct resource *mres, *nres, *res;
int i, ret;
/*
* DT already has tiles defined properly, so nothing needs to be done
* for DT probe.
*/
if (pdev->dev.of_node)
return 0;
/* Allocate for new resources */
nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL);
if (!nres)
return -ENOMEM;
res = nres;
for (i = 0; i < pdev->num_resources; i++) {
struct resource *r = &pdev->resource[i];
/* Save memory resource and copy others */
if (resource_type(r) == IORESOURCE_MEM)
mres = r;
else
*res++ = *r;
}
/* Append tile memory resources */
for (i = 0; i < ARRAY_SIZE(sc8180x_tiles); i++, res++) {
const struct tile_info *info = &sc8180x_tile_info[i];
res->start = mres->start + info->offset;
res->end = mres->start + info->offset + info->size - 1;
res->flags = mres->flags;
res->name = sc8180x_tiles[i];
/* Add new MEM to resource tree */
insert_resource(mres->parent, res);
}
/* Remove old MEM from resource tree */
remove_resource(mres);
/* Free old resources and install new ones */
ret = platform_device_add_resources(pdev, nres, nres_num);
if (ret) {
dev_err(&pdev->dev, "failed to add new resources: %d\n", ret);
return ret;
}
return 0;
}
static int sc8180x_pinctrl_probe(struct platform_device *pdev)
{
const struct msm_pinctrl_soc_data *soc_data;
int ret;
soc_data = device_get_match_data(&pdev->dev);
if (!soc_data)
return -EINVAL;
ret = sc8180x_pinctrl_add_tile_resources(pdev);
if (ret)
return ret;
return msm_pinctrl_probe(pdev, soc_data);
}
static const struct acpi_device_id sc8180x_pinctrl_acpi_match[] = {
{
.id = "QCOM040D",
.driver_data = (kernel_ulong_t) &sc8180x_acpi_pinctrl,
},
{ }
};
MODULE_DEVICE_TABLE(acpi, sc8180x_pinctrl_acpi_match);
static const struct of_device_id sc8180x_pinctrl_of_match[] = {
{ .compatible = "qcom,sc8180x-tlmm", },
{
.compatible = "qcom,sc8180x-tlmm",
.data = &sc8180x_pinctrl,
},
{ },
};
MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match);
@ -1603,6 +1721,7 @@ static struct platform_driver sc8180x_pinctrl_driver = {
.driver = {
.name = "sc8180x-pinctrl",
.of_match_table = sc8180x_pinctrl_of_match,
.acpi_match_table = sc8180x_pinctrl_acpi_match,
},
.probe = sc8180x_pinctrl_probe,
.remove = msm_pinctrl_remove,

21
drivers/pinctrl/qcom/pinctrl-sm8350.c
View File

@ -1603,6 +1603,25 @@ static const struct msm_pingroup sm8350_groups[] = {
[206] = SDC_PINGROUP(sdc2_data, 0x1cf000, 9, 0),
};
static const struct msm_gpio_wakeirq_map sm8350_pdc_map[] = {
{ 2, 117 }, { 7, 82 }, { 11, 83 }, { 14, 80 }, { 15, 146 },
{ 19, 121 }, { 23, 84 }, { 26, 86 }, { 27, 75 }, { 31, 85 },
{ 32, 97 }, { 34, 98 }, { 35, 131 }, { 36, 79 }, { 38, 99 },
{ 39, 92 }, { 40, 101 }, { 43, 137 }, { 44, 102 }, { 46, 96 },
{ 47, 93 }, { 50, 108 }, { 51, 127 }, { 55, 128 }, { 56, 81 },
{ 59, 112 }, { 60, 119 }, { 63, 73 }, { 67, 74 }, { 71, 134 },
{ 75, 103 }, { 79, 104 }, { 80, 126 }, { 81, 139 }, { 82, 140 },
{ 83, 141 }, { 84, 124 }, { 85, 109 }, { 86, 143 }, { 87, 138 },
{ 88, 122 }, { 89, 113 }, { 90, 114 }, { 91, 115 }, { 92, 76 },
{ 95, 147 }, { 96, 148 }, { 98, 149 }, { 99, 150 }, { 115, 125 },
{ 116, 106 }, { 117, 105 }, { 118, 116 }, { 119, 123 }, { 130, 145 },
{ 136, 72 }, { 140, 100 }, { 151, 110 }, { 153, 95 }, { 155, 107 },
{ 156, 94 }, { 157, 111 }, { 159, 118 }, { 162, 77 }, { 165, 78 },
{ 169, 70 }, { 172, 132 }, { 174, 87 }, { 175, 88 }, { 177, 89 },
{ 179, 120 }, { 180, 129 }, { 183, 90 }, { 185, 136 }, { 187, 142 },
{ 190, 144 }, { 198, 91 }, { 200, 133 }, { 202, 135 },
};
static const struct msm_pinctrl_soc_data sm8350_tlmm = {
.pins = sm8350_pins,
.npins = ARRAY_SIZE(sm8350_pins),
@ -1611,6 +1630,8 @@ static const struct msm_pinctrl_soc_data sm8350_tlmm = {
.groups = sm8350_groups,
.ngroups = ARRAY_SIZE(sm8350_groups),
.ngpios = 204,
.wakeirq_map = sm8350_pdc_map,
.nwakeirq_map = ARRAY_SIZE(sm8350_pdc_map),
};
static int sm8350_tlmm_probe(struct platform_device *pdev)

7
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View File

@ -1127,8 +1127,15 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
/* pm8150l has 12 GPIOs with holes on 7 */
{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
{ },

20
drivers/pinctrl/renesas/core.c
View File

@ -394,26 +394,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit)
{
unsigned int i, j;
for (i = 0; pfc->info->bias_regs[i].puen; i++) {
for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
if (pfc->info->bias_regs[i].pins[j] == pin) {
*bit = j;
return &pfc->info->bias_regs[i];
}
}
}
WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
return NULL;
}
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;

8
drivers/pinctrl/renesas/core.h
View File

@ -29,12 +29,4 @@ void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *bit);
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
#endif /* __SH_PFC_CORE_H__ */

48
drivers/pinctrl/renesas/pfc-r8a73a4.c
View File

@ -2649,59 +2649,21 @@ static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(329), /* IRQ57 */
};
#define PORTCR_PULMD_OFF (0 << 6)
#define PORTCR_PULMD_DOWN (2 << 6)
#define PORTCR_PULMD_UP (3 << 6)
#define PORTCR_PULMD_MASK (3 << 6)
static const unsigned int r8a73a4_portcr_offsets[] = {
0x00000000, 0x00001000, 0x00000000, 0x00001000,
0x00001000, 0x00002000, 0x00002000, 0x00002000,
0x00002000, 0x00003000, 0x00003000,
};
static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
unsigned int pin)
static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
{
void __iomem *addr;
addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
switch (ioread8(addr) & PORTCR_PULMD_MASK) {
case PORTCR_PULMD_UP:
return PIN_CONFIG_BIAS_PULL_UP;
case PORTCR_PULMD_DOWN:
return PIN_CONFIG_BIAS_PULL_DOWN;
case PORTCR_PULMD_OFF:
default:
return PIN_CONFIG_BIAS_DISABLE;
}
}
static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
void __iomem *addr;
u32 value;
addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
value = ioread8(addr) & ~PORTCR_PULMD_MASK;
switch (bias) {
case PIN_CONFIG_BIAS_PULL_UP:
value |= PORTCR_PULMD_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value |= PORTCR_PULMD_DOWN;
break;
}
iowrite8(value, addr);
return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
}
static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
.get_bias = r8a73a4_pinmux_get_bias,
.set_bias = r8a73a4_pinmux_set_bias,
.get_bias = rmobile_pinmux_get_bias,
.set_bias = rmobile_pinmux_set_bias,
.pin_to_portcr = r8a73a4_pin_to_portcr,
};
const struct sh_pfc_soc_info r8a73a4_pinmux_info = {

46
drivers/pinctrl/renesas/pfc-r8a7740.c
View File

@ -3672,11 +3672,6 @@ static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(41, 167), /* IRQ31A */
};
#define PORTnCR_PULMD_OFF (0 << 6)
#define PORTnCR_PULMD_DOWN (2 << 6)
#define PORTnCR_PULMD_UP (3 << 6)
#define PORTnCR_PULMD_MASK (3 << 6)
struct r8a7740_portcr_group {
unsigned int end_pin;
unsigned int offset;
@ -3686,7 +3681,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
{ 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
};
static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin)
{
unsigned int i;
@ -3701,43 +3696,10 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
return NULL;
}
static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
{
void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
switch (value) {
case PORTnCR_PULMD_UP:
return PIN_CONFIG_BIAS_PULL_UP;
case PORTnCR_PULMD_DOWN:
return PIN_CONFIG_BIAS_PULL_DOWN;
case PORTnCR_PULMD_OFF:
default:
return PIN_CONFIG_BIAS_DISABLE;
}
}
static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias)
{
void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
switch (bias) {
case PIN_CONFIG_BIAS_PULL_UP:
value |= PORTnCR_PULMD_UP;
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
value |= PORTnCR_PULMD_DOWN;
break;
}
iowrite8(value, addr);
}
static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
.get_bias = r8a7740_pinmux_get_bias,
.set_bias = r8a7740_pinmux_set_bias,
.get_bias = rmobile_pinmux_get_bias,
.set_bias = rmobile_pinmux_set_bias,
.pin_to_portcr = r8a7740_pin_to_portcr,
};
const struct sh_pfc_soc_info r8a7740_pinmux_info = {

1
drivers/pinctrl/renesas/pfc-r8a7778.c
View File

@ -16,7 +16,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \

387
drivers/pinctrl/renesas/pfc-r8a7791.c
View File

@ -16,22 +16,50 @@
* which case they support both 3.3V and 1.8V signalling.
*/
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_26(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx), \
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_1(6, 24, fn, sfx), \
PORT_GP_1(6, 25, fn, sfx), \
PORT_GP_1(6, 26, fn, sfx), \
PORT_GP_1(6, 27, fn, sfx), \
PORT_GP_1(6, 28, fn, sfx), \
PORT_GP_1(6, 29, fn, sfx), \
PORT_GP_1(6, 30, fn, sfx), \
PORT_GP_1(6, 31, fn, sfx), \
PORT_GP_26(7, fn, sfx)
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_1(7, 7, fn, sfx), \
PORT_GP_1(7, 8, fn, sfx), \
PORT_GP_1(7, 9, fn, sfx), \
PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
#define CPU_ALL_NOGP(fn) \
PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
enum {
PINMUX_RESERVED = 0,
@ -1696,8 +1724,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
};
/*
* Pins not associated with a GPIO port.
*/
enum {
GP_ASSIGN_LAST(),
NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
PINMUX_NOGP_ALL(),
};
#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
@ -6645,8 +6682,322 @@ static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
return 31 - (pin & 0x1f);
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
[ 0] = RCAR_GP_PIN(1, 4), /* A20 */
[ 1] = RCAR_GP_PIN(1, 5), /* A21 */
[ 2] = RCAR_GP_PIN(1, 6), /* A22 */
[ 3] = RCAR_GP_PIN(1, 7), /* A23 */
[ 4] = RCAR_GP_PIN(1, 8), /* A24 */
[ 5] = RCAR_GP_PIN(6, 31), /* DU0_DOTCLKIN */
[ 6] = RCAR_GP_PIN(0, 0), /* D0 */
[ 7] = RCAR_GP_PIN(0, 1), /* D1 */
[ 8] = RCAR_GP_PIN(0, 2), /* D2 */
[ 9] = RCAR_GP_PIN(0, 3), /* D3 */
[10] = RCAR_GP_PIN(0, 4), /* D4 */
[11] = RCAR_GP_PIN(0, 5), /* D5 */
[12] = RCAR_GP_PIN(0, 6), /* D6 */
[13] = RCAR_GP_PIN(0, 7), /* D7 */
[14] = RCAR_GP_PIN(0, 8), /* D8 */
[15] = RCAR_GP_PIN(0, 9), /* D9 */
[16] = RCAR_GP_PIN(0, 10), /* D10 */
[17] = RCAR_GP_PIN(0, 11), /* D11 */
[18] = RCAR_GP_PIN(0, 12), /* D12 */
[19] = RCAR_GP_PIN(0, 13), /* D13 */
[20] = RCAR_GP_PIN(0, 14), /* D14 */
[21] = RCAR_GP_PIN(0, 15), /* D15 */
[22] = RCAR_GP_PIN(0, 16), /* A0 */
[23] = RCAR_GP_PIN(0, 17), /* A1 */
[24] = RCAR_GP_PIN(0, 18), /* A2 */
[25] = RCAR_GP_PIN(0, 19), /* A3 */
[26] = RCAR_GP_PIN(0, 20), /* A4 */
[27] = RCAR_GP_PIN(0, 21), /* A5 */
[28] = RCAR_GP_PIN(0, 22), /* A6 */
[29] = RCAR_GP_PIN(0, 23), /* A7 */
[30] = RCAR_GP_PIN(0, 24), /* A8 */
[31] = RCAR_GP_PIN(0, 25), /* A9 */
} },
{ PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
[ 0] = RCAR_GP_PIN(0, 26), /* A10 */
[ 1] = RCAR_GP_PIN(0, 27), /* A11 */
[ 2] = RCAR_GP_PIN(0, 28), /* A12 */
[ 3] = RCAR_GP_PIN(0, 29), /* A13 */
[ 4] = RCAR_GP_PIN(0, 30), /* A14 */
[ 5] = RCAR_GP_PIN(0, 31), /* A15 */
[ 6] = RCAR_GP_PIN(1, 0), /* A16 */
[ 7] = RCAR_GP_PIN(1, 1), /* A17 */
[ 8] = RCAR_GP_PIN(1, 2), /* A18 */
[ 9] = RCAR_GP_PIN(1, 3), /* A19 */
[10] = PIN_TRST_N, /* TRST# */
[11] = PIN_TCK, /* TCK */
[12] = PIN_TMS, /* TMS */
[13] = PIN_TDI, /* TDI */
[14] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
[15] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
[16] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
[17] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
[18] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
[19] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
[20] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
[21] = RCAR_GP_PIN(1, 18), /* BS# */
[22] = RCAR_GP_PIN(1, 19), /* RD# */
[23] = RCAR_GP_PIN(1, 20), /* RD/WR# */
[24] = RCAR_GP_PIN(1, 21), /* WE0# */
[25] = RCAR_GP_PIN(1, 22), /* WE1# */
[26] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
[27] = RCAR_GP_PIN(1, 24), /* DREQ0 */
[28] = RCAR_GP_PIN(1, 25), /* DACK0 */
[29] = RCAR_GP_PIN(5, 31), /* SPEEDIN */
[30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */
[31] = RCAR_GP_PIN(2, 1), /* SSI_WS0129 */
} },
{ PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
[ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */
[ 1] = RCAR_GP_PIN(2, 3), /* SSI_SCK1 */
[ 2] = RCAR_GP_PIN(2, 4), /* SSI_WS1 */
[ 3] = RCAR_GP_PIN(2, 5), /* SSI_SDATA1 */
[ 4] = RCAR_GP_PIN(2, 6), /* SSI_SCK2 */
[ 5] = RCAR_GP_PIN(2, 7), /* SSI_WS2 */
[ 6] = RCAR_GP_PIN(2, 8), /* SSI_SDATA2 */
[ 7] = RCAR_GP_PIN(2, 9), /* SSI_SCK34 */
[ 8] = RCAR_GP_PIN(2, 10), /* SSI_WS34 */
[ 9] = RCAR_GP_PIN(2, 11), /* SSI_SDATA3 */
[10] = RCAR_GP_PIN(2, 12), /* SSI_SCK4 */
[11] = RCAR_GP_PIN(2, 13), /* SSI_WS4 */
[12] = RCAR_GP_PIN(2, 14), /* SSI_SDATA4 */
[13] = RCAR_GP_PIN(2, 15), /* SSI_SCK5 */
[14] = RCAR_GP_PIN(2, 16), /* SSI_WS5 */
[15] = RCAR_GP_PIN(2, 17), /* SSI_SDATA5 */
[16] = RCAR_GP_PIN(2, 18), /* SSI_SCK6 */
[17] = RCAR_GP_PIN(2, 19), /* SSI_WS6 */
[18] = RCAR_GP_PIN(2, 20), /* SSI_SDATA6 */
[19] = RCAR_GP_PIN(2, 21), /* SSI_SCK78 */
[20] = RCAR_GP_PIN(2, 22), /* SSI_WS78 */
[21] = RCAR_GP_PIN(2, 23), /* SSI_SDATA7 */
[22] = RCAR_GP_PIN(2, 24), /* SSI_SDATA8 */
[23] = RCAR_GP_PIN(2, 25), /* SSI_SCK9 */
[24] = RCAR_GP_PIN(2, 26), /* SSI_WS9 */
[25] = RCAR_GP_PIN(2, 27), /* SSI_SDATA9 */
[26] = RCAR_GP_PIN(2, 28), /* AUDIO_CLKA */
[27] = RCAR_GP_PIN(2, 29), /* AUDIO_CLKB */
[28] = RCAR_GP_PIN(2, 30), /* AUDIO_CLKC */
[29] = RCAR_GP_PIN(2, 31), /* AUDIO_CLKOUT */
[30] = RCAR_GP_PIN(7, 10), /* IRQ0 */
[31] = RCAR_GP_PIN(7, 11), /* IRQ1 */
} },
{ PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
[ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */
[ 1] = RCAR_GP_PIN(7, 13), /* IRQ3 */
[ 2] = RCAR_GP_PIN(7, 14), /* IRQ4 */
[ 3] = RCAR_GP_PIN(7, 15), /* IRQ5 */
[ 4] = RCAR_GP_PIN(7, 16), /* IRQ6 */
[ 5] = RCAR_GP_PIN(7, 17), /* IRQ7 */
[ 6] = RCAR_GP_PIN(7, 18), /* IRQ8 */
[ 7] = RCAR_GP_PIN(7, 19), /* IRQ9 */
[ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */
[ 9] = RCAR_GP_PIN(3, 1), /* DU1_DR1 */
[10] = RCAR_GP_PIN(3, 2), /* DU1_DR2 */
[11] = RCAR_GP_PIN(3, 3), /* DU1_DR3 */
[12] = RCAR_GP_PIN(3, 4), /* DU1_DR4 */
[13] = RCAR_GP_PIN(3, 5), /* DU1_DR5 */
[14] = RCAR_GP_PIN(3, 6), /* DU1_DR6 */
[15] = RCAR_GP_PIN(3, 7), /* DU1_DR7 */
[16] = RCAR_GP_PIN(3, 8), /* DU1_DG0 */
[17] = RCAR_GP_PIN(3, 9), /* DU1_DG1 */
[18] = RCAR_GP_PIN(3, 10), /* DU1_DG2 */
[19] = RCAR_GP_PIN(3, 11), /* DU1_DG3 */
[20] = RCAR_GP_PIN(3, 12), /* DU1_DG4 */
[21] = RCAR_GP_PIN(3, 13), /* DU1_DG5 */
[22] = RCAR_GP_PIN(3, 14), /* DU1_DG6 */
[23] = RCAR_GP_PIN(3, 15), /* DU1_DG7 */
[24] = RCAR_GP_PIN(3, 16), /* DU1_DB0 */
[25] = RCAR_GP_PIN(3, 17), /* DU1_DB1 */
[26] = RCAR_GP_PIN(3, 18), /* DU1_DB2 */
[27] = RCAR_GP_PIN(3, 19), /* DU1_DB3 */
[28] = RCAR_GP_PIN(3, 20), /* DU1_DB4 */
[29] = RCAR_GP_PIN(3, 21), /* DU1_DB5 */
[30] = RCAR_GP_PIN(3, 22), /* DU1_DB6 */
[31] = RCAR_GP_PIN(3, 23), /* DU1_DB7 */
} },
{ PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
[ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */
[ 1] = RCAR_GP_PIN(3, 25), /* DU1_DOTCLKOUT0 */
[ 2] = RCAR_GP_PIN(3, 26), /* DU1_DOTCLKOUT1 */
[ 3] = RCAR_GP_PIN(3, 27), /* DU1_EXHSYNC_DU1_HSYNC */
[ 4] = RCAR_GP_PIN(3, 28), /* DU1_EXVSYNC_DU1_VSYNC */
[ 5] = RCAR_GP_PIN(3, 29), /* DU1_EXODDF_DU1_ODDF_DISP_CDE */
[ 6] = RCAR_GP_PIN(3, 30), /* DU1_DISP */
[ 7] = RCAR_GP_PIN(3, 31), /* DU1_CDE */
[ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */
[ 9] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */
[10] = RCAR_GP_PIN(4, 2), /* VI0_FIELD */
[11] = RCAR_GP_PIN(4, 3), /* VI0_HSYNC# */
[12] = RCAR_GP_PIN(4, 4), /* VI0_VSYNC# */
[13] = RCAR_GP_PIN(4, 5), /* VI0_DATA0_VI0_B0 */
[14] = RCAR_GP_PIN(4, 6), /* VI0_DATA1_VI0_B1 */
[15] = RCAR_GP_PIN(4, 7), /* VI0_DATA2_VI0_B2 */
[16] = RCAR_GP_PIN(4, 8), /* VI0_DATA3_VI0_B3 */
[17] = RCAR_GP_PIN(4, 9), /* VI0_DATA4_VI0_B4 */
[18] = RCAR_GP_PIN(4, 10), /* VI0_DATA5_VI0_B5 */
[19] = RCAR_GP_PIN(4, 11), /* VI0_DATA6_VI0_B6 */
[20] = RCAR_GP_PIN(4, 12), /* VI0_DATA7_VI0_B7 */
[21] = RCAR_GP_PIN(4, 13), /* VI0_G0 */
[22] = RCAR_GP_PIN(4, 14), /* VI0_G1 */
[23] = RCAR_GP_PIN(4, 15), /* VI0_G2 */
[24] = RCAR_GP_PIN(4, 16), /* VI0_G3 */
[25] = RCAR_GP_PIN(4, 17), /* VI0_G4 */
[26] = RCAR_GP_PIN(4, 18), /* VI0_G5 */
[27] = RCAR_GP_PIN(4, 19), /* VI0_G6 */
[28] = RCAR_GP_PIN(4, 20), /* VI0_G7 */
[29] = RCAR_GP_PIN(4, 21), /* VI0_R0 */
[30] = RCAR_GP_PIN(4, 22), /* VI0_R1 */
[31] = RCAR_GP_PIN(4, 23), /* VI0_R2 */
} },
{ PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
[ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */
[ 1] = RCAR_GP_PIN(4, 25), /* VI0_R4 */
[ 2] = RCAR_GP_PIN(4, 26), /* VI0_R5 */
[ 3] = RCAR_GP_PIN(4, 27), /* VI0_R6 */
[ 4] = RCAR_GP_PIN(4, 28), /* VI0_R7 */
[ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */
[ 6] = RCAR_GP_PIN(5, 1), /* VI1_VSYNC# */
[ 7] = RCAR_GP_PIN(5, 2), /* VI1_CLKENB */
[ 8] = RCAR_GP_PIN(5, 3), /* VI1_FIELD */
[ 9] = RCAR_GP_PIN(5, 4), /* VI1_CLK */
[10] = RCAR_GP_PIN(5, 5), /* VI1_DATA0 */
[11] = RCAR_GP_PIN(5, 6), /* VI1_DATA1 */
[12] = RCAR_GP_PIN(5, 7), /* VI1_DATA2 */
[13] = RCAR_GP_PIN(5, 8), /* VI1_DATA3 */
[14] = RCAR_GP_PIN(5, 9), /* VI1_DATA4 */
[15] = RCAR_GP_PIN(5, 10), /* VI1_DATA5 */
[16] = RCAR_GP_PIN(5, 11), /* VI1_DATA6 */
[17] = RCAR_GP_PIN(5, 12), /* VI1_DATA7 */
[18] = RCAR_GP_PIN(5, 13), /* ETH_MDIO */
[19] = RCAR_GP_PIN(5, 14), /* ETH_CRS_DV */
[20] = RCAR_GP_PIN(5, 15), /* ETH_RX_ER */
[21] = RCAR_GP_PIN(5, 16), /* ETH_RXD0 */
[22] = RCAR_GP_PIN(5, 17), /* ETH_RXD1 */
[23] = RCAR_GP_PIN(5, 18), /* ETH_LINK */
[24] = RCAR_GP_PIN(5, 19), /* ETH_REFCLK */
[25] = RCAR_GP_PIN(5, 20), /* ETH_TXD1 */
[26] = RCAR_GP_PIN(5, 21), /* ETH_TX_EN */
[27] = RCAR_GP_PIN(5, 22), /* ETH_MAGIC */
[28] = RCAR_GP_PIN(5, 23), /* ETH_TXD0 */
[29] = RCAR_GP_PIN(5, 24), /* ETH_MDC */
[30] = RCAR_GP_PIN(5, 25), /* STP_IVCXO27_0 */
[31] = RCAR_GP_PIN(5, 26), /* STP_ISCLK_0 */
} },
{ PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
[ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */
[ 1] = RCAR_GP_PIN(5, 28), /* STP_ISEN_0 */
[ 2] = RCAR_GP_PIN(5, 29), /* STP_ISSYNC_0 */
[ 3] = RCAR_GP_PIN(5, 30), /* STP_OPWM_0 */
[ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */
[ 5] = RCAR_GP_PIN(6, 1), /* SD0_CMD */
[ 6] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */
[ 7] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */
[ 8] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */
[ 9] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */
[10] = RCAR_GP_PIN(6, 6), /* SD0_CD */
[11] = RCAR_GP_PIN(6, 7), /* SD0_WP */
[12] = RCAR_GP_PIN(6, 8), /* SD2_CLK */
[13] = RCAR_GP_PIN(6, 9), /* SD2_CMD */
[14] = RCAR_GP_PIN(6, 10), /* SD2_DATA0 */
[15] = RCAR_GP_PIN(6, 11), /* SD2_DATA1 */
[16] = RCAR_GP_PIN(6, 12), /* SD2_DATA2 */
[17] = RCAR_GP_PIN(6, 13), /* SD2_DATA3 */
[18] = RCAR_GP_PIN(6, 14), /* SD2_CD */
[19] = RCAR_GP_PIN(6, 15), /* SD2_WP */
[20] = RCAR_GP_PIN(6, 16), /* SD3_CLK */
[21] = RCAR_GP_PIN(6, 17), /* SD3_CMD */
[22] = RCAR_GP_PIN(6, 18), /* SD3_DATA0 */
[23] = RCAR_GP_PIN(6, 19), /* SD3_DATA1 */
[24] = RCAR_GP_PIN(6, 20), /* SD3_DATA2 */
[25] = RCAR_GP_PIN(6, 21), /* SD3_DATA3 */
[26] = RCAR_GP_PIN(6, 22), /* SD3_CD */
[27] = RCAR_GP_PIN(6, 23), /* SD3_WP */
[28] = RCAR_GP_PIN(6, 24), /* MSIOF0_SCK */
[29] = RCAR_GP_PIN(6, 25), /* MSIOF0_SYNC */
[30] = RCAR_GP_PIN(6, 26), /* MSIOF0_TXD */
[31] = RCAR_GP_PIN(6, 27), /* MSIOF0_RXD */
} },
{ PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
/* PUPR7 pull-up pins */
[ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */
[ 1] = RCAR_GP_PIN(6, 29), /* MSIOF0_SS2 */
[ 2] = RCAR_GP_PIN(4, 29), /* SIM0_RST */
[ 3] = RCAR_GP_PIN(4, 30), /* SIM0_CLK */
[ 4] = RCAR_GP_PIN(4, 31), /* SIM0_D */
[ 5] = RCAR_GP_PIN(7, 20), /* GPS_CLK */
[ 6] = RCAR_GP_PIN(7, 21), /* GPS_SIGN */
[ 7] = RCAR_GP_PIN(7, 22), /* GPS_MAG */
[ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */
[ 9] = RCAR_GP_PIN(7, 1), /* HRTS0# */
[10] = RCAR_GP_PIN(7, 2), /* HSCK0 */
[11] = RCAR_GP_PIN(7, 3), /* HRX0 */
[12] = RCAR_GP_PIN(7, 4), /* HTX0 */
[13] = RCAR_GP_PIN(7, 5), /* HRX1 */
[14] = RCAR_GP_PIN(7, 6), /* HTX1 */
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = RCAR_GP_PIN(1, 9), /* A25 */
[19] = SH_PFC_PIN_NONE,
[20] = RCAR_GP_PIN(1, 10), /* CS0# */
[21] = RCAR_GP_PIN(7, 23), /* USB0_PWEN */
[22] = RCAR_GP_PIN(7, 24), /* USB0_OVC */
[23] = RCAR_GP_PIN(7, 25), /* USB1_PWEN */
[24] = RCAR_GP_PIN(6, 30), /* USB1_OVC */
[25] = PIN_AVS1, /* AVS1 */
[26] = PIN_AVS2, /* AVS2 */
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
/* PUPR7 pull-down pins */
[ 0] = SH_PFC_PIN_NONE,
[ 1] = SH_PFC_PIN_NONE,
[ 2] = SH_PFC_PIN_NONE,
[ 3] = SH_PFC_PIN_NONE,
[ 4] = SH_PFC_PIN_NONE,
[ 5] = SH_PFC_PIN_NONE,
[ 6] = SH_PFC_PIN_NONE,
[ 7] = SH_PFC_PIN_NONE,
[ 8] = SH_PFC_PIN_NONE,
[ 9] = SH_PFC_PIN_NONE,
[10] = SH_PFC_PIN_NONE,
[11] = SH_PFC_PIN_NONE,
[12] = SH_PFC_PIN_NONE,
[13] = SH_PFC_PIN_NONE,
[14] = SH_PFC_PIN_NONE,
[15] = SH_PFC_PIN_NONE,
[16] = SH_PFC_PIN_NONE,
[17] = SH_PFC_PIN_NONE,
[18] = SH_PFC_PIN_NONE,
[19] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
[20] = SH_PFC_PIN_NONE,
[21] = SH_PFC_PIN_NONE,
[22] = SH_PFC_PIN_NONE,
[23] = SH_PFC_PIN_NONE,
[24] = SH_PFC_PIN_NONE,
[25] = SH_PFC_PIN_NONE,
[26] = SH_PFC_PIN_NONE,
[27] = SH_PFC_PIN_NONE,
[28] = SH_PFC_PIN_NONE,
[29] = SH_PFC_PIN_NONE,
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
{ /* sentinel */ },
};
static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
.pin_to_pocctrl = r8a7791_pin_to_pocctrl,
.get_bias = rcar_pinmux_get_bias,
.set_bias = rcar_pinmux_set_bias,
};
#ifdef CONFIG_PINCTRL_PFC_R8A7743
@ -6665,6 +7016,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@ -6687,6 +7039,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = {
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@ -6711,6 +7064,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
@ -6735,6 +7089,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = {
ARRAY_SIZE(pinmux_functions.automotive),
.cfg_regs = pinmux_config_regs,
.bias_regs = pinmux_bias_regs,
.pinmux_data = pinmux_data,
.pinmux_data_size = ARRAY_SIZE(pinmux_data),

1
drivers/pinctrl/renesas/pfc-r8a7792.c
View File

@ -8,7 +8,6 @@
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \

1
drivers/pinctrl/renesas/pfc-r8a77950.c
View File

@ -8,7 +8,6 @@
#include <linux/errno.h>
#include <linux/kernel.h>
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)

31
drivers/pinctrl/renesas/pfc-r8a77951.c
View File

@ -9,7 +9,6 @@
#include <linux/kernel.h>
#include <linux/sys_soc.h>
#include "core.h"
#include "sh_pfc.h"
#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
@ -4126,6 +4125,18 @@ static const union vin_data vin4_data_b_mux = {
VI4_DATA22_MARK, VI4_DATA23_MARK,
},
};
static const unsigned int vin4_g8_pins[] = {
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin4_g8_mux[] = {
VI4_DATA8_MARK, VI4_DATA9_MARK,
VI4_DATA10_MARK, VI4_DATA11_MARK,
VI4_DATA12_MARK, VI4_DATA13_MARK,
VI4_DATA14_MARK, VI4_DATA15_MARK,
};
static const unsigned int vin4_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
@ -4180,6 +4191,18 @@ static const union vin_data16 vin5_data_mux = {
VI5_DATA14_MARK, VI5_DATA15_MARK,
},
};
static const unsigned int vin5_high8_pins[] = {
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
};
static const unsigned int vin5_high8_mux[] = {
VI5_DATA8_MARK, VI5_DATA9_MARK,
VI5_DATA10_MARK, VI5_DATA11_MARK,
VI5_DATA12_MARK, VI5_DATA13_MARK,
VI5_DATA14_MARK, VI5_DATA15_MARK,
};
static const unsigned int vin5_sync_pins[] = {
/* HSYNC#, VSYNC# */
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
@ -4210,7 +4233,7 @@ static const unsigned int vin5_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[326];
struct sh_pfc_pin_group common[328];
#ifdef CONFIG_PINCTRL_PFC_R8A77951
struct sh_pfc_pin_group automotive[30];
#endif
@ -4530,6 +4553,7 @@ static const struct {
SH_PFC_PIN_GROUP(vin4_data18_b),
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
SH_PFC_PIN_GROUP(vin4_g8),
SH_PFC_PIN_GROUP(vin4_sync),
SH_PFC_PIN_GROUP(vin4_field),
SH_PFC_PIN_GROUP(vin4_clkenb),
@ -4538,6 +4562,7 @@ static const struct {
VIN_DATA_PIN_GROUP(vin5_data, 10),
VIN_DATA_PIN_GROUP(vin5_data, 12),
VIN_DATA_PIN_GROUP(vin5_data, 16),
SH_PFC_PIN_GROUP(vin5_high8),
SH_PFC_PIN_GROUP(vin5_sync),
SH_PFC_PIN_GROUP(vin5_field),
SH_PFC_PIN_GROUP(vin5_clkenb),
@ -5097,6 +5122,7 @@ static const char * const vin4_groups[] = {
"vin4_data18_b",
"vin4_data20_b",
"vin4_data24_b",
"vin4_g8",
"vin4_sync",
"vin4_field",
"vin4_clkenb",
@ -5108,6 +5134,7 @@ static const char * const vin5_groups[] = {
"vin5_data10",
"vin5_data12",
"vin5_data16",
"vin5_high8",
"vin5_sync",
"vin5_field",
"vin5_clkenb",

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