x86: coding style fixes to arch/x86/kernel/cpu/intel.c
Before: total: 37 errors, 16 warnings, 366 lines checked After: total: 0 errors, 15 warnings, 369 lines checked No code changed: arch/x86/kernel/cpu/intel.o: text data bss dec hex filename 1534 452 0 1986 7c2 intel.o.before 1534 452 0 1986 7c2 intel.o.after md5: 1ca348a06de6eb354c4b6ea715a57db5 intel.o.before.asm 1ca348a06de6eb354c4b6ea715a57db5 intel.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
Ingo Molnar
parent
60e11746d9
commit
65eb6b4326
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@ -45,7 +45,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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*
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* This is called before we do cpu ident work
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*/
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int __cpuinit ppro_with_ram_bug(void)
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{
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/* Uses data from early_cpu_detect now */
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@ -58,7 +58,7 @@ int __cpuinit ppro_with_ram_bug(void)
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}
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return 0;
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}
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/*
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* P4 Xeon errata 037 workaround.
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@ -69,7 +69,7 @@ static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
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unsigned long lo, hi;
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
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rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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if ((lo & (1<<9)) == 0) {
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printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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@ -127,10 +127,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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*/
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c->f00f_bug = 0;
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if (!paravirt_enabled() && c->x86 == 5) {
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static int f00f_workaround_enabled = 0;
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static int f00f_workaround_enabled;
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c->f00f_bug = 1;
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if ( !f00f_workaround_enabled ) {
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if (!f00f_workaround_enabled) {
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trap_init_f00f_bug();
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printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
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f00f_workaround_enabled = 1;
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@ -139,7 +139,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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#endif
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l2 = init_intel_cacheinfo(c);
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if (c->cpuid_level > 9 ) {
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if (c->cpuid_level > 9) {
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unsigned eax = cpuid_eax(10);
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/* Check for version and the number of counters */
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if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
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@ -150,9 +150,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_bit(X86_FEATURE_SEP, c->x86_capability);
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/* Names for the Pentium II/Celeron processors
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detectable only by also checking the cache size.
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Dixon is NOT a Celeron. */
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/*
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* Names for the Pentium II/Celeron processors
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* detectable only by also checking the cache size.
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* Dixon is NOT a Celeron.
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*/
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if (c->x86 == 6) {
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switch (c->x86_model) {
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case 5:
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@ -163,14 +165,14 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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p = "Mobile Pentium II (Dixon)";
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}
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break;
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case 6:
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if (l2 == 128)
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p = "Celeron (Mendocino)";
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else if (c->x86_mask == 0 || c->x86_mask == 5)
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p = "Celeron-A";
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break;
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case 8:
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if (l2 == 128)
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p = "Celeron (Coppermine)";
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@ -178,9 +180,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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}
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}
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if ( p )
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if (p)
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strcpy(c->x86_model_id, p);
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c->x86_max_cores = num_cpu_cores(c);
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detect_ht(c);
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@ -211,7 +213,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if (c->x86 == 15) {
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set_bit(X86_FEATURE_P4, c->x86_capability);
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}
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if (c->x86 == 6)
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if (c->x86 == 6)
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set_bit(X86_FEATURE_P3, c->x86_capability);
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if (cpu_has_ds) {
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unsigned int l1;
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@ -226,9 +228,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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ds_init_intel(c);
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}
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static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
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static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/* Intel PIII Tualatin. This comes in two flavours.
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/*
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* Intel PIII Tualatin. This comes in two flavours.
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* One has 256kb of cache, the other 512. We have no way
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* to determine which, so we use a boottime override
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* for the 512kb model, and assume 256 otherwise.
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@ -240,42 +243,42 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c, unsigned
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static struct cpu_dev intel_cpu_dev __cpuinitdata = {
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.c_vendor = "Intel",
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.c_ident = { "GenuineIntel" },
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.c_ident = { "GenuineIntel" },
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.c_models = {
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{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
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{
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[0] = "486 DX-25/33",
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[1] = "486 DX-50",
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[2] = "486 SX",
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[3] = "486 DX/2",
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[4] = "486 SL",
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[5] = "486 SX/2",
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[7] = "486 DX/2-WB",
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[8] = "486 DX/4",
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{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
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{
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[0] = "486 DX-25/33",
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[1] = "486 DX-50",
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[2] = "486 SX",
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[3] = "486 DX/2",
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[4] = "486 SL",
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[5] = "486 SX/2",
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[7] = "486 DX/2-WB",
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[8] = "486 DX/4",
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[9] = "486 DX/4-WB"
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}
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},
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{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
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{
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[0] = "Pentium 60/66 A-step",
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[1] = "Pentium 60/66",
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{
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[0] = "Pentium 60/66 A-step",
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[1] = "Pentium 60/66",
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[2] = "Pentium 75 - 200",
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[3] = "OverDrive PODP5V83",
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[3] = "OverDrive PODP5V83",
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[4] = "Pentium MMX",
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[7] = "Mobile Pentium 75 - 200",
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[7] = "Mobile Pentium 75 - 200",
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[8] = "Mobile Pentium MMX"
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}
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},
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{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
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{
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{
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[0] = "Pentium Pro A-step",
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[1] = "Pentium Pro",
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[3] = "Pentium II (Klamath)",
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[4] = "Pentium II (Deschutes)",
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[5] = "Pentium II (Deschutes)",
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[1] = "Pentium Pro",
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[3] = "Pentium II (Klamath)",
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[4] = "Pentium II (Deschutes)",
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[5] = "Pentium II (Deschutes)",
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[6] = "Mobile Pentium II",
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[7] = "Pentium III (Katmai)",
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[8] = "Pentium III (Coppermine)",
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[7] = "Pentium III (Katmai)",
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[8] = "Pentium III (Coppermine)",
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[10] = "Pentium III (Cascades)",
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[11] = "Pentium III (Tualatin)",
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}
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@ -361,5 +364,5 @@ unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
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EXPORT_SYMBOL(cmpxchg_486_u64);
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#endif
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// arch_initcall(intel_cpu_init);
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/* arch_initcall(intel_cpu_init); */
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