locking/atomics: Add _{acquire|release|relaxed}() variants of some atomic operations
Whilst porting the generic qrwlock code over to arm64, it became
apparent that any portable locking code needs finer-grained control of
the memory-ordering guarantees provided by our atomic routines.
In particular: xchg, cmpxchg, {add,sub}_return are often used in
situations where full barrier semantics (currently the only option
available) are not required. For example, when a reader increments a
reader count to obtain a lock, checking the old value to see if a writer
was present, only acquire semantics are strictly needed.
This patch introduces three new ordering semantics for these operations:
- *_relaxed: No ordering guarantees. This is similar to what we have
already for the non-return atomics (e.g. atomic_add).
- *_acquire: ACQUIRE semantics, similar to smp_load_acquire.
- *_release: RELEASE semantics, similar to smp_store_release.
In memory-ordering speak, this means that the acquire/release semantics
are RCpc as opposed to RCsc. Consequently a RELEASE followed by an
ACQUIRE does not imply a full barrier, as already documented in
memory-barriers.txt.
Currently, all the new macros are conditionally mapped to the full-mb
variants, however if the *_relaxed version is provided by the
architecture, then the acquire/release variants are constructed by
supplementing the relaxed routine with an explicit barrier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman.Long@hp.com
Cc: paulmck@linux.vnet.ibm.com
Link: http://lkml.kernel.org/r/1438880084-18856-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Will Deacon
Ingo Molnar
parent
ba33034fff
commit
654672d4ba
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@ -2,6 +2,329 @@
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#ifndef atomic_read_acquire
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#define atomic_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic_set_release
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#define atomic_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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*/
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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#define __atomic_op_release(op, args...) \
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({ \
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smp_mb__before_atomic(); \
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op##_relaxed(args); \
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})
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#define __atomic_op_fence(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret; \
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smp_mb__before_atomic(); \
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__ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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/* atomic_add_return_relaxed */
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#ifndef atomic_add_return_relaxed
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#define atomic_add_return_relaxed atomic_add_return
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#define atomic_add_return_acquire atomic_add_return
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#define atomic_add_return_release atomic_add_return
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#else /* atomic_add_return_relaxed */
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#ifndef atomic_add_return_acquire
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#define atomic_add_return_acquire(...) \
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__atomic_op_acquire(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return_release
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#define atomic_add_return_release(...) \
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__atomic_op_release(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return
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#define atomic_add_return(...) \
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__atomic_op_fence(atomic_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic_add_return_relaxed */
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/* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return
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#define atomic_sub_return_acquire atomic_sub_return
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#define atomic_sub_return_release atomic_sub_return
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#else /* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_acquire
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#define atomic_sub_return_acquire(...) \
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__atomic_op_acquire(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return_release
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#define atomic_sub_return_release(...) \
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__atomic_op_release(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return
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#define atomic_sub_return(...) \
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__atomic_op_fence(atomic_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic_sub_return_relaxed */
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/* atomic_xchg_relaxed */
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#ifndef atomic_xchg_relaxed
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#define atomic_xchg_relaxed atomic_xchg
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#define atomic_xchg_acquire atomic_xchg
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#define atomic_xchg_release atomic_xchg
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#else /* atomic_xchg_relaxed */
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#ifndef atomic_xchg_acquire
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#define atomic_xchg_acquire(...) \
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__atomic_op_acquire(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg_release
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#define atomic_xchg_release(...) \
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__atomic_op_release(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg
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#define atomic_xchg(...) \
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__atomic_op_fence(atomic_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic_xchg_relaxed */
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/* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_relaxed
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#define atomic_cmpxchg_relaxed atomic_cmpxchg
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#define atomic_cmpxchg_acquire atomic_cmpxchg
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#define atomic_cmpxchg_release atomic_cmpxchg
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#else /* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_acquire
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#define atomic_cmpxchg_acquire(...) \
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__atomic_op_acquire(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg_release
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#define atomic_cmpxchg_release(...) \
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__atomic_op_release(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg
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#define atomic_cmpxchg(...) \
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__atomic_op_fence(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#endif /* atomic_cmpxchg_relaxed */
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#ifndef atomic64_read_acquire
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#define atomic64_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic64_set_release
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#define atomic64_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_relaxed
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#define atomic64_add_return_relaxed atomic64_add_return
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#define atomic64_add_return_acquire atomic64_add_return
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#define atomic64_add_return_release atomic64_add_return
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#else /* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_acquire
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#define atomic64_add_return_acquire(...) \
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__atomic_op_acquire(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return_release
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#define atomic64_add_return_release(...) \
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__atomic_op_release(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return
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#define atomic64_add_return(...) \
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__atomic_op_fence(atomic64_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_add_return_relaxed */
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/* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return
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#define atomic64_sub_return_acquire atomic64_sub_return
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#define atomic64_sub_return_release atomic64_sub_return
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#else /* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_acquire
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#define atomic64_sub_return_acquire(...) \
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__atomic_op_acquire(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return_release
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#define atomic64_sub_return_release(...) \
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__atomic_op_release(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return
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#define atomic64_sub_return(...) \
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__atomic_op_fence(atomic64_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_sub_return_relaxed */
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/* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_relaxed
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#define atomic64_xchg_relaxed atomic64_xchg
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#define atomic64_xchg_acquire atomic64_xchg
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#define atomic64_xchg_release atomic64_xchg
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#else /* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_acquire
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#define atomic64_xchg_acquire(...) \
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__atomic_op_acquire(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg_release
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#define atomic64_xchg_release(...) \
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__atomic_op_release(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg
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#define atomic64_xchg(...) \
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__atomic_op_fence(atomic64_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic64_xchg_relaxed */
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/* atomic64_cmpxchg_relaxed */
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#ifndef atomic64_cmpxchg_relaxed
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#define atomic64_cmpxchg_relaxed atomic64_cmpxchg
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#define atomic64_cmpxchg_acquire atomic64_cmpxchg
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#define atomic64_cmpxchg_release atomic64_cmpxchg
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#else /* atomic64_cmpxchg_relaxed */
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#ifndef atomic64_cmpxchg_acquire
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#define atomic64_cmpxchg_acquire(...) \
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__atomic_op_acquire(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_cmpxchg_release
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#define atomic64_cmpxchg_release(...) \
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__atomic_op_release(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_cmpxchg
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#define atomic64_cmpxchg(...) \
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__atomic_op_fence(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#endif /* atomic64_cmpxchg_relaxed */
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/* cmpxchg_relaxed */
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#ifndef cmpxchg_relaxed
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#define cmpxchg_relaxed cmpxchg
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#define cmpxchg_acquire cmpxchg
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#define cmpxchg_release cmpxchg
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#else /* cmpxchg_relaxed */
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#ifndef cmpxchg_acquire
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#define cmpxchg_acquire(...) \
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__atomic_op_acquire(cmpxchg, __VA_ARGS__)
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#endif
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#ifndef cmpxchg_release
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#define cmpxchg_release(...) \
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__atomic_op_release(cmpxchg, __VA_ARGS__)
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#endif
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#ifndef cmpxchg
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#define cmpxchg(...) \
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__atomic_op_fence(cmpxchg, __VA_ARGS__)
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#endif
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#endif /* cmpxchg_relaxed */
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/* cmpxchg64_relaxed */
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#ifndef cmpxchg64_relaxed
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#define cmpxchg64_relaxed cmpxchg64
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#define cmpxchg64_acquire cmpxchg64
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#define cmpxchg64_release cmpxchg64
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#else /* cmpxchg64_relaxed */
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#ifndef cmpxchg64_acquire
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#define cmpxchg64_acquire(...) \
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__atomic_op_acquire(cmpxchg64, __VA_ARGS__)
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#endif
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#ifndef cmpxchg64_release
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#define cmpxchg64_release(...) \
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__atomic_op_release(cmpxchg64, __VA_ARGS__)
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#endif
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#ifndef cmpxchg64
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#define cmpxchg64(...) \
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__atomic_op_fence(cmpxchg64, __VA_ARGS__)
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#endif
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#endif /* cmpxchg64_relaxed */
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/* xchg_relaxed */
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#ifndef xchg_relaxed
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#define xchg_relaxed xchg
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#define xchg_acquire xchg
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#define xchg_release xchg
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#else /* xchg_relaxed */
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#ifndef xchg_acquire
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#define xchg_acquire(...) __atomic_op_acquire(xchg, __VA_ARGS__)
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#endif
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#ifndef xchg_release
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#define xchg_release(...) __atomic_op_release(xchg, __VA_ARGS__)
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#endif
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#ifndef xchg
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#define xchg(...) __atomic_op_fence(xchg, __VA_ARGS__)
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#endif
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#endif /* xchg_relaxed */
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/**
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* atomic_add_unless - add unless the number is already a given value
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