[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface, a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS interface, and IDMA/XOR engines, and depending on the model, also features one or two Gigabit Ethernet interfaces, two SATA II interfaces, one or two TWSI interfaces, one or two UARTs, a TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and an SDIO interface. This patch adds supports for the Marvell DB-88F6281-BP Development Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs, enabling support for the PCIe interface, the USB interface, the ethernet interfaces, the SATA interfaces, the TWSI interfaces, the UARTs, and the NAND controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This commit is contained in:
Saeed Bishara
Lennert Buytenhek
parent
9c2af6c57c
commit
651c74c74b
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@ -352,6 +352,16 @@ config ARCH_L7200
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If you have any questions or comments about the Linux kernel port
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to this board, send e-mail to <sjhill@cotw.com>.
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config ARCH_KIRKWOOD
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bool "Marvell Kirkwood"
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select PCI
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select PLAT_ORION
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help
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Support for the following Marvell Kirkwood series SoCs:
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88F6180, 88F6192 and 88F6281.
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config ARCH_KS8695
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bool "Micrel/Kendin KS8695"
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select GENERIC_GPIO
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@ -530,6 +540,8 @@ source "arch/arm/mach-omap2/Kconfig"
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source "arch/arm/mach-orion5x/Kconfig"
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/plat-s3c24xx/Kconfig"
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source "arch/arm/plat-s3c/Kconfig"
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@ -135,6 +135,7 @@ endif
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machine-$(CONFIG_ARCH_NETX) := netx
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machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
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machine-$(CONFIG_ARCH_DAVINCI) := davinci
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machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
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machine-$(CONFIG_ARCH_KS8695) := ks8695
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incdir-$(CONFIG_ARCH_MXC) := mxc
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machine-$(CONFIG_ARCH_MX3) := mx3
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@ -0,0 +1,25 @@
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if ARCH_KIRKWOOD
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menu "Marvell Kirkwood Implementations"
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config MACH_DB88F6281_BP
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bool "Marvell DB-88F6281-BP Development Board"
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help
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Say 'Y' here if you want your kernel to support the
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Marvell DB-88F6281-BP Development Board.
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config MACH_RD88F6192_NAS
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bool "Marvell RD-88F6192-NAS Reference Board"
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help
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Say 'Y' here if you want your kernel to support the
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Marvell RD-88F6192-NAS Reference Board.
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config MACH_RD88F6281
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bool "Marvell RD-88F6281 Reference Board"
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help
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Say 'Y' here if you want your kernel to support the
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Marvell RD-88F6281 Reference Board.
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endmenu
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endif
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@ -0,0 +1,5 @@
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obj-y += common.o addr-map.o irq.o pcie.o
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obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o
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obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
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obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6281-setup.o
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@ -0,0 +1,3 @@
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zreladdr-y := 0x00008000
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params_phys-y := 0x00000100
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initrd_phys-y := 0x00800000
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@ -0,0 +1,139 @@
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/*
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* arch/arm/mach-kirkwood/addr-map.c
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*
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* Address map functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <asm/hardware.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE 4
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#define ATTR_DEV_SPI_ROM 0x1e
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#define ATTR_DEV_BOOT 0x1d
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#define ATTR_DEV_NAND 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_MEM 0xe8
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN_CTRL_OFF 0x0000
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#define WIN_BASE_OFF 0x0004
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_HI_OFF 0x000c
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struct mbus_dram_target_info kirkwood_mbus_dram_info;
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static int __init cpu_win_can_remap(int win)
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{
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if (win < 4)
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return 1;
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return 0;
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}
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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void __iomem *addr = (void __iomem *)WIN_OFF(win);
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u32 ctrl;
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base &= 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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writel(base, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(win)) {
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if (remap < 0)
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remap = base;
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writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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void __init kirkwood_setup_cpu_mbus(void)
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{
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void __iomem *addr;
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 8; i++) {
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addr = (void __iomem *)WIN_OFF(i);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(i)) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/*
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* Setup windows for PCIe IO+MEM space.
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*/
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setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
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setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, -1);
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/*
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* Setup window for NAND controller.
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*/
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setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
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TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
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/*
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* Setup MBUS dram target info.
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*/
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kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(addr + DDR_BASE_CS_OFF(i));
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u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &kirkwood_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & 0xffff0000;
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w->size = (size | 0x0000ffff) + 1;
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}
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}
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kirkwood_mbus_dram_info.num_cs = cs;
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}
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@ -0,0 +1,326 @@
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/*
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* arch/arm/mach-kirkwood/common.c
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*
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* Core functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/mbus.h>
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#include <linux/mv643xx_eth.h>
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#include <linux/ata_platform.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/plat-orion/cache-feroceon-l2.h>
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#include <asm/plat-orion/ehci-orion.h>
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#include <asm/plat-orion/orion_nand.h>
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#include <asm/plat-orion/time.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc kirkwood_io_desc[] __initdata = {
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{
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.virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
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.length = KIRKWOOD_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init kirkwood_map_io(void)
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{
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iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
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}
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/*****************************************************************************
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* EHCI
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****************************************************************************/
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static struct orion_ehci_data kirkwood_ehci_data = {
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.dram = &kirkwood_mbus_dram_info,
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};
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static u64 ehci_dmamask = 0xffffffffUL;
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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static struct resource kirkwood_ehci_resources[] = {
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{
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.start = USB_PHYS_BASE,
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.end = USB_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_KIRKWOOD_USB,
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.end = IRQ_KIRKWOOD_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ehci = {
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.name = "orion-ehci",
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.id = 0,
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.dev = {
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.dma_mask = &ehci_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &kirkwood_ehci_data,
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},
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.resource = kirkwood_ehci_resources,
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.num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
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};
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void __init kirkwood_ehci_init(void)
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{
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platform_device_register(&kirkwood_ehci);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
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.t_clk = KIRKWOOD_TCLK,
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.dram = &kirkwood_mbus_dram_info,
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};
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static struct resource kirkwood_ge00_shared_resources[] = {
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{
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.name = "ge00 base",
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.start = GE00_PHYS_BASE + 0x2000,
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.end = GE00_PHYS_BASE + 0x3fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device kirkwood_ge00_shared = {
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.name = MV643XX_ETH_SHARED_NAME,
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.id = 0,
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.dev = {
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.platform_data = &kirkwood_ge00_shared_data,
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},
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.num_resources = 1,
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.resource = kirkwood_ge00_shared_resources,
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};
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static struct resource kirkwood_ge00_resources[] = {
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{
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.name = "ge00 irq",
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.start = IRQ_KIRKWOOD_GE00_SUM,
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.end = IRQ_KIRKWOOD_GE00_SUM,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_ge00 = {
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.name = MV643XX_ETH_NAME,
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.id = 0,
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.num_resources = 1,
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.resource = kirkwood_ge00_resources,
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};
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void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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eth_data->shared = &kirkwood_ge00_shared;
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kirkwood_ge00.dev.platform_data = eth_data;
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platform_device_register(&kirkwood_ge00_shared);
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platform_device_register(&kirkwood_ge00);
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}
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/*****************************************************************************
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* SoC RTC
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****************************************************************************/
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static struct resource kirkwood_rtc_resource = {
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.start = RTC_PHYS_BASE,
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.end = RTC_PHYS_BASE + SZ_16 - 1,
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.flags = IORESOURCE_MEM,
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};
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void __init kirkwood_rtc_init(void)
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{
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platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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static struct resource kirkwood_sata_resources[] = {
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{
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.name = "sata base",
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.start = SATA_PHYS_BASE,
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.end = SATA_PHYS_BASE + 0x5000 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "sata irq",
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.start = IRQ_KIRKWOOD_SATA,
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.end = IRQ_KIRKWOOD_SATA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_sata = {
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.name = "sata_mv",
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.id = 0,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(kirkwood_sata_resources),
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.resource = kirkwood_sata_resources,
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};
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void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
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{
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sata_data->dram = &kirkwood_mbus_dram_info;
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kirkwood_sata.dev.platform_data = sata_data;
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platform_device_register(&kirkwood_sata);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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static struct plat_serial8250_port kirkwood_uart0_data[] = {
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{
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.mapbase = UART0_PHYS_BASE,
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.membase = (char *)UART0_VIRT_BASE,
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.irq = IRQ_KIRKWOOD_UART_0,
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.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = KIRKWOOD_TCLK,
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}, {
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},
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};
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static struct resource kirkwood_uart0_resources[] = {
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{
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.start = UART0_PHYS_BASE,
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.end = UART0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_KIRKWOOD_UART_0,
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.end = IRQ_KIRKWOOD_UART_0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device kirkwood_uart0 = {
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.name = "serial8250",
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.id = 0,
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.dev = {
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.platform_data = kirkwood_uart0_data,
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},
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.resource = kirkwood_uart0_resources,
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.num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
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};
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void __init kirkwood_uart0_init(void)
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{
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platform_device_register(&kirkwood_uart0);
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}
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/*****************************************************************************
|
||||
* UART1
|
||||
****************************************************************************/
|
||||
static struct plat_serial8250_port kirkwood_uart1_data[] = {
|
||||
{
|
||||
.mapbase = UART1_PHYS_BASE,
|
||||
.membase = (char *)UART1_VIRT_BASE,
|
||||
.irq = IRQ_KIRKWOOD_UART_1,
|
||||
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = KIRKWOOD_TCLK,
|
||||
}, {
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource kirkwood_uart1_resources[] = {
|
||||
{
|
||||
.start = UART1_PHYS_BASE,
|
||||
.end = UART1_PHYS_BASE + 0xff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_KIRKWOOD_UART_1,
|
||||
.end = IRQ_KIRKWOOD_UART_1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device kirkwood_uart1 = {
|
||||
.name = "serial8250",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = kirkwood_uart1_data,
|
||||
},
|
||||
.resource = kirkwood_uart1_resources,
|
||||
.num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
|
||||
};
|
||||
|
||||
void __init kirkwood_uart1_init(void)
|
||||
{
|
||||
platform_device_register(&kirkwood_uart1);
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Time handling
|
||||
****************************************************************************/
|
||||
static void kirkwood_timer_init(void)
|
||||
{
|
||||
orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
|
||||
}
|
||||
|
||||
struct sys_timer kirkwood_timer = {
|
||||
.init = kirkwood_timer_init,
|
||||
};
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* General
|
||||
****************************************************************************/
|
||||
static char * __init kirkwood_id(void)
|
||||
{
|
||||
switch (readl(DEVICE_ID) & 0x3) {
|
||||
case 0:
|
||||
return "88F6180";
|
||||
case 1:
|
||||
return "88F6192";
|
||||
case 2:
|
||||
return "88F6281";
|
||||
}
|
||||
|
||||
return "unknown 88F6000 variant";
|
||||
}
|
||||
|
||||
void __init kirkwood_init(void)
|
||||
{
|
||||
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
|
||||
kirkwood_id(), KIRKWOOD_TCLK);
|
||||
|
||||
kirkwood_setup_cpu_mbus();
|
||||
|
||||
#ifdef CONFIG_CACHE_FEROCEON_L2
|
||||
feroceon_l2_init(1);
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/common.h
|
||||
*
|
||||
* Core functions for Marvell Kirkwood SoCs
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_KIRKWOOD_COMMON_H
|
||||
#define __ARCH_KIRKWOOD_COMMON_H
|
||||
|
||||
struct mv643xx_eth_platform_data;
|
||||
struct mv_sata_platform_data;
|
||||
|
||||
/*
|
||||
* Basic Kirkwood init functions used early by machine-setup.
|
||||
*/
|
||||
void kirkwood_map_io(void);
|
||||
void kirkwood_init(void);
|
||||
void kirkwood_init_irq(void);
|
||||
|
||||
extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
|
||||
void kirkwood_setup_cpu_mbus(void);
|
||||
void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
|
||||
int maj, int min);
|
||||
void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
|
||||
int maj, int min);
|
||||
|
||||
void kirkwood_ehci_init(void);
|
||||
void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
|
||||
void kirkwood_pcie_init(void);
|
||||
void kirkwood_rtc_init(void);
|
||||
void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
|
||||
void kirkwood_uart0_init(void);
|
||||
void kirkwood_uart1_init(void);
|
||||
|
||||
extern struct sys_timer kirkwood_timer;
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/db88f6281-bp-setup.c
|
||||
*
|
||||
* Marvell DB-88F6281-BP Development Board Setup
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include "common.h"
|
||||
|
||||
static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
|
||||
.phy_addr = 8,
|
||||
};
|
||||
|
||||
static struct mv_sata_platform_data db88f6281_sata_data = {
|
||||
.n_ports = 2,
|
||||
};
|
||||
|
||||
static void __init db88f6281_init(void)
|
||||
{
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
kirkwood_init();
|
||||
|
||||
kirkwood_ehci_init();
|
||||
kirkwood_ge00_init(&db88f6281_ge00_data);
|
||||
kirkwood_rtc_init();
|
||||
kirkwood_sata_init(&db88f6281_sata_data);
|
||||
kirkwood_uart0_init();
|
||||
kirkwood_uart1_init();
|
||||
}
|
||||
|
||||
static int __init db88f6281_pci_init(void)
|
||||
{
|
||||
if (machine_is_db88f6281_bp())
|
||||
kirkwood_pcie_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(db88f6281_pci_init);
|
||||
|
||||
MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
|
||||
/* Maintainer: Saeed Bishara <saeed@marvell.com> */
|
||||
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
|
||||
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
|
||||
.boot_params = 0x00000100,
|
||||
.init_machine = db88f6281_init,
|
||||
.map_io = kirkwood_map_io,
|
||||
.init_irq = kirkwood_init_irq,
|
||||
.timer = &kirkwood_timer,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/irq.c
|
||||
*
|
||||
* Kirkwood IRQ handling.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <asm/plat-orion/irq.h>
|
||||
#include "common.h"
|
||||
|
||||
void __init kirkwood_init_irq(void)
|
||||
{
|
||||
orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
|
||||
orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
|
||||
}
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/pcie.c
|
||||
*
|
||||
* PCIe functions for Marvell Kirkwood SoCs
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/mbus.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/plat-orion/pcie.h>
|
||||
#include "common.h"
|
||||
|
||||
|
||||
#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
|
||||
|
||||
static int pcie_valid_config(int bus, int dev)
|
||||
{
|
||||
/*
|
||||
* Don't go out when trying to access --
|
||||
* 1. nonexisting device on local bus
|
||||
* 2. where there's no device connected (no link)
|
||||
*/
|
||||
if (bus == 0 && dev == 0)
|
||||
return 1;
|
||||
|
||||
if (!orion_pcie_link_up(PCIE_BASE))
|
||||
return 0;
|
||||
|
||||
if (bus == 0 && dev != 1)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* PCIe config cycles are done by programming the PCIE_CONF_ADDR register
|
||||
* and then reading the PCIE_CONF_DATA register. Need to make sure these
|
||||
* transactions are atomic.
|
||||
*/
|
||||
static DEFINE_SPINLOCK(kirkwood_pcie_lock);
|
||||
|
||||
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
||||
int size, u32 *val)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
|
||||
*val = 0xffffffff;
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&kirkwood_pcie_lock, flags);
|
||||
ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
|
||||
spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
spin_lock_irqsave(&kirkwood_pcie_lock, flags);
|
||||
ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
|
||||
spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct pci_ops pcie_ops = {
|
||||
.read = pcie_rd_conf,
|
||||
.write = pcie_wr_conf,
|
||||
};
|
||||
|
||||
|
||||
static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
/*
|
||||
* Generic PCIe unit setup.
|
||||
*/
|
||||
orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
|
||||
|
||||
/*
|
||||
* Request resources.
|
||||
*/
|
||||
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
|
||||
if (!res)
|
||||
panic("pcie_setup unable to alloc resources");
|
||||
|
||||
/*
|
||||
* IORESOURCE_IO
|
||||
*/
|
||||
res[0].name = "PCIe I/O Space";
|
||||
res[0].flags = IORESOURCE_IO;
|
||||
res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
|
||||
res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
|
||||
if (request_resource(&ioport_resource, &res[0]))
|
||||
panic("Request PCIe IO resource failed\n");
|
||||
sys->resource[0] = &res[0];
|
||||
|
||||
/*
|
||||
* IORESOURCE_MEM
|
||||
*/
|
||||
res[1].name = "PCIe Memory Space";
|
||||
res[1].flags = IORESOURCE_MEM;
|
||||
res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
|
||||
res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
|
||||
if (request_resource(&iomem_resource, &res[1]))
|
||||
panic("Request PCIe Memory resource failed\n");
|
||||
sys->resource[1] = &res[1];
|
||||
|
||||
sys->resource[2] = NULL;
|
||||
sys->io_offset = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void __devinit rc_pci_fixup(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
* Prevent enumeration of root complex.
|
||||
*/
|
||||
if (dev->bus->parent == NULL && dev->devfn == 0) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
||||
dev->resource[i].start = 0;
|
||||
dev->resource[i].end = 0;
|
||||
dev->resource[i].flags = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
|
||||
|
||||
static struct pci_bus __init *
|
||||
kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
struct pci_bus *bus;
|
||||
|
||||
if (nr == 0) {
|
||||
bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
|
||||
} else {
|
||||
bus = NULL;
|
||||
BUG();
|
||||
}
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
return IRQ_KIRKWOOD_PCIE;
|
||||
}
|
||||
|
||||
static struct hw_pci kirkwood_pci __initdata = {
|
||||
.nr_controllers = 1,
|
||||
.swizzle = pci_std_swizzle,
|
||||
.setup = kirkwood_pcie_setup,
|
||||
.scan = kirkwood_pcie_scan_bus,
|
||||
.map_irq = kirkwood_pcie_map_irq,
|
||||
};
|
||||
|
||||
void __init kirkwood_pcie_init(void)
|
||||
{
|
||||
pci_common_init(&kirkwood_pci);
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
|
||||
*
|
||||
* Marvell RD-88F6192-NAS Reference Board Setup
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include "common.h"
|
||||
|
||||
#define RD88F6192_GPIO_USB_VBUS 10
|
||||
|
||||
static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
|
||||
.phy_addr = 8,
|
||||
};
|
||||
|
||||
static struct mv_sata_platform_data rd88f6192_sata_data = {
|
||||
.n_ports = 2,
|
||||
};
|
||||
|
||||
static void __init rd88f6192_init(void)
|
||||
{
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
kirkwood_init();
|
||||
|
||||
kirkwood_ehci_init();
|
||||
kirkwood_ge00_init(&rd88f6192_ge00_data);
|
||||
kirkwood_rtc_init();
|
||||
kirkwood_sata_init(&rd88f6192_sata_data);
|
||||
kirkwood_uart0_init();
|
||||
}
|
||||
|
||||
static int __init rd88f6192_pci_init(void)
|
||||
{
|
||||
if (machine_is_rd88f6192_nas())
|
||||
kirkwood_pcie_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(rd88f6192_pci_init);
|
||||
|
||||
MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
|
||||
/* Maintainer: Saeed Bishara <saeed@marvell.com> */
|
||||
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
|
||||
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
|
||||
.boot_params = 0x00000100,
|
||||
.init_machine = rd88f6192_init,
|
||||
.map_io = kirkwood_map_io,
|
||||
.init_irq = kirkwood_init_irq,
|
||||
.timer = &kirkwood_timer,
|
||||
MACHINE_END
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* arch/arm/mach-kirkwood/rd88f6281-setup.c
|
||||
*
|
||||
* Marvell RD-88F6281 Reference Board Setup
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/ata_platform.h>
|
||||
#include <linux/mv643xx_eth.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/pci.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
#include <asm/plat-orion/orion_nand.h>
|
||||
#include "common.h"
|
||||
|
||||
static struct mtd_partition rd88f6281_nand_parts[] = {
|
||||
{
|
||||
.name = "u-boot",
|
||||
.offset = 0,
|
||||
.size = SZ_1M
|
||||
}, {
|
||||
.name = "uImage",
|
||||
.offset = MTDPART_OFS_NXTBLK,
|
||||
.size = SZ_2M
|
||||
}, {
|
||||
.name = "root",
|
||||
.offset = MTDPART_OFS_NXTBLK,
|
||||
.size = MTDPART_SIZ_FULL
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource rd88f6281_nand_resource = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = KIRKWOOD_NAND_MEM_PHYS_BASE,
|
||||
.end = KIRKWOOD_NAND_MEM_PHYS_BASE +
|
||||
KIRKWOOD_NAND_MEM_SIZE - 1,
|
||||
};
|
||||
|
||||
static struct orion_nand_data rd88f6281_nand_data = {
|
||||
.parts = rd88f6281_nand_parts,
|
||||
.nr_parts = ARRAY_SIZE(rd88f6281_nand_parts),
|
||||
.cle = 0,
|
||||
.ale = 1,
|
||||
.width = 8,
|
||||
};
|
||||
|
||||
static struct platform_device rd88f6281_nand_flash = {
|
||||
.name = "orion_nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &rd88f6281_nand_data,
|
||||
},
|
||||
.resource = &rd88f6281_nand_resource,
|
||||
.num_resources = 1,
|
||||
};
|
||||
|
||||
static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
|
||||
.phy_addr = -1,
|
||||
};
|
||||
|
||||
static struct mv_sata_platform_data rd88f6281_sata_data = {
|
||||
.n_ports = 2,
|
||||
};
|
||||
|
||||
static void __init rd88f6281_init(void)
|
||||
{
|
||||
/*
|
||||
* Basic setup. Needs to be called early.
|
||||
*/
|
||||
kirkwood_init();
|
||||
|
||||
kirkwood_ehci_init();
|
||||
kirkwood_ge00_init(&rd88f6281_ge00_data);
|
||||
kirkwood_rtc_init();
|
||||
kirkwood_sata_init(&rd88f6281_sata_data);
|
||||
kirkwood_uart0_init();
|
||||
kirkwood_uart1_init();
|
||||
|
||||
platform_device_register(&rd88f6281_nand_flash);
|
||||
}
|
||||
|
||||
static int __init rd88f6281_pci_init(void)
|
||||
{
|
||||
if (machine_is_rd88f6281())
|
||||
kirkwood_pcie_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
subsys_initcall(rd88f6281_pci_init);
|
||||
|
||||
MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
|
||||
/* Maintainer: Saeed Bishara <saeed@marvell.com> */
|
||||
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
|
||||
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
|
||||
.boot_params = 0x00000100,
|
||||
.init_machine = rd88f6281_init,
|
||||
.map_io = kirkwood_map_io,
|
||||
.init_irq = kirkwood_init_irq,
|
||||
.timer = &kirkwood_timer,
|
||||
MACHINE_END
|
||||
|
|
@ -365,7 +365,7 @@ config CPU_XSC3
|
|||
# Feroceon
|
||||
config CPU_FEROCEON
|
||||
bool
|
||||
depends on ARCH_ORION5X || ARCH_LOKI
|
||||
depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD
|
||||
default y
|
||||
select CPU_32v5
|
||||
select CPU_ABRT_EV5T
|
||||
|
|
@ -716,7 +716,7 @@ config OUTER_CACHE
|
|||
|
||||
config CACHE_FEROCEON_L2
|
||||
bool "Enable the Feroceon L2 cache controller"
|
||||
depends on FOOBAR
|
||||
depends on ARCH_KIRKWOOD
|
||||
default y
|
||||
select OUTER_CACHE
|
||||
help
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/debug-macro.S
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
.macro addruart,rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE
|
||||
ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE
|
||||
orr \rx, \rx, #0x00012000
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
|
|
@ -0,0 +1 @@
|
|||
/* empty */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for Marvell Kirkwood platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
ldr \base, =IRQ_VIRT_BASE
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
@ check low interrupts
|
||||
ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
|
||||
ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
|
||||
mov \irqnr, #31
|
||||
ands \irqstat, \irqstat, \tmp
|
||||
bne 1001f
|
||||
|
||||
@ if no low interrupts set, check high interrupts
|
||||
ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
|
||||
ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
|
||||
mov \irqnr, #63
|
||||
ands \irqstat, \irqstat, \tmp
|
||||
|
||||
@ find first active interrupt source
|
||||
1001: clzne \irqstat, \irqstat
|
||||
subne \irqnr, \irqnr, \irqstat
|
||||
.endm
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/hardware.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include "kirkwood.h"
|
||||
|
||||
#define pcibios_assign_all_busses() 1
|
||||
|
||||
#define PCIBIOS_MIN_IO 0x00001000
|
||||
#define PCIBIOS_MIN_MEM 0x01000000
|
||||
#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/io.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#include "kirkwood.h"
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
static inline void __iomem *__io(unsigned long addr)
|
||||
{
|
||||
return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
|
||||
+ KIRKWOOD_PCIE_IO_VIRT_BASE);
|
||||
}
|
||||
|
||||
#define __io(a) __io(a)
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/irqs.h
|
||||
*
|
||||
* IRQ definitions for Marvell Kirkwood SoCs
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H
|
||||
#define __ASM_ARCH_IRQS_H
|
||||
|
||||
#include "kirkwood.h" /* need GPIO_MAX */
|
||||
|
||||
/*
|
||||
* Low Interrupt Controller
|
||||
*/
|
||||
#define IRQ_KIRKWOOD_HIGH_SUM 0
|
||||
#define IRQ_KIRKWOOD_BRIDGE 1
|
||||
#define IRQ_KIRKWOOD_HOST2CPU 2
|
||||
#define IRQ_KIRKWOOD_CPU2HOST 3
|
||||
#define IRQ_KIRKWOOD_XOR_00 5
|
||||
#define IRQ_KIRKWOOD_XOR_01 6
|
||||
#define IRQ_KIRKWOOD_XOR_10 7
|
||||
#define IRQ_KIRKWOOD_XOR_11 8
|
||||
#define IRQ_KIRKWOOD_PCIE 9
|
||||
#define IRQ_KIRKWOOD_GE00_SUM 11
|
||||
#define IRQ_KIRKWOOD_GE01_SUM 15
|
||||
#define IRQ_KIRKWOOD_USB 19
|
||||
#define IRQ_KIRKWOOD_SATA 21
|
||||
#define IRQ_KIRKWOOD_CRYPTO 22
|
||||
#define IRQ_KIRKWOOD_SPI 23
|
||||
#define IRQ_KIRKWOOD_I2S 24
|
||||
#define IRQ_KIRKWOOD_TS_0 26
|
||||
#define IRQ_KIRKWOOD_SDIO 28
|
||||
#define IRQ_KIRKWOOD_TWSI 29
|
||||
#define IRQ_KIRKWOOD_AVB 30
|
||||
#define IRQ_KIRKWOOD_TDMI 31
|
||||
|
||||
/*
|
||||
* High Interrupt Controller
|
||||
*/
|
||||
#define IRQ_KIRKWOOD_UART_0 33
|
||||
#define IRQ_KIRKWOOD_UART_1 34
|
||||
#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35
|
||||
#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36
|
||||
#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37
|
||||
#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38
|
||||
#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39
|
||||
#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40
|
||||
#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
|
||||
|
||||
/*
|
||||
* KIRKWOOD General Purpose Pins
|
||||
*/
|
||||
#define IRQ_KIRKWOOD_GPIO_START 64
|
||||
#define NR_GPIO_IRQS GPIO_MAX
|
||||
|
||||
#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/kirkwood.h
|
||||
*
|
||||
* Generic definitions for Marvell Kirkwood SoC flavors:
|
||||
* 88F6180, 88F6192 and 88F6281.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_KIRKWOOD_H
|
||||
#define __ASM_ARCH_KIRKWOOD_H
|
||||
|
||||
/*
|
||||
* Marvell Kirkwood address maps.
|
||||
*
|
||||
* phys
|
||||
* e0000000 PCIe Memory space
|
||||
* f1000000 on-chip peripheral registers
|
||||
* f2000000 PCIe I/O space
|
||||
* f3000000 NAND controller address window
|
||||
*
|
||||
* virt phys size
|
||||
* fee00000 f1000000 1M on-chip peripheral registers
|
||||
* fef00000 f2000000 1M PCIe I/O space
|
||||
*/
|
||||
|
||||
#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
|
||||
#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K
|
||||
* is the minimal window size
|
||||
*/
|
||||
|
||||
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
|
||||
#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
|
||||
#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
|
||||
#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
|
||||
|
||||
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
|
||||
#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
|
||||
#define KIRKWOOD_REGS_SIZE SZ_1M
|
||||
|
||||
#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
|
||||
#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
|
||||
|
||||
/*
|
||||
* MBUS bridge registers.
|
||||
*/
|
||||
#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
|
||||
#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
|
||||
#define CPU_RESET 0x00000002
|
||||
//#define L2_WRITETHROUGH 0x00020000
|
||||
#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
|
||||
#define SOFT_RESET_OUT_EN 0x00000004
|
||||
#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
|
||||
#define SOFT_RESET 0x00000001
|
||||
#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
|
||||
#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
|
||||
#define BRIDGE_INT_TIMER0 0x0002
|
||||
#define BRIDGE_INT_TIMER1 0x0004
|
||||
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
|
||||
#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
|
||||
#define IRQ_CAUSE_LOW_OFF 0x0000
|
||||
#define IRQ_MASK_LOW_OFF 0x0004
|
||||
#define IRQ_CAUSE_HIGH_OFF 0x0010
|
||||
#define IRQ_MASK_HIGH_OFF 0x0014
|
||||
#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
|
||||
|
||||
/*
|
||||
* Register Map
|
||||
*/
|
||||
#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
|
||||
#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
|
||||
|
||||
#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
|
||||
#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
|
||||
#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
|
||||
#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
|
||||
#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
|
||||
#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
|
||||
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
|
||||
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
|
||||
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
|
||||
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
|
||||
|
||||
#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
|
||||
|
||||
#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
|
||||
|
||||
#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
|
||||
#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
|
||||
|
||||
#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
|
||||
|
||||
|
||||
#define GPIO_MAX 50
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#define PHYS_OFFSET UL(0x00000000)
|
||||
|
||||
#define __virt_to_bus(x) __virt_to_phys(x)
|
||||
#define __bus_to_virt(x) __phys_to_virt(x)
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/system.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
/*
|
||||
* Enable soft reset to assert RSTOUTn.
|
||||
*/
|
||||
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
|
||||
|
||||
/*
|
||||
* Assert soft reset.
|
||||
*/
|
||||
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
|
||||
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/timex.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
|
||||
#define KIRKWOOD_TCLK 166666667
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/uncompress.h
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/arch/kirkwood.h>
|
||||
|
||||
#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
|
||||
|
||||
static void putc(const char c)
|
||||
{
|
||||
unsigned char *base = SERIAL_BASE;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 0x1000; i++) {
|
||||
if (base[UART_LSR << 2] & UART_LSR_THRE)
|
||||
break;
|
||||
barrier();
|
||||
}
|
||||
|
||||
base[UART_TX << 2] = c;
|
||||
}
|
||||
|
||||
static void flush(void)
|
||||
{
|
||||
unsigned char *base = SERIAL_BASE;
|
||||
unsigned char mask;
|
||||
int i;
|
||||
|
||||
mask = UART_LSR_TEMT | UART_LSR_THRE;
|
||||
|
||||
for (i = 0; i < 0x1000; i++) {
|
||||
if ((base[UART_LSR << 2] & mask) == mask)
|
||||
break;
|
||||
barrier();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
/*
|
||||
* include/asm-arm/arch-kirkwood/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xfe800000
|
||||
Loading…
Reference in New Issue