bcma: add PMU clock support for BCM4706
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -226,6 +226,36 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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return (fc / div) * 1000000;
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}
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static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, ndiv, p1div, p2div;
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u32 clock;
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BUG_ON(!m || m > 4);
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/* Get N, P1 and P2 dividers to determine CPU clock */
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tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
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ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
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>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
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p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
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>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
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p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
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>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
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tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
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/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
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clock = (25000000 / 4) * ndiv * p2div / p1div;
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else
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/* Fixed reference clock 25MHz and m = 2 */
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clock = (25000000 / 2) * ndiv * p2div / p1div;
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if (m == BCMA_CC_PMU5_MAINPLL_SSB)
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clock = clock / 4;
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return clock;
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}
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/* query bus clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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{
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@ -245,8 +275,8 @@ u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM53572:
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return 75000000;
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default:
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@ -267,6 +297,10 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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if (cc->pmu.rev >= 5) {
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u32 pll;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock_bcm4706(cc,
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BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_CPU);
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case BCMA_CHIP_ID_BCM5356:
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pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
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break;
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@ -279,8 +313,6 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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break;
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}
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/* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
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return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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}
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@ -88,6 +88,11 @@
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#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
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#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
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#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
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#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
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#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
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#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
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#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
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#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
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#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
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#define BCMA_CC_JCMD_START 0x80000000
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#define BCMA_CC_JCMD_BUSY 0x80000000
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@ -280,6 +285,15 @@
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/* 4706 PMU */
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#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
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#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
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#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
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#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
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#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
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#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
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#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
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#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
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#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
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#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
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/* ALP clock on pre-PMU chips */
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#define BCMA_CC_PMU_ALP_CLOCK 20000000
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