ARM: dts: imx7: correct enet ipg clock
ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus clock. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -120,7 +120,7 @@
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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@ -1091,7 +1091,7 @@
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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