i2c: add support for microchip fpga i2c controllers
Add Microchip CoreI2C i2c controller support. This driver supports the "hard" i2c controller on the Microchip PolarFire SoC & the basic feature set for "soft" i2c controller implemtations in the FPGA fabric. Co-developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Conor Dooley
Wolfram Sang
parent
24fff66f1f
commit
64a6f1c498
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@ -782,6 +782,17 @@ config I2C_MESON
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If you say yes to this option, support will be included for the
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I2C interface on the Amlogic Meson family of SoCs.
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config I2C_MICROCHIP_CORE
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tristate "Microchip FPGA I2C controller"
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depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
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depends on OF
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help
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If you say yes to this option, support will be included for the
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I2C interface on Microchip FPGAs.
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This driver can also be built as a module. If so, the module will be
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called i2c-microchip-core.
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config I2C_MPC
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tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
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depends on PPC
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@ -78,6 +78,7 @@ obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
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obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
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obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o
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obj-$(CONFIG_I2C_MESON) += i2c-meson.o
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obj-$(CONFIG_I2C_MICROCHIP_CORE) += i2c-microchip-corei2c.o
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obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
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obj-$(CONFIG_I2C_MT65XX) += i2c-mt65xx.o
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obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
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@ -0,0 +1,480 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip CoreI2C I2C controller driver
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*
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* Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
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*
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* Author: Daire McNamara <daire.mcnamara@microchip.com>
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define CORE_I2C_CTRL (0x00)
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#define CTRL_CR0 BIT(0)
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#define CTRL_CR1 BIT(1)
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#define CTRL_AA BIT(2)
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#define CTRL_SI BIT(3)
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#define CTRL_STO BIT(4)
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#define CTRL_STA BIT(5)
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#define CTRL_ENS1 BIT(6)
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#define CTRL_CR2 BIT(7)
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#define STATUS_BUS_ERROR (0x00)
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#define STATUS_M_START_SENT (0x08)
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#define STATUS_M_REPEATED_START_SENT (0x10)
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#define STATUS_M_SLAW_ACK (0x18)
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#define STATUS_M_SLAW_NACK (0x20)
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#define STATUS_M_TX_DATA_ACK (0x28)
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#define STATUS_M_TX_DATA_NACK (0x30)
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#define STATUS_M_ARB_LOST (0x38)
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#define STATUS_M_SLAR_ACK (0x40)
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#define STATUS_M_SLAR_NACK (0x48)
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#define STATUS_M_RX_DATA_ACKED (0x50)
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#define STATUS_M_RX_DATA_NACKED (0x58)
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#define STATUS_S_SLAW_ACKED (0x60)
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#define STATUS_S_ARB_LOST_SLAW_ACKED (0x68)
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#define STATUS_S_GENERAL_CALL_ACKED (0x70)
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#define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED (0x78)
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#define STATUS_S_RX_DATA_ACKED (0x80)
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#define STATUS_S_RX_DATA_NACKED (0x88)
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#define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
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#define STATUS_S_GENERAL_CALL_RX_DATA_NACKED (0x98)
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#define STATUS_S_RX_STOP (0xA0)
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#define STATUS_S_SLAR_ACKED (0xA8)
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#define STATUS_S_ARB_LOST_SLAR_ACKED (0xB0)
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#define STATUS_S_TX_DATA_ACK (0xB8)
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#define STATUS_S_TX_DATA_NACK (0xC0)
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#define STATUS_LAST_DATA_ACK (0xC8)
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#define STATUS_M_SMB_MASTER_RESET (0xD0)
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#define STATUS_S_SCL_LOW_TIMEOUT (0xD8) /* 25 ms */
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#define STATUS_NO_STATE_INFO (0xF8)
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#define CORE_I2C_STATUS (0x04)
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#define CORE_I2C_DATA (0x08)
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#define WRITE_BIT (0x0)
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#define READ_BIT (0x1)
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#define SLAVE_ADDR_SHIFT (1)
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#define CORE_I2C_SLAVE0_ADDR (0x0c)
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#define GENERAL_CALL_BIT (0x0)
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#define CORE_I2C_SMBUS (0x10)
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#define SMBALERT_INT_ENB (0x0)
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#define SMBSUS_INT_ENB (0x1)
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#define SMBUS_ENB (0x2)
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#define SMBALERT_NI_STATUS (0x3)
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#define SMBALERT_NO_CTRL (0x4)
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#define SMBSUS_NI_STATUS (0x5)
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#define SMBSUS_NO_CTRL (0x6)
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#define SMBUS_RESET (0x7)
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#define CORE_I2C_FREQ (0x14)
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#define CORE_I2C_GLITCHREG (0x18)
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#define CORE_I2C_SLAVE1_ADDR (0x1c)
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#define PCLK_DIV_960 (CTRL_CR2)
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#define PCLK_DIV_256 (0)
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#define PCLK_DIV_224 (CTRL_CR0)
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#define PCLK_DIV_192 (CTRL_CR1)
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#define PCLK_DIV_160 (CTRL_CR0 | CTRL_CR1)
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#define PCLK_DIV_120 (CTRL_CR0 | CTRL_CR2)
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#define PCLK_DIV_60 (CTRL_CR1 | CTRL_CR2)
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#define BCLK_DIV_8 (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
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#define CLK_MASK (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
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/**
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* struct mchp_corei2c_dev - Microchip CoreI2C device private data
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*
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* @base: pointer to register struct
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* @dev: device reference
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* @i2c_clk: clock reference for i2c input clock
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* @buf: pointer to msg buffer for easier use
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* @msg_complete: xfer completion object
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* @adapter: core i2c abstraction
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* @msg_err: error code for completed message
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* @bus_clk_rate: current i2c bus clock rate
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* @isr_status: cached copy of local ISR status
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* @msg_len: number of bytes transferred in msg
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* @addr: address of the current slave
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*/
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struct mchp_corei2c_dev {
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void __iomem *base;
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struct device *dev;
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struct clk *i2c_clk;
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u8 *buf;
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struct completion msg_complete;
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struct i2c_adapter adapter;
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int msg_err;
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u32 bus_clk_rate;
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u32 isr_status;
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u16 msg_len;
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u8 addr;
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};
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static void mchp_corei2c_core_disable(struct mchp_corei2c_dev *idev)
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{
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u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl &= ~CTRL_ENS1;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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}
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static void mchp_corei2c_core_enable(struct mchp_corei2c_dev *idev)
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{
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u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl |= CTRL_ENS1;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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}
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static void mchp_corei2c_reset(struct mchp_corei2c_dev *idev)
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{
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mchp_corei2c_core_disable(idev);
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mchp_corei2c_core_enable(idev);
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}
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static inline void mchp_corei2c_stop(struct mchp_corei2c_dev *idev)
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{
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u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl |= CTRL_STO;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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}
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static inline int mchp_corei2c_set_divisor(u32 rate,
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struct mchp_corei2c_dev *idev)
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{
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u8 clkval, ctrl;
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if (rate >= 960)
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clkval = PCLK_DIV_960;
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else if (rate >= 256)
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clkval = PCLK_DIV_256;
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else if (rate >= 224)
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clkval = PCLK_DIV_224;
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else if (rate >= 192)
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clkval = PCLK_DIV_192;
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else if (rate >= 160)
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clkval = PCLK_DIV_160;
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else if (rate >= 120)
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clkval = PCLK_DIV_120;
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else if (rate >= 60)
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clkval = PCLK_DIV_60;
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else if (rate >= 8)
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clkval = BCLK_DIV_8;
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else
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return -EINVAL;
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl &= ~CLK_MASK;
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ctrl |= clkval;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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if ((ctrl & CLK_MASK) != clkval)
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return -EIO;
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return 0;
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}
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static int mchp_corei2c_init(struct mchp_corei2c_dev *idev)
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{
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u32 clk_rate = clk_get_rate(idev->i2c_clk);
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u32 divisor = clk_rate / idev->bus_clk_rate;
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int ret;
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ret = mchp_corei2c_set_divisor(divisor, idev);
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if (ret)
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return ret;
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mchp_corei2c_reset(idev);
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return 0;
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}
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static void mchp_corei2c_empty_rx(struct mchp_corei2c_dev *idev)
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{
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u8 ctrl;
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if (idev->msg_len > 0) {
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*idev->buf++ = readb(idev->base + CORE_I2C_DATA);
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idev->msg_len--;
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}
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if (idev->msg_len == 0) {
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl &= ~CTRL_AA;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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}
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}
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static int mchp_corei2c_fill_tx(struct mchp_corei2c_dev *idev)
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{
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if (idev->msg_len > 0)
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writeb(*idev->buf++, idev->base + CORE_I2C_DATA);
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idev->msg_len--;
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return 0;
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}
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static irqreturn_t mchp_corei2c_handle_isr(struct mchp_corei2c_dev *idev)
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{
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u32 status = idev->isr_status;
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u8 ctrl;
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bool last_byte = false, finished = false;
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if (!idev->buf)
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return IRQ_NONE;
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switch (status) {
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case STATUS_M_START_SENT:
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case STATUS_M_REPEATED_START_SENT:
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl &= ~CTRL_STA;
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writeb(idev->addr, idev->base + CORE_I2C_DATA);
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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if (idev->msg_len == 0)
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finished = true;
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break;
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case STATUS_M_ARB_LOST:
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idev->msg_err = -EAGAIN;
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finished = true;
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break;
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case STATUS_M_SLAW_ACK:
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case STATUS_M_TX_DATA_ACK:
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if (idev->msg_len > 0)
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mchp_corei2c_fill_tx(idev);
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else
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last_byte = true;
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break;
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case STATUS_M_TX_DATA_NACK:
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case STATUS_M_SLAR_NACK:
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case STATUS_M_SLAW_NACK:
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idev->msg_err = -ENXIO;
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last_byte = true;
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break;
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case STATUS_M_SLAR_ACK:
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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if (idev->msg_len == 1u) {
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ctrl &= ~CTRL_AA;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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} else {
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ctrl |= CTRL_AA;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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}
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if (idev->msg_len < 1u)
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last_byte = true;
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break;
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case STATUS_M_RX_DATA_ACKED:
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mchp_corei2c_empty_rx(idev);
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break;
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case STATUS_M_RX_DATA_NACKED:
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mchp_corei2c_empty_rx(idev);
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if (idev->msg_len == 0)
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last_byte = true;
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break;
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default:
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break;
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}
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/* On the last byte to be transmitted, send STOP */
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if (last_byte)
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mchp_corei2c_stop(idev);
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if (last_byte || finished)
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complete(&idev->msg_complete);
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return IRQ_HANDLED;
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}
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static irqreturn_t mchp_corei2c_isr(int irq, void *_dev)
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{
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struct mchp_corei2c_dev *idev = _dev;
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irqreturn_t ret = IRQ_NONE;
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u8 ctrl;
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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if (ctrl & CTRL_SI) {
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idev->isr_status = readb(idev->base + CORE_I2C_STATUS);
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ret = mchp_corei2c_handle_isr(idev);
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}
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl &= ~CTRL_SI;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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return ret;
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}
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static int mchp_corei2c_xfer_msg(struct mchp_corei2c_dev *idev,
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struct i2c_msg *msg)
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{
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u8 ctrl;
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unsigned long time_left;
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idev->addr = i2c_8bit_addr_from_msg(msg);
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idev->msg_len = msg->len;
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idev->buf = msg->buf;
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idev->msg_err = 0;
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reinit_completion(&idev->msg_complete);
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mchp_corei2c_core_enable(idev);
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ctrl = readb(idev->base + CORE_I2C_CTRL);
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ctrl |= CTRL_STA;
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writeb(ctrl, idev->base + CORE_I2C_CTRL);
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time_left = wait_for_completion_timeout(&idev->msg_complete,
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idev->adapter.timeout);
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if (!time_left)
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return -ETIMEDOUT;
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return idev->msg_err;
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}
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static int mchp_corei2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct mchp_corei2c_dev *idev = i2c_get_adapdata(adap);
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int i, ret;
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for (i = 0; i < num; i++) {
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ret = mchp_corei2c_xfer_msg(idev, msgs++);
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if (ret)
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return ret;
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}
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return num;
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}
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static u32 mchp_corei2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm mchp_corei2c_algo = {
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.master_xfer = mchp_corei2c_xfer,
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.functionality = mchp_corei2c_func,
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};
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static int mchp_corei2c_probe(struct platform_device *pdev)
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{
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struct mchp_corei2c_dev *idev;
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struct resource *res;
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int irq, ret;
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idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
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if (!idev)
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return -ENOMEM;
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idev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(idev->base))
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return PTR_ERR(idev->base);
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irq = platform_get_irq(pdev, 0);
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if (irq <= 0)
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return dev_err_probe(&pdev->dev, -ENXIO,
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"invalid IRQ %d for I2C controller\n", irq);
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idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(idev->i2c_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(idev->i2c_clk),
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"missing clock\n");
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idev->dev = &pdev->dev;
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init_completion(&idev->msg_complete);
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|
||||
ret = device_property_read_u32(idev->dev, "clock-frequency",
|
||||
&idev->bus_clk_rate);
|
||||
if (ret || !idev->bus_clk_rate) {
|
||||
dev_info(&pdev->dev, "default to 100kHz\n");
|
||||
idev->bus_clk_rate = 100000;
|
||||
}
|
||||
|
||||
if (idev->bus_clk_rate > 400000)
|
||||
return dev_err_probe(&pdev->dev, -EINVAL,
|
||||
"clock-frequency too high: %d\n",
|
||||
idev->bus_clk_rate);
|
||||
|
||||
/*
|
||||
* This driver supports both the hard peripherals & soft FPGA cores.
|
||||
* The hard peripherals do not have shared IRQs, but we don't have
|
||||
* control over what way the interrupts are wired for the soft cores.
|
||||
*/
|
||||
ret = devm_request_irq(&pdev->dev, irq, mchp_corei2c_isr, IRQF_SHARED,
|
||||
pdev->name, idev);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret,
|
||||
"failed to claim irq %d\n", irq);
|
||||
|
||||
ret = clk_prepare_enable(idev->i2c_clk);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret,
|
||||
"failed to enable clock\n");
|
||||
|
||||
ret = mchp_corei2c_init(idev);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(idev->i2c_clk);
|
||||
return dev_err_probe(&pdev->dev, ret, "failed to program clock divider\n");
|
||||
}
|
||||
|
||||
i2c_set_adapdata(&idev->adapter, idev);
|
||||
snprintf(idev->adapter.name, sizeof(idev->adapter.name),
|
||||
"Microchip I2C hw bus at %08lx", (unsigned long)res->start);
|
||||
idev->adapter.owner = THIS_MODULE;
|
||||
idev->adapter.algo = &mchp_corei2c_algo;
|
||||
idev->adapter.dev.parent = &pdev->dev;
|
||||
idev->adapter.dev.of_node = pdev->dev.of_node;
|
||||
idev->adapter.timeout = HZ;
|
||||
|
||||
platform_set_drvdata(pdev, idev);
|
||||
|
||||
ret = i2c_add_adapter(&idev->adapter);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(idev->i2c_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "registered CoreI2C bus driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mchp_corei2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mchp_corei2c_dev *idev = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(idev->i2c_clk);
|
||||
i2c_del_adapter(&idev->adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mchp_corei2c_of_match[] = {
|
||||
{ .compatible = "microchip,mpfs-i2c" },
|
||||
{ .compatible = "microchip,corei2c-rtl-v7" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mchp_corei2c_of_match);
|
||||
|
||||
static struct platform_driver mchp_corei2c_driver = {
|
||||
.probe = mchp_corei2c_probe,
|
||||
.remove = mchp_corei2c_remove,
|
||||
.driver = {
|
||||
.name = "microchip-corei2c",
|
||||
.of_match_table = mchp_corei2c_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(mchp_corei2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip CoreI2C bus driver");
|
||||
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue