MIPS: Pistachio: Remove plat_setup_iocoherency
The Pistachio SoC does not have an IOCU. Hence, DMA is non-coherent. Remove the function checking for iocoherency and select CONFIG_DMA_NONCOHERENT in Kconfig This code is probably accidentally inherited from Malta. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: James Hartley <james.hartley@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13433/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -384,7 +384,7 @@ config MACH_PISTACHIO
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select CLKSRC_MIPS_GIC
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select COMMON_CLK
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select CSRC_R4K
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select DMA_MAYBE_COHERENT
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select DMA_NONCOHERENT
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select GPIOLIB
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select IRQ_MIPS_CPU
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select LIBFDT
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@ -60,29 +60,6 @@ const char *get_system_type(void)
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return sys_type;
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}
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static void __init plat_setup_iocoherency(void)
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{
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/*
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* Kernel has been configured with software coherency
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* but we might choose to turn it off and use hardware
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* coherency instead.
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*/
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if (mips_cm_numiocu() != 0) {
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/* Nothing special needs to be done to enable coherency */
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pr_info("CMP IOCU detected\n");
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hw_coherentio = 1;
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if (coherentio == 0)
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pr_info("Hardware DMA cache coherency disabled\n");
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else
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pr_info("Hardware DMA cache coherency enabled\n");
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} else {
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if (coherentio == 1)
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pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
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else
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pr_info("Software DMA cache coherency enabled\n");
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}
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}
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void __init *plat_get_fdt(void)
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{
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if (fw_arg0 != -2)
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@ -93,8 +70,6 @@ void __init *plat_get_fdt(void)
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void __init plat_mem_setup(void)
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{
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__dt_setup_arch(plat_get_fdt());
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plat_setup_iocoherency();
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}
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#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
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