phy: Add drivers for PCIe and SATA phy on SPEAr13xx
ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys. This also adds proper bindings for miphys. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Tested-by: Mohit Kumar <mohit.kumar@st.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Pratyush Anand
Viresh Kumar
parent
51b66a6ce1
commit
64562e9947
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@ -0,0 +1,15 @@
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ST SPEAr miphy DT details
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=========================
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ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
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Required properties:
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- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
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- reg : offset and length of the PHY register set.
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- misc: phandle for the syscon node to access misc registers
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- #phy-cells : from the generic PHY bindings, must be 1.
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- cell[1]: 0 if phy used for SATA, 1 for PCIe.
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Optional properties:
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- phy-id: Instance id of the phy. Only required when there are multiple phys
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present on a implementation.
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@ -178,4 +178,16 @@ config PHY_XGENE
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help
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This option enables support for APM X-Gene SoC multi-purpose PHY.
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config PHY_ST_SPEAR1310_MIPHY
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tristate "ST SPEAR1310-MIPHY driver"
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select GENERIC_PHY
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help
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Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA.
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config PHY_ST_SPEAR1340_MIPHY
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tristate "ST SPEAR1340-MIPHY driver"
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select GENERIC_PHY
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help
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Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA.
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endmenu
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@ -20,3 +20,5 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
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phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
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obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
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obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
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obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
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obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
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@ -0,0 +1,274 @@
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/*
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* ST SPEAr1310-miphy driver
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*
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* Copyright (C) 2014 ST Microelectronics
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* Pratyush Anand <pratyush.anand@st.com>
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* Mohit Kumar <mohit.kumar@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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/* SPEAr1310 Registers */
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#define SPEAR1310_PCIE_SATA_CFG 0x3A4
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#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
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#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
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#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
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#define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31)
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#define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30)
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#define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29)
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#define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27)
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#define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26)
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#define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25)
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#define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24)
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#define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23)
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#define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22)
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#define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21)
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#define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20)
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#define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19)
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#define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18)
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#define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17)
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#define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16)
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#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11)
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#define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10)
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#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9)
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#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8)
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#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7)
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#define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6)
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#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5)
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#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4)
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#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3)
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#define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2)
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#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1)
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#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0)
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#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | BIT((x + 29)))
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#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
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BIT((x + 29)))
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#define SPEAR1310_PCIE_CFG_VAL(x) \
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(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
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SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
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SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
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SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
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SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
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#define SPEAR1310_SATA_CFG_VAL(x) \
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(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
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SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
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SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
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SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
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SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
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#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
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#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31)
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#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28)
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#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
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#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15)
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#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12)
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#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
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(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
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SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
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SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
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SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
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(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
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#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
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(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
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SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
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SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
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#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
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enum spear1310_miphy_mode {
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SATA,
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PCIE,
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};
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struct spear1310_miphy_priv {
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/* instance id of this phy */
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u32 id;
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/* phy mode: 0 for SATA 1 for PCIe */
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enum spear1310_miphy_mode mode;
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/* regmap for any soc specific misc registers */
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struct regmap *misc;
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/* phy struct pointer */
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struct phy *phy;
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};
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static int spear1310_miphy_pcie_init(struct spear1310_miphy_priv *priv)
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{
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u32 val;
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
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switch (priv->id) {
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case 0:
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val = SPEAR1310_PCIE_CFG_VAL(0);
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break;
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case 1:
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val = SPEAR1310_PCIE_CFG_VAL(1);
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break;
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case 2:
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val = SPEAR1310_PCIE_CFG_VAL(2);
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
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SPEAR1310_PCIE_CFG_MASK(priv->id), val);
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return 0;
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}
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static int spear1310_miphy_pcie_exit(struct spear1310_miphy_priv *priv)
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{
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_SATA_CFG,
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SPEAR1310_PCIE_CFG_MASK(priv->id), 0);
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regmap_update_bits(priv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
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SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
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return 0;
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}
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static int spear1310_miphy_init(struct phy *phy)
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{
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struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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if (priv->mode == PCIE)
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ret = spear1310_miphy_pcie_init(priv);
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return ret;
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}
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static int spear1310_miphy_exit(struct phy *phy)
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{
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struct spear1310_miphy_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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if (priv->mode == PCIE)
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ret = spear1310_miphy_pcie_exit(priv);
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return ret;
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}
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static const struct of_device_id spear1310_miphy_of_match[] = {
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{ .compatible = "st,spear1310-miphy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, spear1310_miphy_of_match);
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static struct phy_ops spear1310_miphy_ops = {
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.init = spear1310_miphy_init,
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.exit = spear1310_miphy_exit,
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.owner = THIS_MODULE,
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};
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static struct phy *spear1310_miphy_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct spear1310_miphy_priv *priv = dev_get_drvdata(dev);
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if (args->args_count < 1) {
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dev_err(dev, "DT did not pass correct no of args\n");
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return NULL;
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}
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priv->mode = args->args[0];
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if (priv->mode != SATA && priv->mode != PCIE) {
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dev_err(dev, "DT did not pass correct phy mode\n");
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return NULL;
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}
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return priv->phy;
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}
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static int spear1310_miphy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spear1310_miphy_priv *priv;
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struct phy_provider *phy_provider;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(dev, "can't alloc spear1310_miphy private date memory\n");
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return -ENOMEM;
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}
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priv->misc =
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syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
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if (IS_ERR(priv->misc)) {
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dev_err(dev, "failed to find misc regmap\n");
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return PTR_ERR(priv->misc);
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}
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if (of_property_read_u32(dev->of_node, "phy-id", &priv->id)) {
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dev_err(dev, "failed to find phy id\n");
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return -EINVAL;
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}
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priv->phy = devm_phy_create(dev, &spear1310_miphy_ops, NULL);
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if (IS_ERR(priv->phy)) {
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dev_err(dev, "failed to create SATA PCIe PHY\n");
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return PTR_ERR(priv->phy);
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}
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dev_set_drvdata(dev, priv);
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phy_set_drvdata(priv->phy, priv);
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phy_provider =
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devm_of_phy_provider_register(dev, spear1310_miphy_xlate);
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if (IS_ERR(phy_provider)) {
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dev_err(dev, "failed to register phy provider\n");
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return PTR_ERR(phy_provider);
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}
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return 0;
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}
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static struct platform_driver spear1310_miphy_driver = {
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.probe = spear1310_miphy_probe,
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.driver = {
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.name = "spear1310-miphy",
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(spear1310_miphy_of_match),
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},
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};
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static int __init spear1310_miphy_phy_init(void)
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{
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return platform_driver_register(&spear1310_miphy_driver);
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}
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module_init(spear1310_miphy_phy_init);
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static void __exit spear1310_miphy_phy_exit(void)
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{
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platform_driver_unregister(&spear1310_miphy_driver);
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}
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module_exit(spear1310_miphy_phy_exit);
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MODULE_DESCRIPTION("ST SPEAR1310-MIPHY driver");
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MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,307 @@
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/*
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* ST spear1340-miphy driver
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*
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* Copyright (C) 2014 ST Microelectronics
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* Pratyush Anand <pratyush.anand@st.com>
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* Mohit Kumar <mohit.kumar@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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/* SPEAr1340 Registers */
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/* Power Management Registers */
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#define SPEAR1340_PCM_CFG 0x100
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#define SPEAR1340_PCM_CFG_SATA_POWER_EN BIT(11)
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#define SPEAR1340_PCM_WKUP_CFG 0x104
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#define SPEAR1340_SWITCH_CTR 0x108
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#define SPEAR1340_PERIP1_SW_RST 0x318
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#define SPEAR1340_PERIP1_SW_RSATA BIT(12)
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#define SPEAR1340_PERIP2_SW_RST 0x31C
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#define SPEAR1340_PERIP3_SW_RST 0x320
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/* PCIE - SATA configuration registers */
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#define SPEAR1340_PCIE_SATA_CFG 0x424
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/* PCIE CFG MASks */
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#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT BIT(11)
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#define SPEAR1340_PCIE_CFG_POWERUP_RESET BIT(10)
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#define SPEAR1340_PCIE_CFG_CORE_CLK_EN BIT(9)
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#define SPEAR1340_PCIE_CFG_AUX_CLK_EN BIT(8)
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#define SPEAR1340_SATA_CFG_TX_CLK_EN BIT(4)
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#define SPEAR1340_SATA_CFG_RX_CLK_EN BIT(3)
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#define SPEAR1340_SATA_CFG_POWERUP_RESET BIT(2)
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#define SPEAR1340_SATA_CFG_PM_CLK_EN BIT(1)
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#define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
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#define SPEAR1340_PCIE_SATA_SEL_SATA (1)
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#define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
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#define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
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SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
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SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
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SPEAR1340_PCIE_CFG_POWERUP_RESET | \
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SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
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#define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
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SPEAR1340_SATA_CFG_PM_CLK_EN | \
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SPEAR1340_SATA_CFG_POWERUP_RESET | \
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SPEAR1340_SATA_CFG_RX_CLK_EN | \
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SPEAR1340_SATA_CFG_TX_CLK_EN)
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#define SPEAR1340_PCIE_MIPHY_CFG 0x428
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#define SPEAR1340_MIPHY_OSC_BYPASS_EXT BIT(31)
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#define SPEAR1340_MIPHY_CLK_REF_DIV2 BIT(27)
|
||||
#define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
|
||||
#define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
|
||||
#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
|
||||
#define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
|
||||
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
|
||||
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
|
||||
SPEAR1340_MIPHY_CLK_REF_DIV2 | \
|
||||
SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
|
||||
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
|
||||
(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
|
||||
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
|
||||
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
|
||||
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
|
||||
|
||||
enum spear1340_miphy_mode {
|
||||
SATA,
|
||||
PCIE,
|
||||
};
|
||||
|
||||
struct spear1340_miphy_priv {
|
||||
/* phy mode: 0 for SATA 1 for PCIe */
|
||||
enum spear1340_miphy_mode mode;
|
||||
/* regmap for any soc specific misc registers */
|
||||
struct regmap *misc;
|
||||
/* phy struct pointer */
|
||||
struct phy *phy;
|
||||
};
|
||||
|
||||
static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
|
||||
{
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
|
||||
SPEAR1340_PCIE_SATA_CFG_MASK,
|
||||
SPEAR1340_SATA_CFG_VAL);
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
|
||||
SPEAR1340_PCIE_MIPHY_CFG_MASK,
|
||||
SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
|
||||
/* Switch on sata power domain */
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
|
||||
SPEAR1340_PCM_CFG_SATA_POWER_EN,
|
||||
SPEAR1340_PCM_CFG_SATA_POWER_EN);
|
||||
/* Wait for SATA power domain on */
|
||||
msleep(20);
|
||||
|
||||
/* Disable PCIE SATA Controller reset */
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
|
||||
SPEAR1340_PERIP1_SW_RSATA, 0);
|
||||
/* Wait for SATA reset de-assert completion */
|
||||
msleep(20);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
|
||||
{
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
|
||||
SPEAR1340_PCIE_SATA_CFG_MASK, 0);
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
|
||||
SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
|
||||
|
||||
/* Enable PCIE SATA Controller reset */
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
|
||||
SPEAR1340_PERIP1_SW_RSATA,
|
||||
SPEAR1340_PERIP1_SW_RSATA);
|
||||
/* Wait for SATA power domain off */
|
||||
msleep(20);
|
||||
/* Switch off sata power domain */
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
|
||||
SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
|
||||
/* Wait for SATA reset assert completion */
|
||||
msleep(20);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
|
||||
{
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
|
||||
SPEAR1340_PCIE_MIPHY_CFG_MASK,
|
||||
SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
|
||||
SPEAR1340_PCIE_SATA_CFG_MASK,
|
||||
SPEAR1340_PCIE_CFG_VAL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
|
||||
{
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
|
||||
SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
|
||||
regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
|
||||
SPEAR1340_PCIE_SATA_CFG_MASK, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_init(struct phy *phy)
|
||||
{
|
||||
struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
|
||||
int ret = 0;
|
||||
|
||||
if (priv->mode == SATA)
|
||||
ret = spear1340_miphy_sata_init(priv);
|
||||
else if (priv->mode == PCIE)
|
||||
ret = spear1340_miphy_pcie_init(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_exit(struct phy *phy)
|
||||
{
|
||||
struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
|
||||
int ret = 0;
|
||||
|
||||
if (priv->mode == SATA)
|
||||
ret = spear1340_miphy_sata_exit(priv);
|
||||
else if (priv->mode == PCIE)
|
||||
ret = spear1340_miphy_pcie_exit(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id spear1340_miphy_of_match[] = {
|
||||
{ .compatible = "st,spear1340-miphy" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
|
||||
|
||||
static struct phy_ops spear1340_miphy_ops = {
|
||||
.init = spear1340_miphy_init,
|
||||
.exit = spear1340_miphy_exit,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int spear1340_miphy_suspend(struct device *dev)
|
||||
{
|
||||
struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
if (priv->mode == SATA)
|
||||
ret = spear1340_miphy_sata_exit(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_resume(struct device *dev)
|
||||
{
|
||||
struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
if (priv->mode == SATA)
|
||||
ret = spear1340_miphy_sata_init(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(spear1340_miphy_pm_ops, spear1340_miphy_suspend,
|
||||
spear1340_miphy_resume);
|
||||
|
||||
static struct phy *spear1340_miphy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
if (args->args_count < 1) {
|
||||
dev_err(dev, "DT did not pass correct no of args\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
priv->mode = args->args[0];
|
||||
|
||||
if (priv->mode != SATA && priv->mode != PCIE) {
|
||||
dev_err(dev, "DT did not pass correct phy mode\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return priv->phy;
|
||||
}
|
||||
|
||||
static int spear1340_miphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spear1340_miphy_priv *priv;
|
||||
struct phy_provider *phy_provider;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
dev_err(dev, "can't alloc spear1340_miphy private date memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv->misc =
|
||||
syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
|
||||
if (IS_ERR(priv->misc)) {
|
||||
dev_err(dev, "failed to find misc regmap\n");
|
||||
return PTR_ERR(priv->misc);
|
||||
}
|
||||
|
||||
priv->phy = devm_phy_create(dev, &spear1340_miphy_ops, NULL);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create SATA PCIe PHY\n");
|
||||
return PTR_ERR(priv->phy);
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, priv);
|
||||
phy_set_drvdata(priv->phy, priv);
|
||||
|
||||
phy_provider =
|
||||
devm_of_phy_provider_register(dev, spear1340_miphy_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
dev_err(dev, "failed to register phy provider\n");
|
||||
return PTR_ERR(phy_provider);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver spear1340_miphy_driver = {
|
||||
.probe = spear1340_miphy_probe,
|
||||
.driver = {
|
||||
.name = "spear1340-miphy",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &spear1340_miphy_pm_ops,
|
||||
.of_match_table = of_match_ptr(spear1340_miphy_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
static int __init spear1340_miphy_phy_init(void)
|
||||
{
|
||||
return platform_driver_register(&spear1340_miphy_driver);
|
||||
}
|
||||
module_init(spear1340_miphy_phy_init);
|
||||
|
||||
static void __exit spear1340_miphy_phy_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&spear1340_miphy_driver);
|
||||
}
|
||||
module_exit(spear1340_miphy_phy_exit);
|
||||
|
||||
MODULE_DESCRIPTION("ST SPEAR1340-MIPHY driver");
|
||||
MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue