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Renesas ARM Based SoC Cleanup for v4.3 

* Remove non-multiplatform code from timer
 * Remove CONFIG_ARCH_SHMOBILE_MULTI check in setup-rcar-gen2.c
   as it is always true
 * Remove legacy (non-multiplatform) support for both sh73a0/kzm9g and
   r8a7740/armadillo800eva
 * Move to_rmobile_pd from header to source file where it is used
 * Use BIT() macro instead of open coding in r-mobile PM code
 * r8a7779: Remove usage of GENPD_FLAG_PM_CLK flag which has no effect
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Merge tag 'renesas-cleanup-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup

Merge "Renesas ARM Based SoC Cleanup for v4.3" from Simon Horman:

* Remove non-multiplatform code from timer
* Remove CONFIG_ARCH_SHMOBILE_MULTI check in setup-rcar-gen2.c
  as it is always true
* Remove legacy (non-multiplatform) support for both sh73a0/kzm9g and
  r8a7740/armadillo800eva
* Move to_rmobile_pd from header to source file where it is used
* Use BIT() macro instead of open coding in r-mobile PM code
* r8a7779: Remove usage of GENPD_FLAG_PM_CLK flag which has no effect

* tag 'renesas-cleanup-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: timer: r8a73a4 and r8a7790 are multi-platform only
  ARM: shmobile: R-Car Gen2: CONFIG_ARCH_SHMOBILE_MULTI is always set
  ARM: shmobile: Remove obsolete zboot support
  ARM: shmobile: R-Mobile: Remove legacy PM Domain code
  ARM: shmobile: Remove unused dma-register.h
  ARM: shmobile: Remove legacy SoC code for R-Mobile A1
  ARM: shmobile: Drop r8a7740-armadillo800eva.dtb for legacy builds
  ARM: shmobile: Remove legacy armadillo800eva_defconfig
  ARM: shmobile: Remove legacy board code for Armadillo-800 EVA
  ARM: shmobile: Remove legacy SoC code for SH-Mobile AG5
  ARM: shmobile: Drop sh73a0-kzm9g.dtb for legacy builds
  ARM: shmobile: Remove legacy kzm9g_defconfig
  ARM: shmobile: Remove legacy board code for KZM-A9-GT
  ARM: shmobile: r8a7779: Remove GENPD_FLAG_PM_CLK flag
  ARM: shmobile: R-Mobile: Use BIT() macro instead of open coding
  ARM: shmobile: R-Mobile: Move to_rmobile_pd from header to source file

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-07-14 11:48:31 +02:00
parent bc0195aad0 20834a406e
commit 63f346937b
30 changed files with 15 additions and 6912 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -1464,9 +1464,7 @@ F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/armadillo800eva_defconfig
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/kzm9g_defconfig
F: arch/arm/configs/marzen_defconfig
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S

4
arch/arm/boot/compressed/Makefile
View File

@ -51,10 +51,6 @@ else
endif
endif
ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
OBJS += head-shmobile.o
endif
#
# We now have a PIC decompressor implementation. Decompressors running
# from RAM should not define ZTEXTADDR. Decompressors running directly

71
arch/arm/boot/compressed/head-shmobile.S
View File

@ -1,71 +0,0 @@
/*
* The head-file for SH-Mobile ARM platforms
*
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
* Simon Horman <horms@verge.net.au>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifdef CONFIG_ZBOOT_ROM
.section ".start", "ax"
/* load board-specific initialization code */
#include <mach/zboot.h>
adr r0, dtb_info
ldmia r0, {r1, r3, r4, r5, r7}
sub r0, r0, r1 @ calculate the delta offset
add r5, r5, r0 @ _edata
ldr lr, [r5, #0] @ check if valid DTB is present
cmp lr, r3
bne 0f
add r9, r7, #31 @ rounded up to a multiple
bic r9, r9, #31 @ ... of 32 bytes
add r6, r9, r5 @ copy from _edata
add r9, r9, r4 @ to MEMORY_START
1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
cmp r6, r5
stmdb r9!, {r0 - r3, r10 - r12, lr}
bhi 1b
/* Success: Zero board ID, pointer to start of memory for atag/dtb */
mov r7, #0
mov r8, r4
b 2f
.align 2
dtb_info:
.word dtb_info
#ifndef __ARMEB__
.word 0xedfe0dd0 @ sig is 0xd00dfeed big endian
#else
.word 0xd00dfeed
#endif
.word MEMORY_START
.word _edata
.word 0x4000 @ maximum DTB size
0:
/* Failure: Zero board ID, NULL atag/dtb */
mov r7, #0
mov r8, #0 @ pass null pointer as atag
2 :
#endif /* CONFIG_ZBOOT_ROM */

4
arch/arm/boot/dts/Makefile
View File

@ -501,11 +501,9 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb \
r8a7779-marzen.dtb \
sh73a0-kzm9g.dtb
r8a7779-marzen.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \

162
arch/arm/configs/armadillo800eva_defconfig
View File

@ -1,162 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7740=y
CONFIG_MACH_ARMADILLO800EVA=y
# CONFIG_SH_TIMER_TMU is not set
CONFIG_ARM_THUMB=y
CONFIG_CACHE_L2X0=y
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_458693=y
CONFIG_ARM_ERRATA_460075=y
CONFIG_PL310_ERRATA_588369=y
CONFIG_ARM_ERRATA_720789=y
CONFIG_PL310_ERRATA_727915=y
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_751472=y
CONFIG_PL310_ERRATA_753970=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_PL310_ERRATA_769419=y
CONFIG_ARM_ERRATA_775420=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_FORCE_MAX_ZONEORDER=13
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
CONFIG_SH_ETH=y
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ST1232=y
# CONFIG_SERIO is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
CONFIG_REGULATOR=y
CONFIG_REGULATOR_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_VIDEO_DEV=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_SOC_CAMERA_MT9T112=y
CONFIG_VIDEO_SH_MOBILE_CEU=y
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_FB_SH_MOBILE_HDMI=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_PWM=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SOC_SH4_FSI=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_S35390A=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_PWM=y
CONFIG_PWM_RENESAS_TPU=y
# CONFIG_DNOTIFY is not set
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_ANSI_CPRNG=y
CONFIG_XZ_DEC=y

154
arch/arm/configs/kzm9g_defconfig
View File

@ -1,154 +0,0 @@
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_SH73A0=y
CONFIG_MACH_KZM9G=y
CONFIG_MEMORY_START=0x41000000
CONFIG_MEMORY_SIZE=0x1f000000
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_KEXEC=y
CONFIG_VFP=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_IRDA=y
CONFIG_SH_IRDA=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
# CONFIG_WLAN is not set
CONFIG_INPUT_SPARSEKMAP=y
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ST1232=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_ADXL34X=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_SH_MOBILE=y
CONFIG_GPIO_PCF857X=y
# CONFIG_HWMON is not set
CONFIG_MFD_AS3711=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_AS3711=y
CONFIG_FB=y
CONFIG_FB_SH_MOBILE_LCDC=y
CONFIG_BACKLIGHT_AS3711=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_FB_SH_MOBILE_MERAM=y
CONFIG_SOUND=y
CONFIG_SND=y
# CONFIG_SND_SUPPORT_OLD_API is not set
# CONFIG_SND_VERBOSE_PROCFS is not set
# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_ARM is not set
# CONFIG_SND_USB is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_SH4_FSI=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS_UDC=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_RS5C372=y
CONFIG_DMADEVICES=y
CONFIG_SH_DMAE=y
CONFIG_ASYNC_TX_DMA=y
CONFIG_STAGING=y
CONFIG_IIO=y
CONFIG_AK8975=y
# CONFIG_DNOTIFY is not set
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
CONFIG_CRC16=y

33
arch/arm/mach-shmobile/Kconfig
View File

@ -103,22 +103,6 @@ if ARCH_SHMOBILE_LEGACY
comment "Renesas ARM SoCs System Type"
config ARCH_SH73A0
bool "SH-Mobile AG5 (R8A73A00)"
select ARCH_RMOBILE
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select I2C
select SH_INTC
select RENESAS_INTC_IRQPIN
config ARCH_R8A7740
bool "R-Mobile A1 (R8A77400)"
select ARCH_RMOBILE
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select RENESAS_INTC_IRQPIN
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
@ -133,15 +117,6 @@ config ARCH_R8A7779
comment "Renesas ARM SoCs Board Type"
config MACH_ARMADILLO800EVA
bool "Armadillo-800 EVA board"
depends on ARCH_R8A7740
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SMSC_PHY if SH_ETH
select SND_SOC_WM8978 if SND_SIMPLE_CARD && I2C
select USE_OF
config MACH_BOCKW
bool "BOCK-W platform"
depends on ARCH_R8A7778
@ -171,14 +146,6 @@ config MACH_MARZEN
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
config MACH_KZM9G
bool "KZM-A9-GT board"
depends on ARCH_SH73A0
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SND_SOC_AK4642 if SND_SIMPLE_CARD
select USE_OF
comment "Renesas ARM SoCs System Configuration"
config CPU_HAS_INTEVT

8
arch/arm/mach-shmobile/Makefile
View File

@ -6,9 +6,9 @@
obj-y := timer.o console.o
# CPU objects
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o
obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o pm-r8a7779.o
obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
@ -20,8 +20,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
# Clock objects
ifndef CONFIG_COMMON_CLK
obj-y += clock.o
obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
endif
@ -57,8 +55,6 @@ else
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o
endif
# Framework support

2
arch/arm/mach-shmobile/Makefile.boot
View File

@ -1,9 +1,7 @@
# per-board load address for uImage
loadaddr-y :=
loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
__ZRELADDR := $(sort $(loadaddr-y))

1365
arch/arm/mach-shmobile/board-armadillo800eva.c
View File

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arch/arm/mach-shmobile/board-kzm9g.c
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/*
* KZM-A9-GT board support
*
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/i2c/pcf857x.h>
#include <linux/input.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/as3711.h>
#include <linux/mfd/tmio.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/renesas_usbhs.h>
#include <linux/videodev2.h>
#include <sound/sh_fsi.h>
#include <sound/simple_card.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <video/sh_mobile_lcdc.h>
#include "common.h"
#include "intc.h"
#include "irqs.h"
#include "sh73a0.h"
/*
* external GPIO
*/
#define GPIO_PCF8575_BASE (310)
#define GPIO_PCF8575_PORT10 (GPIO_PCF8575_BASE + 8)
#define GPIO_PCF8575_PORT11 (GPIO_PCF8575_BASE + 9)
#define GPIO_PCF8575_PORT12 (GPIO_PCF8575_BASE + 10)
#define GPIO_PCF8575_PORT13 (GPIO_PCF8575_BASE + 11)
#define GPIO_PCF8575_PORT14 (GPIO_PCF8575_BASE + 12)
#define GPIO_PCF8575_PORT15 (GPIO_PCF8575_BASE + 13)
#define GPIO_PCF8575_PORT16 (GPIO_PCF8575_BASE + 14)
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};
/*
* FSI-AK4648
*
* this command is required when playback.
*
* # amixer set "LINEOUT Mixer DACL" on
*/
/* SMSC 9221 */
static struct resource smsc9221_resources[] = {
[0] = {
.start = 0x10000000, /* CS4 */
.end = 0x100000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = irq_pin(3), /* IRQ3 */
.flags = IORESOURCE_IRQ,
},
};
static struct smsc911x_platform_config smsc9221_platdata = {
.flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
};
static struct platform_device smsc_device = {
.name = "smsc911x",
.dev = {
.platform_data = &smsc9221_platdata,
},
.resource = smsc9221_resources,
.num_resources = ARRAY_SIZE(smsc9221_resources),
};
/* USB external chip */
static struct r8a66597_platdata usb_host_data = {
.on_chip = 0,
.xtal = R8A66597_PLATDATA_XTAL_48MHZ,
};
static struct resource usb_resources[] = {
[0] = {
.start = 0x10010000,
.end = 0x1001ffff - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = irq_pin(1), /* IRQ1 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usb_host_device = {
.name = "r8a66597_hcd",
.dev = {
.platform_data = &usb_host_data,
.dma_mask = NULL,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(usb_resources),
.resource = usb_resources,
};
/* USB Func CN17 */
struct usbhs_private {
void __iomem *phy;
void __iomem *cr2;
struct renesas_usbhs_platform_info info;
};
#define IRQ15 irq_pin(15)
#define USB_PHY_MODE (1 << 4)
#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
#define USB_PHY_ON (1 << 1)
#define USB_PHY_OFF (1 << 0)
#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF)
#define usbhs_get_priv(pdev) \
container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
static int usbhs_get_vbus(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
return !((1 << 7) & __raw_readw(priv->cr2));
}
static int usbhs_phy_reset(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
/* init phy */
__raw_writew(0x8a0a, priv->cr2);
return 0;
}
static int usbhs_get_id(struct platform_device *pdev)
{
return USBHS_GADGET;
}
static irqreturn_t usbhs_interrupt(int irq, void *data)
{
struct platform_device *pdev = data;
struct usbhs_private *priv = usbhs_get_priv(pdev);
renesas_usbhs_call_notify_hotplug(pdev);
/* clear status */
__raw_writew(__raw_readw(priv->phy) | USB_PHY_INT_CLR, priv->phy);
return IRQ_HANDLED;
}
static int usbhs_hardware_init(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
int ret;
/* clear interrupt status */
__raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
ret = request_irq(IRQ15, usbhs_interrupt, IRQF_TRIGGER_HIGH,
dev_name(&pdev->dev), pdev);
if (ret) {
dev_err(&pdev->dev, "request_irq err\n");
return ret;
}
/* enable USB phy interrupt */
__raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->phy);
return 0;
}
static int usbhs_hardware_exit(struct platform_device *pdev)
{
struct usbhs_private *priv = usbhs_get_priv(pdev);
/* clear interrupt status */
__raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
free_irq(IRQ15, pdev);
return 0;
}
static u32 usbhs_pipe_cfg[] = {
USB_ENDPOINT_XFER_CONTROL,
USB_ENDPOINT_XFER_ISOC,
USB_ENDPOINT_XFER_ISOC,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_INT,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
USB_ENDPOINT_XFER_BULK,
};
static struct usbhs_private usbhs_private = {
.phy = IOMEM(0xe60781e0), /* USBPHYINT */
.cr2 = IOMEM(0xe605810c), /* USBCR2 */
.info = {
.platform_callback = {
.hardware_init = usbhs_hardware_init,
.hardware_exit = usbhs_hardware_exit,
.get_id = usbhs_get_id,
.phy_reset = usbhs_phy_reset,
.get_vbus = usbhs_get_vbus,
},
.driver_param = {
.buswait_bwait = 4,
.has_otg = 1,
.pipe_type = usbhs_pipe_cfg,
.pipe_size = ARRAY_SIZE(usbhs_pipe_cfg),
},
},
};
static struct resource usbhs_resources[] = {
[0] = {
.start = 0xE6890000,
.end = 0xE68900e6 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(62),
.end = gic_spi(62),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usbhs_device = {
.name = "renesas_usbhs",
.id = -1,
.dev = {
.dma_mask = NULL,
.coherent_dma_mask = 0xffffffff,
.platform_data = &usbhs_private.info,
},
.num_resources = ARRAY_SIZE(usbhs_resources),
.resource = usbhs_resources,
};
/* LCDC */
static struct fb_videomode kzm_lcdc_mode = {
.name = "WVGA Panel",
.xres = 800,
.yres = 480,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 70,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.sync = 0,
};
static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.lcd_modes = &kzm_lcdc_mode,
.num_modes = 1,
.clock_divider = 5,
.flags = 0,
.panel_cfg = {
.width = 152,
.height = 91,
},
}
};
static struct resource lcdc_resources[] = {
[0] = {
.name = "LCDC",
.start = 0xfe940000,
.end = 0xfe943fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = intcs_evt2irq(0x580),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lcdc_device = {
.name = "sh_mobile_lcdc_fb",
.num_resources = ARRAY_SIZE(lcdc_resources),
.resource = lcdc_resources,
.dev = {
.platform_data = &lcdc_info,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* Fixed 1.8V regulator to be used by MMCIF */
static struct regulator_consumer_supply fixed1v8_power_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
};
/* MMCIF */
static struct resource sh_mmcif_resources[] = {
[0] = {
.name = "MMCIF",
.start = 0xe6bd0000,
.end = 0xe6bd00ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(140),
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = gic_spi(141),
.flags = IORESOURCE_IRQ,
},
};
static struct sh_mmcif_plat_data sh_mmcif_platdata = {
.ocr = MMC_VDD_165_195,
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
.ccs_unsupported = true,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
static struct platform_device mmc_device = {
.name = "sh_mmcif",
.dev = {
.dma_mask = NULL,
.coherent_dma_mask = 0xffffffff,
.platform_data = &sh_mmcif_platdata,
},
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
.resource = sh_mmcif_resources,
};
/* Fixed 3.3V regulators to be used by SDHI0 */
static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
};
static struct regulator_init_data vcc_sdhi0_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
.consumer_supplies = vcc_sdhi0_consumers,
};
static struct fixed_voltage_config vcc_sdhi0_info = {
.supply_name = "SDHI0 Vcc",
.microvolts = 3300000,
.gpio = 15,
.enable_high = 1,
.init_data = &vcc_sdhi0_init_data,
};
static struct platform_device vcc_sdhi0 = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &vcc_sdhi0_info,
},
};
/* Fixed 3.3V regulators to be used by SDHI2 */
static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
};
static struct regulator_init_data vcc_sdhi2_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers),
.consumer_supplies = vcc_sdhi2_consumers,
};
static struct fixed_voltage_config vcc_sdhi2_info = {
.supply_name = "SDHI2 Vcc",
.microvolts = 3300000,
.gpio = 14,
.enable_high = 1,
.init_data = &vcc_sdhi2_init_data,
};
static struct platform_device vcc_sdhi2 = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &vcc_sdhi2_info,
},
};
/* SDHI */
static struct tmio_mmc_data sdhi0_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
.flags = TMIO_MMC_HAS_IDLE_WAIT,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
};
static struct resource sdhi0_resources[] = {
[0] = {
.name = "SDHI0",
.start = 0xee100000,
.end = 0xee1000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
.start = gic_spi(83),
.flags = IORESOURCE_IRQ,
},
[2] = {
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
.start = gic_spi(84),
.flags = IORESOURCE_IRQ,
},
[3] = {
.name = SH_MOBILE_SDHI_IRQ_SDIO,
.start = gic_spi(85),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi0_device = {
.name = "sh_mobile_sdhi",
.num_resources = ARRAY_SIZE(sdhi0_resources),
.resource = sdhi0_resources,
.dev = {
.platform_data = &sdhi0_info,
},
};
/* Micro SD */
static struct tmio_mmc_data sdhi2_info = {
.chan_priv_tx = (void *)SHDMA_SLAVE_SDHI2_TX,
.chan_priv_rx = (void *)SHDMA_SLAVE_SDHI2_RX,
.flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_USE_GPIO_CD |
TMIO_MMC_WRPROTECT_DISABLE,
.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
.cd_gpio = 13,
};
static struct resource sdhi2_resources[] = {
[0] = {
.name = "SDHI2",
.start = 0xee140000,
.end = 0xee1400ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
.start = gic_spi(103),
.flags = IORESOURCE_IRQ,
},
[2] = {
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
.start = gic_spi(104),
.flags = IORESOURCE_IRQ,
},
[3] = {
.name = SH_MOBILE_SDHI_IRQ_SDIO,
.start = gic_spi(105),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sdhi2_device = {
.name = "sh_mobile_sdhi",
.id = 2,
.num_resources = ARRAY_SIZE(sdhi2_resources),
.resource = sdhi2_resources,
.dev = {
.platform_data = &sdhi2_info,
},
};
/* KEY */
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
static struct gpio_keys_button gpio_buttons[] = {
GPIO_KEY(KEY_BACK, GPIO_PCF8575_PORT10, "SW3"),
GPIO_KEY(KEY_RIGHT, GPIO_PCF8575_PORT11, "SW2-R"),
GPIO_KEY(KEY_LEFT, GPIO_PCF8575_PORT12, "SW2-L"),
GPIO_KEY(KEY_ENTER, GPIO_PCF8575_PORT13, "SW2-P"),
GPIO_KEY(KEY_UP, GPIO_PCF8575_PORT14, "SW2-U"),
GPIO_KEY(KEY_DOWN, GPIO_PCF8575_PORT15, "SW2-D"),
GPIO_KEY(KEY_HOME, GPIO_PCF8575_PORT16, "SW1"),
};
static struct gpio_keys_platform_data gpio_key_info = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
static struct platform_device gpio_keys_device = {
.name = "gpio-keys",
.dev = {
.platform_data = &gpio_key_info,
},
};
/* FSI-AK4648 */
static struct sh_fsi_platform_info fsi_info = {
.port_a = {
.tx_id = SHDMA_SLAVE_FSI2A_TX,
},
};
static struct resource fsi_resources[] = {
[0] = {
.name = "FSI",
.start = 0xEC230000,
.end = 0xEC230400 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(146),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device fsi_device = {
.name = "sh_fsi2",
.id = -1,
.num_resources = ARRAY_SIZE(fsi_resources),
.resource = fsi_resources,
.dev = {
.platform_data = &fsi_info,
},
};
static struct asoc_simple_card_info fsi2_ak4648_info = {
.name = "AK4648",
.card = "FSI2A-AK4648",
.codec = "ak4642-codec.0-0012",
.platform = "sh_fsi2",
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
.cpu_dai = {
.name = "fsia-dai",
},
.codec_dai = {
.name = "ak4642-hifi",
.sysclk = 11289600,
},
};
static struct platform_device fsi_ak4648_device = {
.name = "asoc-simple-card",
.dev = {
.platform_data = &fsi2_ak4648_info,
.coherent_dma_mask = DMA_BIT_MASK(32),
.dma_mask = &fsi_ak4648_device.dev.coherent_dma_mask,
},
};
/* I2C */
/* StepDown1 is used to supply 1.315V to the CPU */
static struct regulator_init_data as3711_sd1 = {
.constraints = {
.name = "1.315V CPU",
.boot_on = 1,
.always_on = 1,
.min_uV = 1315000,
.max_uV = 1335000,
},
};
/* StepDown2 is used to supply 1.8V to the CPU and to the board */
static struct regulator_init_data as3711_sd2 = {
.constraints = {
.name = "1.8V",
.boot_on = 1,
.always_on = 1,
.min_uV = 1800000,
.max_uV = 1800000,
},
};
/*
* StepDown3 is switched in parallel with StepDown2, seems to be off,
* according to read-back pre-set register values
*/
/* StepDown4 is used to supply 1.215V to the CPU and to the board */
static struct regulator_init_data as3711_sd4 = {
.constraints = {
.name = "1.215V",
.boot_on = 1,
.always_on = 1,
.min_uV = 1215000,
.max_uV = 1235000,
},
};
/* LDO1 is unused and unconnected */
/* LDO2 is used to supply 2.8V to the CPU */
static struct regulator_init_data as3711_ldo2 = {
.constraints = {
.name = "2.8V CPU",
.boot_on = 1,
.always_on = 1,
.min_uV = 2800000,
.max_uV = 2800000,
},
};
/* LDO3 is used to supply 3.0V to the CPU */
static struct regulator_init_data as3711_ldo3 = {
.constraints = {
.name = "3.0V CPU",
.boot_on = 1,
.always_on = 1,
.min_uV = 3000000,
.max_uV = 3000000,
},
};
/* LDO4 is used to supply 2.8V to the board */
static struct regulator_init_data as3711_ldo4 = {
.constraints = {
.name = "2.8V",
.boot_on = 1,
.always_on = 1,
.min_uV = 2800000,
.max_uV = 2800000,
},
};
/* LDO5 is switched parallel to LDO4, also set to 2.8V */
static struct regulator_init_data as3711_ldo5 = {
.constraints = {
.name = "2.8V #2",
.boot_on = 1,
.always_on = 1,
.min_uV = 2800000,
.max_uV = 2800000,
},
};
/* LDO6 is unused and unconnected */
/* LDO7 is used to supply 1.15V to the CPU */
static struct regulator_init_data as3711_ldo7 = {
.constraints = {
.name = "1.15V CPU",
.boot_on = 1,
.always_on = 1,
.min_uV = 1150000,
.max_uV = 1150000,
},
};
/* LDO8 is switched parallel to LDO7, also set to 1.15V */
static struct regulator_init_data as3711_ldo8 = {
.constraints = {
.name = "1.15V CPU #2",
.boot_on = 1,
.always_on = 1,
.min_uV = 1150000,
.max_uV = 1150000,
},
};
static struct as3711_platform_data as3711_pdata = {
.regulator = {
.init_data = {
[AS3711_REGULATOR_SD_1] = &as3711_sd1,
[AS3711_REGULATOR_SD_2] = &as3711_sd2,
[AS3711_REGULATOR_SD_4] = &as3711_sd4,
[AS3711_REGULATOR_LDO_2] = &as3711_ldo2,
[AS3711_REGULATOR_LDO_3] = &as3711_ldo3,
[AS3711_REGULATOR_LDO_4] = &as3711_ldo4,
[AS3711_REGULATOR_LDO_5] = &as3711_ldo5,
[AS3711_REGULATOR_LDO_7] = &as3711_ldo7,
[AS3711_REGULATOR_LDO_8] = &as3711_ldo8,
},
},
.backlight = {
.su2_fb = "sh_mobile_lcdc_fb.0",
.su2_max_uA = 36000,
.su2_feedback = AS3711_SU2_CURR_AUTO,
.su2_fbprot = AS3711_SU2_GPIO4,
.su2_auto_curr1 = true,
.su2_auto_curr2 = true,
.su2_auto_curr3 = true,
},
};
static struct pcf857x_platform_data pcf8575_pdata = {
.gpio_base = GPIO_PCF8575_BASE,
};
static struct i2c_board_info i2c0_devices[] = {
{
I2C_BOARD_INFO("ak4648", 0x12),
},
{
I2C_BOARD_INFO("r2025sd", 0x32),
},
{
I2C_BOARD_INFO("ak8975", 0x0c),
.irq = irq_pin(28), /* IRQ28 */
},
{
I2C_BOARD_INFO("adxl34x", 0x1d),
.irq = irq_pin(26), /* IRQ26 */
},
{
I2C_BOARD_INFO("as3711", 0x40),
.irq = intcs_evt2irq(0x3300), /* IRQ24 */
.platform_data = &as3711_pdata,
},
};
static struct i2c_board_info i2c1_devices[] = {
{
I2C_BOARD_INFO("st1232-ts", 0x55),
.irq = irq_pin(8), /* IRQ8 */
},
};
static struct i2c_board_info i2c3_devices[] = {
{
I2C_BOARD_INFO("pcf8575", 0x20),
.irq = irq_pin(19), /* IRQ19 */
.platform_data = &pcf8575_pdata,
},
};
static struct platform_device *kzm_devices[] __initdata = {
&smsc_device,
&usb_host_device,
&usbhs_device,
&lcdc_device,
&mmc_device,
&vcc_sdhi0,
&vcc_sdhi2,
&sdhi0_device,
&sdhi2_device,
&gpio_keys_device,
&fsi_device,
&fsi_ak4648_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
/* FSIA (AK4648) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_1", "i2c3"),
/* LCD */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_sync", "lcd"),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA4 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_ctrl", "sdhi2"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_cs4", "bsc"),
/* USB */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
"usb_vbus", "usb"),
};
static void __init kzm_init(void)
{
regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
sh73a0_pinmux_init();
/* SMSC */
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
/* Touchscreen */
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices));
i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices));
sh73a0_add_standard_devices();
platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
sh73a0_pm_init();
}
static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
{
#define RESCNT2 IOMEM(0xe6188020)
/* Do soft power on reset */
writel((1 << 31), RESCNT2);
}
static const char *kzm9g_boards_compat_dt[] __initdata = {
"renesas,kzm9g",
NULL,
};
DT_MACHINE_START(KZM9G_DT, "kzm9g")
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
.init_early = sh73a0_add_early_devices,
.init_irq = sh73a0_init_irq,
.init_machine = kzm_init,
.init_late = shmobile_init_late,
.init_time = sh73a0_earlytimer_init,
.restart = kzm9g_restart,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END

675
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -1,675 +0,0 @@
/*
* R8A7740 processor support
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include "clock.h"
#include "common.h"
#include "r8a7740.h"
/*
* | MDx | XTAL1/EXTAL1 | System | EXTALR |
* Clock |-------+-----------------+ clock | 32.768 | RCLK
* Mode | 2/1/0 | src MHz | source | KHz | source
* -------+-------+-----------------+-----------+--------+----------
* 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
* 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
* 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
* 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
* 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
* 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
* 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
* 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
*/
/* CPG registers */
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define VCLKCR1 IOMEM(0xE6150008)
#define VCLKCR2 IOMEM(0xE615000c)
#define FRQCRC IOMEM(0xe61500e0)
#define FSIACKCR IOMEM(0xe6150018)
#define PLLC01CR IOMEM(0xe6150028)
#define SUBCKCR IOMEM(0xe6150080)
#define USBCKCR IOMEM(0xe615008c)
#define MSTPSR0 IOMEM(0xe6150030)
#define MSTPSR1 IOMEM(0xe6150038)
#define MSTPSR2 IOMEM(0xe6150040)
#define MSTPSR3 IOMEM(0xe6150048)
#define MSTPSR4 IOMEM(0xe615004c)
#define FSIBCKCR IOMEM(0xe6150090)
#define HDMICKCR IOMEM(0xe6150094)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define FSIDIVA IOMEM(0xFE1F8000)
#define FSIDIVB IOMEM(0xFE1F8008)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk extalr_clk = {
.rate = 32768,
};
/*
* 25MHz default rate for the EXTAL1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk extal1_clk = {
.rate = 25000000,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk extal2_clk = {
.rate = 48000000,
};
/*
* 27MHz default rate for the DV_CLKI root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk dv_clk = {
.rate = 27000000,
};
SH_CLK_RATIO(div2, 1, 2);
SH_CLK_RATIO(div1k, 1, 1024);
SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
/* Main clock */
static struct clk system_clk = {
.ops = &followparent_clk_ops,
};
SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
/* r_clk */
static struct clk r_clk = {
.ops = &followparent_clk_ops,
};
/* PLLC0/PLLC1 */
static unsigned long pllc01_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC01CR) & (1 << 14))
mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc01_clk_ops = {
.recalc = pllc01_recalc,
};
static struct clk pllc0_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &system_clk,
.enable_reg = (void __iomem *)FRQCRC,
};
static struct clk pllc1_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &system_div2_clk,
.enable_reg = (void __iomem *)FRQCRA,
};
/* PLLC1 / 2 */
SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
/* USB clock */
/*
* USBCKCR is controlling usb24 clock
* bit[7] : parent clock
* bit[6] : clock divide rate
* And this bit[7] is used as a "usb24s" from other devices.
* (Video clock / Sub clock / SPU clock)
* You can controll this clock as a below.
*
* struct clk *usb24 = clk_get(dev, "usb24");
* struct clk *usb24s = clk_get(NULL, "usb24s");
* struct clk *system = clk_get(NULL, "system_clk");
* int rate = clk_get_rate(system);
*
* clk_set_parent(usb24s, system); // for bit[7]
* clk_set_rate(usb24, rate / 2); // for bit[6]
*/
static struct clk *usb24s_parents[] = {
[0] = &system_clk,
[1] = &extal2_clk
};
static int usb24s_enable(struct clk *clk)
{
__raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
return 0;
}
static void usb24s_disable(struct clk *clk)
{
__raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
}
static int usb24s_set_parent(struct clk *clk, struct clk *parent)
{
int i, ret;
u32 val;
if (!clk->parent_table || !clk->parent_num)
return -EINVAL;
/* Search the parent */
for (i = 0; i < clk->parent_num; i++)
if (clk->parent_table[i] == parent)
break;
if (i == clk->parent_num)
return -ENODEV;
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
val = __raw_readl(USBCKCR);
val &= ~(1 << 7);
val |= i << 7;
__raw_writel(val, USBCKCR);
return 0;
}
static struct sh_clk_ops usb24s_clk_ops = {
.recalc = followparent_recalc,
.enable = usb24s_enable,
.disable = usb24s_disable,
.set_parent = usb24s_set_parent,
};
static struct clk usb24s_clk = {
.ops = &usb24s_clk_ops,
.parent_table = usb24s_parents,
.parent_num = ARRAY_SIZE(usb24s_parents),
.parent = &system_clk,
};
static unsigned long usb24_recalc(struct clk *clk)
{
return clk->parent->rate /
((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
};
static int usb24_set_rate(struct clk *clk, unsigned long rate)
{
u32 val;
/* closer to which ? parent->rate or parent->rate/2 */
val = __raw_readl(USBCKCR);
val &= ~(1 << 6);
val |= (rate > (clk->parent->rate / 4) * 3) << 6;
__raw_writel(val, USBCKCR);
return 0;
}
static struct sh_clk_ops usb24_clk_ops = {
.recalc = usb24_recalc,
.set_rate = usb24_set_rate,
};
static struct clk usb24_clk = {
.ops = &usb24_clk_ops,
.parent = &usb24s_clk,
};
/* External FSIACK/FSIBCK clock */
static struct clk fsiack_clk = {
};
static struct clk fsibck_clk = {
};
static struct clk *main_clks[] = {
&extalr_clk,
&extal1_clk,
&extal2_clk,
&extal1_div2_clk,
&extal1_div1024_clk,
&extal1_div2048_clk,
&extal2_div2_clk,
&dv_clk,
&system_clk,
&system_div2_clk,
&r_clk,
&pllc0_clk,
&pllc1_clk,
&pllc1_div2_clk,
&usb24s_clk,
&usb24_clk,
&fsiack_clk,
&fsibck_clk,
};
/* DIV4 clocks */
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in FRQCRB to update hardware setting */
value = __raw_readl(FRQCRB);
value |= (1 << 31);
__raw_writel(value, FRQCRB);
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 32, 36, 48, 0, 72, 96, 0 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum {
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
DIV4_NR
};
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
[DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
};
/* DIV6 reparent */
enum {
DIV6_HDMI,
DIV6_VCLK1, DIV6_VCLK2,
DIV6_FSIA, DIV6_FSIB,
DIV6_REPARENT_NR,
};
static struct clk *hdmi_parent[] = {
[0] = &pllc1_div2_clk,
[1] = &system_clk,
[2] = &dv_clk
};
static struct clk *vclk_parents[8] = {
[0] = &pllc1_div2_clk,
[2] = &dv_clk,
[3] = &usb24s_clk,
[4] = &extal1_div2_clk,
[5] = &extalr_clk,
};
static struct clk *fsia_parents[] = {
[0] = &pllc1_div2_clk,
[1] = &fsiack_clk, /* external clock */
};
static struct clk *fsib_parents[] = {
[0] = &pllc1_div2_clk,
[1] = &fsibck_clk, /* external clock */
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
[DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
[DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
[DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
};
/* DIV6 clocks */
enum {
DIV6_SUB,
DIV6_NR
};
static struct clk div6_clks[DIV6_NR] = {
[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
};
/* HDMI1/2 clock */
static unsigned long hdmi12_recalc(struct clk *clk)
{
u32 val = __raw_readl(HDMICKCR);
int shift = (int)clk->priv;
val >>= shift;
val &= 0x3;
return clk->parent->rate / (1 << val);
};
static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
{
u32 val, mask;
int i, shift;
for (i = 0; i < 3; i++)
if (rate == clk->parent->rate / (1 << i))
goto find;
return -ENODEV;
find:
shift = (int)clk->priv;
val = __raw_readl(HDMICKCR);
mask = ~(0x3 << shift);
val = (val & mask) | i << shift;
__raw_writel(val, HDMICKCR);
return 0;
};
static struct sh_clk_ops hdmi12_clk_ops = {
.recalc = hdmi12_recalc,
.set_rate = hdmi12_set_rate,
};
static struct clk hdmi1_clk = {
.ops = &hdmi12_clk_ops,
.priv = (void *)9,
.parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
};
static struct clk hdmi2_clk = {
.ops = &hdmi12_clk_ops,
.priv = (void *)11,
.parent = &div6_reparent_clks[DIV6_HDMI], /* late install */
};
static struct clk *late_main_clks[] = {
&hdmi1_clk,
&hdmi2_clk,
};
/* FSI DIV */
enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
static struct clk fsidivs[] = {
[FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
[FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
};
/* MSTP */
enum {
MSTP128, MSTP127, MSTP125,
MSTP116, MSTP111, MSTP100, MSTP117,
MSTP230, MSTP229,
MSTP222,
MSTP218, MSTP217, MSTP216, MSTP214,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP329, MSTP328, MSTP323, MSTP320,
MSTP314, MSTP313, MSTP312,
MSTP309, MSTP304,
MSTP416, MSTP415, MSTP407, MSTP406,
MSTP_NR
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 28, 0), /* CEU21 */
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
[MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
[MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
[MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */
[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
[MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */
[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */
[MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
[MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
[MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */
[MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("extalr", &extalr_clk),
CLKDEV_CON_ID("extal1", &extal1_clk),
CLKDEV_CON_ID("extal2", &extal2_clk),
CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
CLKDEV_CON_ID("dv_clk", &dv_clk),
CLKDEV_CON_ID("system_clk", &system_clk),
CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
CLKDEV_CON_ID("usb24s", &usb24s_clk),
CLKDEV_CON_ID("hdmi1", &hdmi1_clk),
CLKDEV_CON_ID("hdmi2", &hdmi2_clk),
CLKDEV_CON_ID("video1", &div6_reparent_clks[DIV6_VCLK1]),
CLKDEV_CON_ID("video2", &div6_reparent_clks[DIV6_VCLK2]),
CLKDEV_CON_ID("fsiack", &fsiack_clk),
CLKDEV_CON_ID("fsibck", &fsibck_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
/* DIV6 clocks */
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]),
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]),
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("e6c30000.serial", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("e9a00000.ethernet", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]),
/* ICK */
CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]),
CLKDEV_ICK_ID("fck", "fff90000.timer", &mstp_clks[MSTP111]),
CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]),
CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]),
CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]),
CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]),
CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
};
void __init r8a7740_clock_init(u8 md_ck)
{
int k, ret = 0;
/* detect system clock parent */
if (md_ck & MD_CK1)
system_clk.parent = &extal1_div2_clk;
else
system_clk.parent = &extal1_clk;
/* detect RCLK parent */
switch (md_ck & (MD_CK2 | MD_CK1)) {
case MD_CK2 | MD_CK1:
r_clk.parent = &extal1_div2048_clk;
break;
case MD_CK2:
r_clk.parent = &extal1_div1024_clk;
break;
case MD_CK1:
default:
r_clk.parent = &extalr_clk;
break;
}
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_div6_reparent_register(div6_reparent_clks,
DIV6_REPARENT_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
if (!ret)
ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup r8a7740 clocks\n");
}

752
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -1,752 +0,0 @@
/*
* sh73a0 clock framework support
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <asm/processor.h>
#include "clock.h"
#include "common.h"
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define FRQCRD IOMEM(0xe61500e4)
#define VCLKCR1 IOMEM(0xe6150008)
#define VCLKCR2 IOMEM(0xe615000C)
#define VCLKCR3 IOMEM(0xe615001C)
#define ZBCKCR IOMEM(0xe6150010)
#define FLCKCR IOMEM(0xe6150014)
#define SD0CKCR IOMEM(0xe6150074)
#define SD1CKCR IOMEM(0xe6150078)
#define SD2CKCR IOMEM(0xe615007C)
#define FSIACKCR IOMEM(0xe6150018)
#define FSIBCKCR IOMEM(0xe6150090)
#define SUBCKCR IOMEM(0xe6150080)
#define SPUACKCR IOMEM(0xe6150084)
#define SPUVCKCR IOMEM(0xe6150094)
#define MSUCKCR IOMEM(0xe6150088)
#define HSICKCR IOMEM(0xe615008C)
#define MFCK1CR IOMEM(0xe6150098)
#define MFCK2CR IOMEM(0xe615009C)
#define DSITCKCR IOMEM(0xe6150060)
#define DSI0PCKCR IOMEM(0xe6150064)
#define DSI1PCKCR IOMEM(0xe6150068)
#define DSI0PHYCR 0xe615006C
#define DSI1PHYCR 0xe6150070
#define PLLECR IOMEM(0xe61500d0)
#define PLL0CR IOMEM(0xe61500d8)
#define PLL1CR IOMEM(0xe6150028)
#define PLL2CR IOMEM(0xe615002c)
#define PLL3CR IOMEM(0xe61500dc)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define SMSTPCR5 IOMEM(0xe6150144)
#define CKSCR IOMEM(0xe61500c0)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk r_clk = {
.rate = 32768,
};
/*
* 26MHz default rate for the EXTAL1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh73a0_extal1_clk = {
.rate = 26000000,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
struct clk sh73a0_extal2_clk = {
.rate = 48000000,
};
static struct sh_clk_ops main_clk_ops = {
.recalc = followparent_recalc,
};
/* Main clock */
static struct clk main_clk = {
/* .parent wll be set on sh73a0_clock_init() */
.ops = &main_clk_ops,
};
/* PLL0, PLL1, PLL2, PLL3 */
static unsigned long pll_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
/* handle CFG bit for PLL1 and PLL2 */
switch (clk->enable_bit) {
case 1:
case 2:
if (__raw_readl(clk->enable_reg) & (1 << 20))
mult *= 2;
}
}
return clk->parent->rate * mult;
}
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll0_clk = {
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &main_clk,
.enable_reg = (void __iomem *)PLL0CR,
.enable_bit = 0,
};
static struct clk pll1_clk = {
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &main_clk,
.enable_reg = (void __iomem *)PLL1CR,
.enable_bit = 1,
};
static struct clk pll2_clk = {
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &main_clk,
.enable_reg = (void __iomem *)PLL2CR,
.enable_bit = 2,
};
static struct clk pll3_clk = {
.ops = &pll_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &main_clk,
.enable_reg = (void __iomem *)PLL3CR,
.enable_bit = 3,
};
/* A fixed divide block */
SH_CLK_RATIO(div2, 1, 2);
SH_CLK_RATIO(div7, 1, 7);
SH_CLK_RATIO(div13, 1, 13);
SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
/* External input clock */
struct clk sh73a0_extcki_clk = {
};
struct clk sh73a0_extalr_clk = {
};
static struct clk *main_clks[] = {
&r_clk,
&sh73a0_extal1_clk,
&sh73a0_extal2_clk,
&extal1_div2_clk,
&extal2_div2_clk,
&main_clk,
&main_div2_clk,
&pll0_clk,
&pll1_clk,
&pll2_clk,
&pll3_clk,
&pll1_div2_clk,
&pll1_div7_clk,
&pll1_div13_clk,
&sh73a0_extcki_clk,
&sh73a0_extalr_clk,
};
static int frqcr_kick(void)
{
int i;
/* set KICK bit in FRQCRB to update hardware setting, check success */
__raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
for (i = 1000; i; i--)
if (__raw_readl(FRQCRB) & (1 << 31))
cpu_relax();
else
return i;
return -ETIMEDOUT;
}
static void div4_kick(struct clk *clk)
{
frqcr_kick();
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
24, 0, 36, 48, 7 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
/*
* ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
* exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
* 239.2MHz for VDD_DVFS=1.315V.
*/
[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
[DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
[DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
};
static unsigned long twd_recalc(struct clk *clk)
{
return clk_get_rate(clk->parent) / 4;
}
static struct sh_clk_ops twd_clk_ops = {
.recalc = twd_recalc,
};
static struct clk twd_clk = {
.parent = &div4_clks[DIV4_Z],
.ops = &twd_clk_ops,
};
static struct sh_clk_ops zclk_ops, kicker_ops;
static const struct sh_clk_ops *div4_clk_ops;
static int zclk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (!clk->parent || !__clk_get(clk->parent))
return -ENODEV;
if (readl(FRQCRB) & (1 << 31))
return -EBUSY;
if (rate == clk_get_rate(clk->parent)) {
/* 1:1 - switch off divider */
__raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
/* nullify the divider to prepare for the next time */
ret = div4_clk_ops->set_rate(clk, rate / 2);
if (!ret)
ret = frqcr_kick();
if (ret > 0)
ret = 0;
} else {
/* Enable the divider */
__raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
ret = frqcr_kick();
if (ret >= 0)
/*
* set the divider - call the DIV4 method, it will kick
* FRQCRB too
*/
ret = div4_clk_ops->set_rate(clk, rate);
if (ret < 0)
goto esetrate;
}
esetrate:
__clk_put(clk->parent);
return ret;
}
static long zclk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
parent_freq = clk_get_rate(clk->parent);
if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
return parent_freq;
return div_freq;
}
static unsigned long zclk_recalc(struct clk *clk)
{
/*
* Must recalculate frequencies in case PLL0 has been changed, even if
* the divisor is unused ATM!
*/
unsigned long div_freq = div4_clk_ops->recalc(clk);
if (__raw_readl(FRQCRB) & (1 << 28))
return div_freq;
return clk_get_rate(clk->parent);
}
static int kicker_set_rate(struct clk *clk, unsigned long rate)
{
if (__raw_readl(FRQCRB) & (1 << 31))
return -EBUSY;
return div4_clk_ops->set_rate(clk, rate);
}
static void div4_clk_extend(void)
{
int i;
div4_clk_ops = div4_clks[0].ops;
/* Add a kicker-busy check before changing the rate */
kicker_ops = *div4_clk_ops;
/* We extend the DIV4 clock with a 1:1 pass-through case */
zclk_ops = *div4_clk_ops;
kicker_ops.set_rate = kicker_set_rate;
zclk_ops.set_rate = zclk_set_rate;
zclk_ops.round_rate = zclk_round_rate;
zclk_ops.recalc = zclk_recalc;
for (i = 0; i < DIV4_NR; i++)
div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
}
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
DIV6_HSI, DIV6_MFG1, DIV6_MFG2,
DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
DIV6_NR };
static struct clk *vck_parent[8] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &sh73a0_extcki_clk,
[3] = &sh73a0_extal2_clk,
[4] = &main_div2_clk,
[5] = &sh73a0_extalr_clk,
[6] = &main_clk,
};
static struct clk *pll_parent[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &pll1_div13_clk,
};
static struct clk *hsi_parent[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &pll1_div7_clk,
};
static struct clk *pll_extal2_parent[] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &sh73a0_extal2_clk,
[3] = &sh73a0_extal2_clk,
};
static struct clk *dsi_parent[8] = {
[0] = &pll1_div2_clk,
[1] = &pll2_clk,
[2] = &main_clk,
[3] = &sh73a0_extal2_clk,
[4] = &sh73a0_extcki_clk,
};
static struct clk div6_clks[DIV6_NR] = {
[DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
[DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
[DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
[DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
[DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
[DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
[DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
[DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
[DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
};
/* DSI DIV */
static unsigned long dsiphy_recalc(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base);
/* FIXME */
if (!(value & 0x000B8000))
return clk->parent->rate;
value &= 0x3f;
value += 1;
if ((value < 12) ||
(value > 33)) {
pr_err("DSIPHY has wrong value (%d)", value);
return 0;
}
return clk->parent->rate / value;
}
static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_mult_range_round(clk, 12, 33, rate);
}
static void dsiphy_disable(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base);
value &= ~0x000B8000;
__raw_writel(value , clk->mapping->base);
}
static int dsiphy_enable(struct clk *clk)
{
u32 value;
int multi;
value = __raw_readl(clk->mapping->base);
multi = (value & 0x3f) + 1;
if ((multi < 12) || (multi > 33))
return -EIO;
__raw_writel(value | 0x000B8000, clk->mapping->base);
return 0;
}
static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
{
u32 value;
int idx;
idx = rate / clk->parent->rate;
if ((idx < 12) || (idx > 33))
return -EINVAL;
idx += -1;
value = __raw_readl(clk->mapping->base);
value = (value & ~0x3f) + idx;
__raw_writel(value, clk->mapping->base);
return 0;
}
static struct sh_clk_ops dsiphy_clk_ops = {
.recalc = dsiphy_recalc,
.round_rate = dsiphy_round_rate,
.set_rate = dsiphy_set_rate,
.enable = dsiphy_enable,
.disable = dsiphy_disable,
};
static struct clk_mapping dsi0phy_clk_mapping = {
.phys = DSI0PHYCR,
.len = 4,
};
static struct clk_mapping dsi1phy_clk_mapping = {
.phys = DSI1PHYCR,
.len = 4,
};
static struct clk dsi0phy_clk = {
.ops = &dsiphy_clk_ops,
.parent = &div6_clks[DIV6_DSI0P], /* late install */
.mapping = &dsi0phy_clk_mapping,
};
static struct clk dsi1phy_clk = {
.ops = &dsiphy_clk_ops,
.parent = &div6_clks[DIV6_DSI1P], /* late install */
.mapping = &dsi1phy_clk_mapping,
};
static struct clk *late_main_clks[] = {
&dsi0phy_clk,
&dsi1phy_clk,
&twd_clk,
};
enum { MSTP001,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
MSTP219, MSTP218, MSTP217,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
MSTP314, MSTP313, MSTP312, MSTP311,
MSTP304, MSTP303, MSTP302, MSTP301, MSTP300,
MSTP411, MSTP410, MSTP403,
MSTP508,
MSTP_NR };
#define MSTP(_parent, _reg, _bit, _flags) \
SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
static struct clk mstp_clks[MSTP_NR] = {
[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
[MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
[MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
[MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
[MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
[MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
[MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
[MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
[MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
[MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
[MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
[MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
[MSTP304] = MSTP(&main_div2_clk, SMSTPCR3, 4, 0), /* TPU0 */
[MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
[MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
[MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
[MSTP300] = MSTP(&main_div2_clk, SMSTPCR3, 0, 0), /* TPU4 */
[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
[MSTP508] = MSTP(&div4_clks[DIV4_HP], SMSTPCR5, 8, 0), /* INTCA0 */
};
/* The lookups structure below includes duplicate entries for some clocks
* with alternate names.
* - The traditional name used when a device is initialised with platform data
* - The name used when a device is initialised using device tree
* The longer-term aim is to remove these duplicates, and indeed the
* lookups table entirely, by describing clocks using device tree.
*/
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
/* DIV4 clocks */
CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
CLKDEV_DEV_ID("e6824000.i2c", &mstp_clks[MSTP001]), /* I2C2 */
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP219]), /* SCIFA7 */
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("e6c50000.serial", &mstp_clks[MSTP203]), /* SCIFA1 */
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("e6c60000.serial", &mstp_clks[MSTP202]), /* SCIFA2 */
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("e6c70000.serial", &mstp_clks[MSTP201]), /* SCIFA3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("e6c80000.serial", &mstp_clks[MSTP200]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP331]), /* SCIFA6 */
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */
CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */
CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */
CLKDEV_DEV_ID("renesas-tpu-pwm.3", &mstp_clks[MSTP301]), /* TPU3 */
CLKDEV_DEV_ID("renesas-tpu-pwm.4", &mstp_clks[MSTP300]), /* TPU4 */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("e6900000.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("e6900004.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("e6900008.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP508]), /* INTCA0 */
CLKDEV_DEV_ID("e690000c.irqpin", &mstp_clks[MSTP508]), /* INTCA0 */
/* ICK */
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */
CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), /* CMT1 */
CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
};
void __init sh73a0_clock_init(void)
{
int k, ret = 0;
/* Set SDHI clocks to a known state */
__raw_writel(0x108, SD0CKCR);
__raw_writel(0x108, SD1CKCR);
__raw_writel(0x108, SD2CKCR);
/* detect main clock parent */
switch ((__raw_readl(CKSCR) >> 28) & 0x03) {
case 0:
main_clk.parent = &sh73a0_extal1_clk;
break;
case 1:
main_clk.parent = &extal1_div2_clk;
break;
case 2:
main_clk.parent = &sh73a0_extal2_clk;
break;
case 3:
main_clk.parent = &extal2_div2_clk;
break;
}
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret) {
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
div4_clk_extend();
}
if (!ret)
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
shmobile_clk_init();
else
panic("failed to setup sh73a0 clocks\n");
}

84
arch/arm/mach-shmobile/dma-register.h
View File

@ -1,84 +0,0 @@
/*
* SH-ARM CPU-specific DMA definitions, used by both DMA drivers
*
* Copyright (C) 2012 Renesas Solutions Corp
*
* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef DMA_REGISTER_H
#define DMA_REGISTER_H
/*
* Direct Memory Access Controller
*/
/* Transmit sizes and respective CHCR register values */
enum {
XMIT_SZ_8BIT = 0,
XMIT_SZ_16BIT = 1,
XMIT_SZ_32BIT = 2,
XMIT_SZ_64BIT = 7,
XMIT_SZ_128BIT = 3,
XMIT_SZ_256BIT = 4,
XMIT_SZ_512BIT = 5,
};
/* log2(size / 8) - used to calculate number of transfers */
static const unsigned int dma_ts_shift[] = {
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_64BIT] = 3,
[XMIT_SZ_128BIT] = 4,
[XMIT_SZ_256BIT] = 5,
[XMIT_SZ_512BIT] = 6,
};
#define TS_LOW_BIT 0x3 /* --xx */
#define TS_HI_BIT 0xc /* xx-- */
#define TS_LOW_SHIFT (3)
#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
#define TS_INDEX2VAL(i) \
((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
(((i) & TS_HI_BIT) << TS_HI_SHIFT))
#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL((xmit_sz)))
#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL((xmit_sz)))
/*
* USB High-Speed DMAC
*/
/* Transmit sizes and respective CHCR register values */
enum {
USBTS_XMIT_SZ_8BYTE = 0,
USBTS_XMIT_SZ_16BYTE = 1,
USBTS_XMIT_SZ_32BYTE = 2,
};
/* log2(size / 8) - used to calculate number of transfers */
static const unsigned int dma_usbts_shift[] = {
[USBTS_XMIT_SZ_8BYTE] = 3,
[USBTS_XMIT_SZ_16BYTE] = 4,
[USBTS_XMIT_SZ_32BYTE] = 5,
};
#define USBTS_LOW_BIT 0x3 /* --xx */
#define USBTS_HI_BIT 0x0 /* ---- */
#define USBTS_LOW_SHIFT 6
#define USBTS_HI_SHIFT 0
#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
#endif /* DMA_REGISTER_H */

410
arch/arm/mach-shmobile/include/mach/head-kzm9g.txt
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@ -1,410 +0,0 @@
LIST "KZM9G low-level initialization routine."
LIST "Adapted from u-boot KZM9G support code."
LIST "Copyright (C) 2013 Ulrich Hecht"
LIST "This program is free software; you can redistribute it and/or modify"
LIST "it under the terms of the GNU General Public License version 2 as"
LIST "published by the Free Software Foundation."
LIST "This program is distributed in the hope that it will be useful,"
LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of"
LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the"
LIST "GNU General Public License for more details."
LIST "Register definitions:"
LIST "Secure control register"
#define LIFEC_SEC_SRC (0xE6110008)
LIST "RWDT"
#define RWDT_BASE (0xE6020000)
#define RWTCSRA0 (RWDT_BASE + 0x04)
LIST "HPB Semaphore Control Registers"
#define HPBSCR_BASE (0xE6000000)
#define HPBCTRL6 (HPBSCR_BASE + 0x1030)
#define SBSC1_BASE (0xFE400000)
#define SDCR0A (SBSC1_BASE + 0x0008)
#define SDCR1A (SBSC1_BASE + 0x000C)
#define SDPCRA (SBSC1_BASE + 0x0010)
#define SDCR0SA (SBSC1_BASE + 0x0018)
#define SDCR1SA (SBSC1_BASE + 0x001C)
#define RTCSRA (SBSC1_BASE + 0x0020)
#define RTCORA (SBSC1_BASE + 0x0028)
#define RTCORHA (SBSC1_BASE + 0x002C)
#define SDWCRC0A (SBSC1_BASE + 0x0040)
#define SDWCRC1A (SBSC1_BASE + 0x0044)
#define SDWCR00A (SBSC1_BASE + 0x0048)
#define SDWCR01A (SBSC1_BASE + 0x004C)
#define SDWCR10A (SBSC1_BASE + 0x0050)
#define SDWCR11A (SBSC1_BASE + 0x0054)
#define SDWCR2A (SBSC1_BASE + 0x0060)
#define SDWCRC2A (SBSC1_BASE + 0x0064)
#define ZQCCRA (SBSC1_BASE + 0x0068)
#define SDMRACR0A (SBSC1_BASE + 0x0084)
#define SDMRTMPCRA (SBSC1_BASE + 0x008C)
#define SDMRTMPMSKA (SBSC1_BASE + 0x0094)
#define SDGENCNTA (SBSC1_BASE + 0x009C)
#define SDDRVCR0A (SBSC1_BASE + 0x00B4)
#define DLLCNT0A (SBSC1_BASE + 0x0354)
#define SDMRA1 (0xFE500000)
#define SDMRA2 (0xFE5C0000)
#define SDMRA3 (0xFE504000)
#define SBSC2_BASE (0xFB400000)
#define SDCR0B (SBSC2_BASE + 0x0008)
#define SDCR1B (SBSC2_BASE + 0x000C)
#define SDPCRB (SBSC2_BASE + 0x0010)
#define SDCR0SB (SBSC2_BASE + 0x0018)
#define SDCR1SB (SBSC2_BASE + 0x001C)
#define RTCSRB (SBSC2_BASE + 0x0020)
#define RTCORB (SBSC2_BASE + 0x0028)
#define RTCORHB (SBSC2_BASE + 0x002C)
#define SDWCRC0B (SBSC2_BASE + 0x0040)
#define SDWCRC1B (SBSC2_BASE + 0x0044)
#define SDWCR00B (SBSC2_BASE + 0x0048)
#define SDWCR01B (SBSC2_BASE + 0x004C)
#define SDWCR10B (SBSC2_BASE + 0x0050)
#define SDWCR11B (SBSC2_BASE + 0x0054)
#define SDPDCR0B (SBSC2_BASE + 0x0058)
#define SDWCR2B (SBSC2_BASE + 0x0060)
#define SDWCRC2B (SBSC2_BASE + 0x0064)
#define ZQCCRB (SBSC2_BASE + 0x0068)
#define SDMRACR0B (SBSC2_BASE + 0x0084)
#define SDMRTMPCRB (SBSC2_BASE + 0x008C)
#define SDMRTMPMSKB (SBSC2_BASE + 0x0094)
#define SDGENCNTB (SBSC2_BASE + 0x009C)
#define DPHYCNT0B (SBSC2_BASE + 0x00A0)
#define DPHYCNT1B (SBSC2_BASE + 0x00A4)
#define DPHYCNT2B (SBSC2_BASE + 0x00A8)
#define SDDRVCR0B (SBSC2_BASE + 0x00B4)
#define DLLCNT0B (SBSC2_BASE + 0x0354)
#define SDMRB1 (0xFB500000)
#define SDMRB2 (0xFB5C0000)
#define SDMRB3 (0xFB504000)
#define CPG_BASE (0xE6150000)
#define FRQCRA (CPG_BASE + 0x0000)
#define FRQCRB (CPG_BASE + 0x0004)
#define FRQCRD (CPG_BASE + 0x00E4)
#define VCLKCR1 (CPG_BASE + 0x0008)
#define VCLKCR2 (CPG_BASE + 0x000C)
#define VCLKCR3 (CPG_BASE + 0x001C)
#define ZBCKCR (CPG_BASE + 0x0010)
#define FLCKCR (CPG_BASE + 0x0014)
#define SD0CKCR (CPG_BASE + 0x0074)
#define SD1CKCR (CPG_BASE + 0x0078)
#define SD2CKCR (CPG_BASE + 0x007C)
#define FSIACKCR (CPG_BASE + 0x0018)
#define SUBCKCR (CPG_BASE + 0x0080)
#define SPUACKCR (CPG_BASE + 0x0084)
#define SPUVCKCR (CPG_BASE + 0x0094)
#define MSUCKCR (CPG_BASE + 0x0088)
#define HSICKCR (CPG_BASE + 0x008C)
#define FSIBCKCR (CPG_BASE + 0x0090)
#define MFCK1CR (CPG_BASE + 0x0098)
#define MFCK2CR (CPG_BASE + 0x009C)
#define DSITCKCR (CPG_BASE + 0x0060)
#define DSI0PCKCR (CPG_BASE + 0x0064)
#define DSI1PCKCR (CPG_BASE + 0x0068)
#define DSI0PHYCR (CPG_BASE + 0x006C)
#define DVFSCR3 (CPG_BASE + 0x0174)
#define DVFSCR4 (CPG_BASE + 0x0178)
#define DVFSCR5 (CPG_BASE + 0x017C)
#define MPMODE (CPG_BASE + 0x00CC)
#define PLLECR (CPG_BASE + 0x00D0)
#define PLL0CR (CPG_BASE + 0x00D8)
#define PLL1CR (CPG_BASE + 0x0028)
#define PLL2CR (CPG_BASE + 0x002C)
#define PLL3CR (CPG_BASE + 0x00DC)
#define PLL0STPCR (CPG_BASE + 0x00F0)
#define PLL1STPCR (CPG_BASE + 0x00C8)
#define PLL2STPCR (CPG_BASE + 0x00F8)
#define PLL3STPCR (CPG_BASE + 0x00FC)
#define RMSTPCR0 (CPG_BASE + 0x0110)
#define RMSTPCR1 (CPG_BASE + 0x0114)
#define RMSTPCR2 (CPG_BASE + 0x0118)
#define RMSTPCR3 (CPG_BASE + 0x011C)
#define RMSTPCR4 (CPG_BASE + 0x0120)
#define RMSTPCR5 (CPG_BASE + 0x0124)
#define SMSTPCR0 (CPG_BASE + 0x0130)
#define SMSTPCR2 (CPG_BASE + 0x0138)
#define SMSTPCR3 (CPG_BASE + 0x013C)
#define CPGXXCR4 (CPG_BASE + 0x0150)
#define SRCR0 (CPG_BASE + 0x80A0)
#define SRCR2 (CPG_BASE + 0x80B0)
#define SRCR3 (CPG_BASE + 0x80A8)
#define VREFCR (CPG_BASE + 0x00EC)
#define PCLKCR (CPG_BASE + 0x1020)
#define PORT32CR (0xE6051020)
#define PORT33CR (0xE6051021)
#define PORT34CR (0xE6051022)
#define PORT35CR (0xE6051023)
LIST "DRAM initialization code:"
EW RWTCSRA0, 0xA507
ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF
ED_AND SMSTPCR3,0xFFFF7FFF
ED_AND SRCR3, 0xFFFF7FFF
ED_AND SMSTPCR2,0xFFFBFFFF
ED_AND SRCR2, 0xFFFBFFFF
ED PLLECR, 0x00000000
WAIT_MASK PLLECR, 0x00000F00, 0x00000000
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
ED PLL0CR, 0x2D000000
ED PLL1CR, 0x17100000
ED FRQCRB, 0x96235880
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
ED FLCKCR, 0x0000000B
ED_AND SMSTPCR0, 0xFFFFFFFD
ED_AND SRCR0, 0xFFFFFFFD
ED 0xE6001628, 0x514
ED 0xE6001648, 0x514
ED 0xE6001658, 0x514
ED 0xE6001678, 0x514
ED DVFSCR4, 0x00092000
ED DVFSCR5, 0x000000DC
ED PLLECR, 0x00000000
WAIT_MASK PLLECR, 0x00000F00, 0x00000000
ED FRQCRA, 0x0012453C
ED FRQCRB, 0x80431350
WAIT_MASK FRQCRB, 0x80000000, 0x00000000
ED FRQCRD, 0x00000B0B
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
ED PCLKCR, 0x00000003
ED VCLKCR1, 0x0000012F
ED VCLKCR2, 0x00000119
ED VCLKCR3, 0x00000119
ED ZBCKCR, 0x00000002
ED FLCKCR, 0x00000005
ED SD0CKCR, 0x00000080
ED SD1CKCR, 0x00000080
ED SD2CKCR, 0x00000080
ED FSIACKCR, 0x0000003F
ED FSIBCKCR, 0x0000003F
ED SUBCKCR, 0x00000080
ED SPUACKCR, 0x0000000B
ED SPUVCKCR, 0x0000000B
ED MSUCKCR, 0x0000013F
ED HSICKCR, 0x00000080
ED MFCK1CR, 0x0000003F
ED MFCK2CR, 0x0000003F
ED DSITCKCR, 0x00000107
ED DSI0PCKCR, 0x00000313
ED DSI1PCKCR, 0x0000130D
ED DSI0PHYCR, 0x2A800E0E
ED PLL0CR, 0x1E000000
ED PLL0CR, 0x2D000000
ED PLL1CR, 0x17100000
ED PLL2CR, 0x27000080
ED PLL3CR, 0x1D000000
ED PLL0STPCR, 0x00080000
ED PLL1STPCR, 0x000120C0
ED PLL2STPCR, 0x00012000
ED PLL3STPCR, 0x00000030
ED PLLECR, 0x0000000B
WAIT_MASK PLLECR, 0x00000B00, 0x00000B00
ED DVFSCR3, 0x000120F0
ED MPMODE, 0x00000020
ED VREFCR, 0x0000028A
ED RMSTPCR0, 0xE4628087
ED RMSTPCR1, 0xFFFFFFFF
ED RMSTPCR2, 0x53FFFFFF
ED RMSTPCR3, 0xFFFFFFFF
ED RMSTPCR4, 0x00800D3D
ED RMSTPCR5, 0xFFFFF3FF
ED SMSTPCR2, 0x00000000
ED SRCR2, 0x00040000
ED_AND PLLECR, 0xFFFFFFF7
WAIT_MASK PLLECR, 0x00000800, 0x00000000
LIST "set SBSC operational"
ED HPBCTRL6, 0x00000001
WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001
LIST "set SBSC operating frequency"
ED FRQCRD, 0x00001414
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
ED PLL3CR, 0x1D000000
ED_OR PLLECR, 0x00000008
WAIT_MASK PLLECR, 0x00000800, 0x00000800
LIST "enable DLL oscillation in DDRPHY"
ED_OR DLLCNT0A, 0x00000002
LIST "wait >= 100 ns"
ED SDGENCNTA, 0x00000005
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
LIST "target LPDDR2 device settings"
ED SDCR0A, 0xACC90159
ED SDCR1A, 0x00010059
ED SDWCRC0A, 0x50874114
ED SDWCRC1A, 0x33199B37
ED SDWCRC2A, 0x008F2313
ED SDWCR00A, 0x31020707
ED SDWCR01A, 0x0017040A
ED SDWCR10A, 0x31020707
ED SDWCR11A, 0x0017040A
ED SDDRVCR0A, 0x055557ff
ED SDWCR2A, 0x30000000
LIST "drive CKE high"
ED_OR SDPCRA, 0x00000080
WAIT_MASK SDPCRA, 0x00000080, 0x00000080
LIST "wait >= 200 us"
ED SDGENCNTA, 0x00002710
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
LIST "issue reset command to LPDDR2 device"
ED SDMRACR0A, 0x0000003F
ED SDMRA1, 0x00000000
LIST "wait >= 10 (or 1) us (docs inconsistent)"
ED SDGENCNTA, 0x000001F4
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
LIST "MRW ZS initialization calibration command"
ED SDMRACR0A, 0x0000FF0A
ED SDMRA3, 0x00000000
LIST "wait >= 1 us"
ED SDGENCNTA, 0x00000032
WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000
LIST "specify operating mode in LPDDR2"
ED SDMRACR0A, 0x00002201
ED SDMRA1, 0x00000000
ED SDMRACR0A, 0x00000402
ED SDMRA1, 0x00000000
ED SDMRACR0A, 0x00000203
ED SDMRA1, 0x00000000
LIST "initialize DDR interface"
ED SDMRA2, 0x00000000
LIST "temperature sensor control"
ED SDMRTMPCRA, 0x88800004
ED SDMRTMPMSKA,0x00000004
LIST "auto-refreshing control"
ED RTCORA, 0xA55A0032
ED RTCORHA, 0xA55A000C
ED RTCSRA, 0xA55A2048
ED_OR SDCR0A, 0x00000800
ED_OR SDCR1A, 0x00000400
LIST "auto ZQ calibration control"
ED ZQCCRA, 0xFFF20000
ED_OR DLLCNT0B, 0x00000002
ED SDGENCNTB, 0x00000005
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
ED SDCR0B, 0xACC90159
ED SDCR1B, 0x00010059
ED SDWCRC0B, 0x50874114
ED SDWCRC1B, 0x33199B37
ED SDWCRC2B, 0x008F2313
ED SDWCR00B, 0x31020707
ED SDWCR01B, 0x0017040A
ED SDWCR10B, 0x31020707
ED SDWCR11B, 0x0017040A
ED SDDRVCR0B, 0x055557ff
ED SDWCR2B, 0x30000000
ED_OR SDPCRB, 0x00000080
WAIT_MASK SDPCRB, 0x00000080, 0x00000080
ED SDGENCNTB, 0x00002710
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
ED SDMRACR0B, 0x0000003F
LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does"
LIST "not seem to make a lot of sense..."
ED SDMRB1, 0x00000000
ED SDGENCNTB, 0x000001F4
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
ED SDMRACR0B, 0x0000FF0A
ED SDMRB3, 0x00000000
ED SDGENCNTB, 0x00000032
WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000
ED SDMRACR0B, 0x00002201
ED SDMRB1, 0x00000000
ED SDMRACR0B, 0x00000402
ED SDMRB1, 0x00000000
ED SDMRACR0B, 0x00000203
ED SDMRB1, 0x00000000
ED SDMRB2, 0x00000000
ED SDMRTMPCRB, 0x88800004
ED SDMRTMPMSKB, 0x00000004
ED RTCORB, 0xA55A0032
ED RTCORHB, 0xA55A000C
ED RTCSRB, 0xA55A2048
ED_OR SDCR0B, 0x00000800
ED_OR SDCR1B, 0x00000400
ED ZQCCRB, 0xFFF20000
ED_OR SDPDCR0B, 0x00030000
ED DPHYCNT1B, 0xA5390000
ED DPHYCNT0B, 0x00001200
ED DPHYCNT1B, 0x07CE0000
ED DPHYCNT0B, 0x00001247
WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000
ED_AND SDPDCR0B, 0xFFFCFFFF
ED FRQCRD, 0x00000B0B
WAIT_MASK FRQCRD, 0x80000000, 0x00000000
ED CPGXXCR4, 0xfffffffc
LIST "Setup SCIF4 / workaround"
EB PORT32CR, 0x12
EB PORT33CR, 0x22
EB PORT34CR, 0x12
EB PORT35CR, 0x22
EW 0xE6C80000, 0
EB 0xE6C80004, 0x19
EW 0xE6C80008, 0x0030
EW 0xE6C80018, 0
EW 0xE6C80030, 0x0014
LIST "Magic to avoid hangs and corruption on DRAM writes."
LIST "It has been observed that the system would most often hang while"
LIST "decompressing the kernel, and if it didn't it would always write"
LIST "a corrupt image to DRAM."
LIST "This problem does not occur in u-boot, and the reason is that"
LIST "u-boot performs an additional cache invalidation after setting up"
LIST "the DRAM controller. Such an invalidation should not be necessary at"
LIST "this point, and attempts at removing parts of the routine to arrive"
LIST "at the minimal snippet of code necessary to avoid the DRAM stability"
LIST "problem yielded the following:"
MRC p15, 0, r0, c1, c0, 0
MCR p15, 0, r0, c1, c0, 0

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arch/arm/mach-shmobile/include/mach/zboot.h
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#ifndef ZBOOT_H
#define ZBOOT_H
#include <mach/zboot_macros.h>
/**************************************************
*
* board specific settings
*
**************************************************/
#ifdef CONFIG_MACH_KZM9G
#define MEMORY_START 0x43000000
#include "mach/head-kzm9g.txt"
#else
#error "unsupported board."
#endif
#endif /* ZBOOT_H */

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arch/arm/mach-shmobile/include/mach/zboot_macros.h
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#ifndef __ZBOOT_MACRO_H
#define __ZBOOT_MACRO_H
/* The LIST command is used to include comments in the script */
.macro LIST comment
.endm
/* The ED command is used to write a 32-bit word */
.macro ED, addr, data
LDR r0, 1f
LDR r1, 2f
STR r1, [r0]
B 3f
1 : .long \addr
2 : .long \data
3 :
.endm
/* The EW command is used to write a 16-bit word */
.macro EW, addr, data
LDR r0, 1f
LDR r1, 2f
STRH r1, [r0]
B 3f
1 : .long \addr
2 : .long \data
3 :
.endm
/* The EB command is used to write an 8-bit word */
.macro EB, addr, data
LDR r0, 1f
LDR r1, 2f
STRB r1, [r0]
B 3f
1 : .long \addr
2 : .long \data
3 :
.endm
/* The WAIT command is used to delay the execution */
.macro WAIT, time, reg
LDR r1, 1f
LDR r0, 2f
STR r0, [r1]
10 :
LDR r0, [r1]
CMP r0, #0x00000000
BNE 10b
NOP
B 3f
1 : .long \reg
2 : .long \time * 100
3 :
.endm
/* The DD command is used to read a 32-bit word */
.macro DD, start, end
LDR r1, 1f
B 2f
1 : .long \start
2 :
.endm
/* loop until a given value has been read (with mask) */
.macro WAIT_MASK, addr, data, cmp
LDR r0, 2f
LDR r1, 3f
LDR r2, 4f
1:
LDR r3, [r0, #0]
AND r3, r1, r3
CMP r2, r3
BNE 1b
B 5f
2: .long \addr
3: .long \data
4: .long \cmp
5:
.endm
/* read 32-bit value from addr, "or" an immediate and write back */
.macro ED_OR, addr, data
LDR r4, 1f
LDR r5, 2f
LDR r6, [r4]
ORR r5, r6, r5
STR r5, [r4]
B 3f
1: .long \addr
2: .long \data
3:
.endm
/* read 32-bit value from addr, "and" an immediate and write back */
.macro ED_AND, addr, data
LDR r4, 1f
LDR r5, 2f
LDR r6, [r4]
AND r5, r6, r5
STR r5, [r4]
B 3f
1: .long \addr
2: .long \data
3:
.endm
#endif /* __ZBOOT_MACRO_H */

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arch/arm/mach-shmobile/intc-sh73a0.c
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/*
* sh73a0 processor support - INTC hardware block
*
* Copyright (C) 2010 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "intc.h"
#include "irqs.h"
#include "sh73a0.h"
enum {
UNUSED = 0,
/* interrupt sources INTCS */
PINTCS_PINT1, PINTCS_PINT2,
RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
KEYSC_KEY, VINT, MSIOF,
TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
RTDMAC_3_DEI10, RTDMAC_3_DEI11,
FRC, GCU, LCDC1, CSIRX,
DSITX0_DSITX00, DSITX0_DSITX01,
SPU2_SPU0, SPU2_SPU1, FSI,
TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
SPUV,
/* interrupt groups INTCS */
RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
DSITX0, SPU2, TMU1, MSU,
};
static struct intc_vect intcs_vectors[] = {
INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
INTCS_VECT(MSIOF, 0x0d20),
INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
INTCS_VECT(TMU0_TUNI02, 0x0ec0),
INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
INTCS_VECT(MSUG, 0x0f80),
INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
INTCS_VECT(FSI, 0x1840),
INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
INTCS_VECT(TMU1_TUNI12, 0x1940),
INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
INTCS_VECT(SCUW, 0x1b40),
INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
INTCS_VECT(SPUV, 0x2300),
};
static struct intc_group intcs_groups[] __initdata = {
INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
RTDMAC_0_DEI2, RTDMAC_0_DEI3),
INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
RTDMAC_2_DEI8, RTDMAC_2_DEI9),
INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
};
static struct intc_mask_reg intcs_mask_registers[] = {
{ 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
{ 0, 0, 0, CEU,
0, 0, 0, 0 } },
{ 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
{ 0, 0, 0, VPU,
BBIF2, 0, 0, MFI } },
{ 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
{ 0, 0, 0, _2DDMAC_2DDM0,
0, ASA, PEP, ICB } },
{ 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
{ 0, 0, 0, CTI,
JPU_JPEG, 0, LCRC, LCDC } },
{ 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
{ KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
{ 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
{ 0, 0, MSIOF, 0,
_3DG_SGX543, 0, 0, 0 } },
{ 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
{ 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
0, 0, 0, 0 } },
{ 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
{ 0, 0, 0, 0,
0, MSU_MSU, MSU_MSU2, MSUG } },
{ 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
{ 0, RWDT0, CMT2, CMT0,
0, 0, 0, 0 } },
{ 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
{ 0, 0, 0, 0,
0, TSIF1, LMB, TSIF0 } },
{ 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
{ 0, 0, 0, 0,
0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
{ 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
{ RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
{ 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
{ FRC, 0, 0, GCU,
LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
{ 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
{ SPU2_SPU0, SPU2_SPU1, FSI, 0,
0, 0, 0, 0 } },
{ 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
{ TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
TSIF2, CMT4, 0, 0 } },
{ 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
{ MFIS2, CPORTS2R, 0, 0,
0, 0, 0, TSG } },
{ 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
{ DMASCH1, 0, SCUW, VIO60,
VIO61, CEU21, 0, CSI21 } },
{ 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
{ DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
{ 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
{ MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
0, 0, 0, 0 } },
{ 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
{ SPUV, 0, 0, 0,
0, 0, 0, 0 } },
};
/* Priority is needed for INTCA to receive the INTCS interrupt */
static struct intc_prio_reg intcs_prio_registers[] = {
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
{ 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
{ 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
0, 0 } },
{ 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
CMT2, CMT0 } },
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
TMU0_TUNI02, TSIF1 } },
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
{ 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
{ 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
{ 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
{ 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
{ 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
{ 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
{ 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
{ 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
DISP, DSRV } },
{ 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
MSTIF0_MST00I, MSTIF0_MST01I } },
{ 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
0, 0 } },
{ 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
};
static struct resource intcs_resources[] __initdata = {
[0] = {
.start = 0xffd20000,
.end = 0xffd201ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0xffd50000,
.end = 0xffd501ff,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = 0xffd60000,
.end = 0xffd601ff,
.flags = IORESOURCE_MEM,
}
};
static struct intc_desc intcs_desc __initdata = {
.name = "sh73a0-intcs",
.resource = intcs_resources,
.num_resources = ARRAY_SIZE(intcs_resources),
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
intcs_prio_registers, NULL, NULL),
};
static struct irqaction sh73a0_intcs_cascade;
static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
{
unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
generic_handle_irq(intcs_evt2irq(evtcodeas));
return IRQ_HANDLED;
}
#define PINTER0_PHYS 0xe69000a0
#define PINTER1_PHYS 0xe69000a4
#define PINTER0_VIRT IOMEM(0xe69000a0)
#define PINTER1_VIRT IOMEM(0xe69000a4)
#define PINTRR0 IOMEM(0xe69000d0)
#define PINTRR1 IOMEM(0xe69000d4)
#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0", \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1", \
INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
static struct irqaction sh73a0_pint0_cascade;
static struct irqaction sh73a0_pint1_cascade;
static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
{
unsigned long value = ioread32(rr) & ioread32(er);
int k;
for (k = 0; k < 32; k++) {
if (value & (1 << (31 - k))) {
generic_handle_irq(base_irq + k);
iowrite32(~(1 << (31 - k)), rr);
}
}
}
static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
{
pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
return IRQ_HANDLED;
}
static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
{
pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
return IRQ_HANDLED;
}
void __init sh73a0_init_irq(void)
{
void __iomem *gic_dist_base = IOMEM(0xf0001000);
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
register_intc_controller(&intcs_desc);
register_intc_controller(&intc_pint0_desc);
register_intc_controller(&intc_pint1_desc);
/* demux using INTEVTSA */
sh73a0_intcs_cascade.name = "INTCS cascade";
sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
sh73a0_intcs_cascade.dev_id = intevtsa;
setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
/* PINT pins are sanely tied to the GIC as SPI */
sh73a0_pint0_cascade.name = "PINT0 cascade";
sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
sh73a0_pint1_cascade.name = "PINT1 cascade";
sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
}

129
arch/arm/mach-shmobile/pm-r8a7740.c
View File

@ -1,129 +0,0 @@
/*
* r8a7740 power management support
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/console.h>
#include <linux/io.h>
#include <linux/suspend.h>
#include "common.h"
#include "pm-rmobile.h"
#define SYSC_BASE IOMEM(0xe6180000)
#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
static int r8a7740_pd_a3sm_suspend(void)
{
/*
* The A3SM domain contains the CPU core and therefore it should
* only be turned off if the CPU is not in use.
*/
return -EBUSY;
}
static int r8a7740_pd_a3sp_suspend(void)
{
/*
* Serial consoles make use of SCIF hardware located in A3SP,
* keep such power domain on if "no_console_suspend" is set.
*/
return console_suspend_enabled ? 0 : -EBUSY;
}
static int r8a7740_pd_d4_suspend(void)
{
/*
* The D4 domain contains the Coresight-ETM hardware block and
* therefore it should only be turned off if the debug module is
* not in use.
*/
return -EBUSY;
}
static struct rmobile_pm_domain r8a7740_pm_domains[] = {
{
.genpd.name = "A4LC",
.base = SYSC_BASE,
.bit_shift = 1,
}, {
.genpd.name = "A4MP",
.base = SYSC_BASE,
.bit_shift = 2,
}, {
.genpd.name = "D4",
.base = SYSC_BASE,
.bit_shift = 3,
.gov = &pm_domain_always_on_gov,
.suspend = r8a7740_pd_d4_suspend,
}, {
.genpd.name = "A4R",
.base = SYSC_BASE,
.bit_shift = 5,
}, {
.genpd.name = "A3RV",
.base = SYSC_BASE,
.bit_shift = 6,
}, {
.genpd.name = "A4S",
.base = SYSC_BASE,
.bit_shift = 10,
.no_debug = true,
}, {
.genpd.name = "A3SP",
.base = SYSC_BASE,
.bit_shift = 11,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = r8a7740_pd_a3sp_suspend,
}, {
.genpd.name = "A3SM",
.base = SYSC_BASE,
.bit_shift = 12,
.gov = &pm_domain_always_on_gov,
.suspend = r8a7740_pd_a3sm_suspend,
}, {
.genpd.name = "A3SG",
.base = SYSC_BASE,
.bit_shift = 13,
}, {
.genpd.name = "A4SU",
.base = SYSC_BASE,
.bit_shift = 20,
},
};
void __init r8a7740_init_pm_domains(void)
{
rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
pm_genpd_add_subdomain_names("A4R", "A3RV");
pm_genpd_add_subdomain_names("A4S", "A3SP");
pm_genpd_add_subdomain_names("A4S", "A3SM");
pm_genpd_add_subdomain_names("A4S", "A3SG");
}
#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
#ifdef CONFIG_SUSPEND
static int r8a7740_enter_suspend(suspend_state_t suspend_state)
{
cpu_do_idle();
return 0;
}
static void r8a7740_suspend_init(void)
{
shmobile_suspend_ops.enter = r8a7740_enter_suspend;
}
#else
static void r8a7740_suspend_init(void) {}
#endif
void __init r8a7740_pm_init(void)
{
r8a7740_suspend_init();
}

1
arch/arm/mach-shmobile/pm-r8a7779.c
View File

@ -83,7 +83,6 @@ static void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
{
struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
genpd->flags = GENPD_FLAG_PM_CLK;
pm_genpd_init(genpd, NULL, false);
genpd->dev_ops.active_wakeup = pd_active_wakeup;
genpd->power_off = pd_power_down;

49
arch/arm/mach-shmobile/pm-rmobile.c
View File

@ -34,6 +34,12 @@
#define PSTR_RETRIES 100
#define PSTR_DELAY_US 10
static inline
struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
{
return container_of(d, struct rmobile_pm_domain, genpd);
}
static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
{
struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
@ -42,7 +48,7 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
if (rmobile_pd->bit_shift == ~0)
return -EBUSY;
mask = 1 << rmobile_pd->bit_shift;
mask = BIT(rmobile_pd->bit_shift);
if (rmobile_pd->suspend) {
int ret = rmobile_pd->suspend();
@ -79,7 +85,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
if (rmobile_pd->bit_shift == ~0)
return 0;
mask = 1 << rmobile_pd->bit_shift;
mask = BIT(rmobile_pd->bit_shift);
if (__raw_readl(rmobile_pd->base + PSTR) & mask)
goto out;
@ -163,43 +169,6 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
__rmobile_pd_power_up(rmobile_pd, false);
}
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
void rmobile_init_domains(struct rmobile_pm_domain domains[], int num)
{
int j;
for (j = 0; j < num; j++)
rmobile_init_pm_domain(&domains[j]);
}
void rmobile_add_device_to_domain_td(const char *domain_name,
struct platform_device *pdev,
struct gpd_timing_data *td)
{
struct device *dev = &pdev->dev;
__pm_genpd_name_add_device(domain_name, dev, td);
}
void rmobile_add_devices_to_domains(struct pm_domain_device data[],
int size)
{
struct gpd_timing_data latencies = {
.stop_latency_ns = DEFAULT_DEV_LATENCY_NS,
.start_latency_ns = DEFAULT_DEV_LATENCY_NS,
.save_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
.restore_state_latency_ns = DEFAULT_DEV_LATENCY_NS,
};
int j;
for (j = 0; j < size; j++)
rmobile_add_device_to_domain_td(data[j].domain_name,
data[j].pdev, &latencies);
}
#else /* !CONFIG_ARCH_SHMOBILE_LEGACY */
static int rmobile_pd_suspend_busy(void)
{
/*
@ -430,5 +399,3 @@ static int __init rmobile_init_pm_domains(void)
}
core_initcall(rmobile_init_pm_domains);
#endif /* !CONFIG_ARCH_SHMOBILE_LEGACY */

30
arch/arm/mach-shmobile/pm-rmobile.h
View File

@ -26,39 +26,9 @@ struct rmobile_pm_domain {
bool no_debug;
};
static inline
struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
{
return container_of(d, struct rmobile_pm_domain, genpd);
}
struct pm_domain_device {
const char *domain_name;
struct platform_device *pdev;
};
#if defined(CONFIG_PM_RMOBILE) && defined(CONFIG_ARCH_SHMOBILE_LEGACY)
extern void rmobile_init_domains(struct rmobile_pm_domain domains[], int num);
extern void rmobile_add_device_to_domain_td(const char *domain_name,
struct platform_device *pdev,
struct gpd_timing_data *td);
static inline void rmobile_add_device_to_domain(const char *domain_name,
struct platform_device *pdev)
{
rmobile_add_device_to_domain_td(domain_name, pdev, NULL);
}
extern void rmobile_add_devices_to_domains(struct pm_domain_device data[],
int size);
#else
#define rmobile_init_domains(domains, num) do { } while (0)
#define rmobile_add_device_to_domain_td(name, pdev, td) do { } while (0)
#define rmobile_add_device_to_domain(name, pdev) do { } while (0)
static inline void rmobile_add_devices_to_domains(struct pm_domain_device d[],
int size) {}
#endif /* CONFIG_PM_RMOBILE */
#endif /* PM_RMOBILE_H */

32
arch/arm/mach-shmobile/pm-sh73a0.c
View File

@ -1,32 +0,0 @@
/*
* sh73a0 Power management support
*
* Copyright (C) 2012 Bastian Hecht <hechtb+renesas@gmail.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/suspend.h>
#include "common.h"
#ifdef CONFIG_SUSPEND
static int sh73a0_enter_suspend(suspend_state_t suspend_state)
{
cpu_do_idle();
return 0;
}
static void sh73a0_suspend_init(void)
{
shmobile_suspend_ops.enter = sh73a0_enter_suspend;
}
#else
static void sh73a0_suspend_init(void) {}
#endif
void __init sh73a0_pm_init(void)
{
sh73a0_suspend_init();
}

58
arch/arm/mach-shmobile/r8a7740.h
View File

@ -1,58 +0,0 @@
/*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_R8A7740_H__
#define __ASM_R8A7740_H__
/*
* MD_CKx pin
*/
#define MD_CK2 (1 << 2)
#define MD_CK1 (1 << 1)
#define MD_CK0 (1 << 0)
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_SDHI2_TX,
SHDMA_SLAVE_FSIA_RX,
SHDMA_SLAVE_FSIA_TX,
SHDMA_SLAVE_FSIB_TX,
SHDMA_SLAVE_USBHS_TX,
SHDMA_SLAVE_USBHS_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
};
extern void r8a7740_meram_workaround(void);
extern void r8a7740_init_irq_of(void);
extern void r8a7740_map_io(void);
extern void r8a7740_add_early_devices(void);
extern void r8a7740_add_standard_devices(void);
extern void r8a7740_clock_init(u8 md_ck);
extern void r8a7740_pinmux_init(void);
extern void r8a7740_pm_init(void);
#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
extern void __init r8a7740_init_pm_domains(void);
#else
static inline void r8a7740_init_pm_domains(void) {}
#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
#endif /* __ASM_R8A7740_H__ */

678
arch/arm/mach-shmobile/setup-r8a7740.c
View File

@ -13,31 +13,19 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/platform_data/sh_ipmmu.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/hardware/cache-l2x0.h>
#include "common.h"
#include "dma-register.h"
#include "irqs.h"
#include "pm-rmobile.h"
#include "r8a7740.h"
static struct map_desc r8a7740_io_desc[] __initdata = {
/*
@ -64,613 +52,12 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
#endif
};
void __init r8a7740_map_io(void)
static void __init r8a7740_map_io(void)
{
debug_ll_io_init();
iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
}
/* PFC */
static const struct resource pfc_resources[] = {
DEFINE_RES_MEM(0xe6050000, 0x8000),
DEFINE_RES_MEM(0xe605800c, 0x0020),
};
void __init r8a7740_pinmux_init(void)
{
platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
ARRAY_SIZE(pfc_resources));
}
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
};
static struct resource irqpin0_resources[] = {
DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
};
static struct platform_device irqpin0_device = {
.name = "renesas_intc_irqpin",
.id = 0,
.resource = irqpin0_resources,
.num_resources = ARRAY_SIZE(irqpin0_resources),
.dev = {
.platform_data = &irqpin0_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin1_platform_data = {
.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
};
static struct resource irqpin1_resources[] = {
DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
};
static struct platform_device irqpin1_device = {
.name = "renesas_intc_irqpin",
.id = 1,
.resource = irqpin1_resources,
.num_resources = ARRAY_SIZE(irqpin1_resources),
.dev = {
.platform_data = &irqpin1_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
};
static struct resource irqpin2_resources[] = {
DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
};
static struct platform_device irqpin2_device = {
.name = "renesas_intc_irqpin",
.id = 2,
.resource = irqpin2_resources,
.num_resources = ARRAY_SIZE(irqpin2_resources),
.dev = {
.platform_data = &irqpin2_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
};
static struct resource irqpin3_resources[] = {
DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
};
static struct platform_device irqpin3_device = {
.name = "renesas_intc_irqpin",
.id = 3,
.resource = irqpin3_resources,
.num_resources = ARRAY_SIZE(irqpin3_resources),
.dev = {
.platform_data = &irqpin3_platform_data,
},
};
/* SCIF */
#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
/* CMT */
static struct sh_timer_config cmt1_platform_data = {
.channels_mask = 0x3f,
};
static struct resource cmt1_resources[] = {
DEFINE_RES_MEM(0xe6138000, 0x170),
DEFINE_RES_IRQ(gic_spi(58)),
};
static struct platform_device cmt1_device = {
.name = "sh-cmt-48",
.id = 1,
.dev = {
.platform_data = &cmt1_platform_data,
},
.resource = cmt1_resources,
.num_resources = ARRAY_SIZE(cmt1_resources),
};
/* TMU */
static struct sh_timer_config tmu0_platform_data = {
.channels_mask = 7,
};
static struct resource tmu0_resources[] = {
DEFINE_RES_MEM(0xfff80000, 0x2c),
DEFINE_RES_IRQ(gic_spi(198)),
DEFINE_RES_IRQ(gic_spi(199)),
DEFINE_RES_IRQ(gic_spi(200)),
};
static struct platform_device tmu0_device = {
.name = "sh-tmu",
.id = 0,
.dev = {
.platform_data = &tmu0_platform_data,
},
.resource = tmu0_resources,
.num_resources = ARRAY_SIZE(tmu0_resources),
};
/* IPMMUI (an IPMMU module for ICB/LMB) */
static struct resource ipmmu_resources[] = {
[0] = {
.name = "IPMMUI",
.start = 0xfe951000,
.end = 0xfe9510ff,
.flags = IORESOURCE_MEM,
},
};
static const char * const ipmmu_dev_names[] = {
"sh_mobile_lcdc_fb.0",
"sh_mobile_lcdc_fb.1",
"sh_mobile_ceu.0",
};
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
.dev_names = ipmmu_dev_names,
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
};
static struct platform_device ipmmu_device = {
.name = "ipmmu",
.id = -1,
.dev = {
.platform_data = &ipmmu_platform_data,
},
.resource = ipmmu_resources,
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct platform_device *r8a7740_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&scif7_device,
&scif8_device,
&irqpin0_device,
&irqpin1_device,
&irqpin2_device,
&irqpin3_device,
&tmu0_device,
&ipmmu_device,
&cmt1_device,
};
/* DMA */
static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc1,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xe6850030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xc2,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xe6860030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc9,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xe6860030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xca,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xe6870030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xcd,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xe6870030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xce,
}, {
.slave_id = SHDMA_SLAVE_FSIA_TX,
.addr = 0xfe1f0024,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb1,
}, {
.slave_id = SHDMA_SLAVE_FSIA_RX,
.addr = 0xfe1f0020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xb2,
}, {
.slave_id = SHDMA_SLAVE_FSIB_TX,
.addr = 0xfe1f0064,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xb5,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
.addr = 0xe6bd0034,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd1,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
.addr = 0xe6bd0034,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd2,
},
};
#define DMA_CHANNEL(a, b, c) \
{ \
.offset = a, \
.dmars = b, \
.dmars_bit = c, \
.chclr_offset = (0x220 - 0x20) + a \
}
static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
DMA_CHANNEL(0x00, 0, 0),
DMA_CHANNEL(0x10, 0, 8),
DMA_CHANNEL(0x20, 4, 0),
DMA_CHANNEL(0x30, 4, 8),
DMA_CHANNEL(0x50, 8, 0),
DMA_CHANNEL(0x60, 8, 8),
};
static struct sh_dmae_pdata dma_platform_data = {
.slave = r8a7740_dmae_slaves,
.slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
.channel = r8a7740_dmae_channels,
.channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
};
/* Resource order important! */
static struct resource r8a7740_dmae0_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe008020,
.end = 0xfe00828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe009000,
.end = 0xfe00900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = gic_spi(34),
.end = gic_spi(34),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = gic_spi(28),
.end = gic_spi(33),
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource r8a7740_dmae1_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe018020,
.end = 0xfe01828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe019000,
.end = 0xfe01900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = gic_spi(41),
.end = gic_spi(41),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = gic_spi(35),
.end = gic_spi(40),
.flags = IORESOURCE_IRQ,
},
};
/* Resource order important! */
static struct resource r8a7740_dmae2_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xfe028020,
.end = 0xfe02828f,
.flags = IORESOURCE_MEM,
},
{
/* DMARSx */
.start = 0xfe029000,
.end = 0xfe02900b,
.flags = IORESOURCE_MEM,
},
{
.name = "error_irq",
.start = gic_spi(48),
.end = gic_spi(48),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = gic_spi(42),
.end = gic_spi(47),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dma0_device = {
.name = "sh-dma-engine",
.id = 0,
.resource = r8a7740_dmae0_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma1_device = {
.name = "sh-dma-engine",
.id = 1,
.resource = r8a7740_dmae1_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device dma2_device = {
.name = "sh-dma-engine",
.id = 2,
.resource = r8a7740_dmae2_resources,
.num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
.dev = {
.platform_data = &dma_platform_data,
},
};
/* USB-DMAC */
static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
{
.offset = 0,
}, {
.offset = 0x20,
},
};
static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
{
.slave_id = SHDMA_SLAVE_USBHS_TX,
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
}, {
.slave_id = SHDMA_SLAVE_USBHS_RX,
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
},
};
static struct sh_dmae_pdata usb_dma_platform_data = {
.slave = r8a7740_usb_dma_slaves,
.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
.channel = r8a7740_usb_dma_channels,
.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
.ts_low_shift = USBTS_LOW_SHIFT,
.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
.ts_high_shift = USBTS_HI_SHIFT,
.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
.ts_shift = dma_usbts_shift,
.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
.dmaor_init = DMAOR_DME,
.chcr_offset = 0x14,
.chcr_ie_bit = 1 << 5,
.dmaor_is_32bit = 1,
.needs_tend_set = 1,
.no_dmars = 1,
.slave_only = 1,
};
static struct resource r8a7740_usb_dma_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xe68a0020,
.end = 0xe68a0064 - 1,
.flags = IORESOURCE_MEM,
},
{
/* VCR/SWR/DMICR */
.start = 0xe68a0000,
.end = 0xe68a0014 - 1,
.flags = IORESOURCE_MEM,
},
{
/* IRQ for channels */
.start = gic_spi(49),
.end = gic_spi(49),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usb_dma_device = {
.name = "sh-dma-engine",
.id = 3,
.resource = r8a7740_usb_dma_resources,
.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
.dev = {
.platform_data = &usb_dma_platform_data,
},
};
/* I2C */
static struct resource i2c0_resources[] = {
[0] = {
.name = "IIC0",
.start = 0xfff20000,
.end = 0xfff20425 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(201),
.end = gic_spi(204),
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c1_resources[] = {
[0] = {
.name = "IIC1",
.start = 0xe6c20000,
.end = 0xe6c20425 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(70), /* IIC1_ALI1 */
.end = gic_spi(73), /* IIC1_DTEI1 */
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c0_device = {
.name = "i2c-sh_mobile",
.id = 0,
.resource = i2c0_resources,
.num_resources = ARRAY_SIZE(i2c0_resources),
};
static struct platform_device i2c1_device = {
.name = "i2c-sh_mobile",
.id = 1,
.resource = i2c1_resources,
.num_resources = ARRAY_SIZE(i2c1_resources),
};
static struct resource pmu_resources[] = {
[0] = {
.start = gic_spi(83),
.end = gic_spi(83),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pmu_device = {
.name = "armv7-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
static struct platform_device *r8a7740_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
&dma0_device,
&dma1_device,
&dma2_device,
&usb_dma_device,
&pmu_device,
};
/*
* r8a7740 chip has lasting errata on MERAM buffer.
* this is work-around for it.
@ -678,7 +65,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
* "Media RAM (MERAM)" on r8a7740 documentation
*/
#define MEBUFCNTR 0xFE950098
void __init r8a7740_meram_workaround(void)
static void __init r8a7740_meram_workaround(void)
{
void __iomem *reg;
@ -689,70 +76,13 @@ void __init r8a7740_meram_workaround(void)
}
}
void __init r8a7740_add_standard_devices(void)
{
static struct pm_domain_device domain_devices[] __initdata = {
{ "A4R", &tmu0_device },
{ "A4R", &i2c0_device },
{ "A4S", &irqpin0_device },
{ "A4S", &irqpin1_device },
{ "A4S", &irqpin2_device },
{ "A4S", &irqpin3_device },
{ "A3SP", &scif0_device },
{ "A3SP", &scif1_device },
{ "A3SP", &scif2_device },
{ "A3SP", &scif3_device },
{ "A3SP", &scif4_device },
{ "A3SP", &scif5_device },
{ "A3SP", &scif6_device },
{ "A3SP", &scif7_device },
{ "A3SP", &scif8_device },
{ "A3SP", &i2c1_device },
{ "A3SP", &ipmmu_device },
{ "A3SP", &dma0_device },
{ "A3SP", &dma1_device },
{ "A3SP", &dma2_device },
{ "A3SP", &usb_dma_device },
};
r8a7740_init_pm_domains();
/* add devices */
platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
platform_add_devices(r8a7740_late_devices,
ARRAY_SIZE(r8a7740_late_devices));
/* add devices to PM domain */
rmobile_add_devices_to_domains(domain_devices,
ARRAY_SIZE(domain_devices));
}
void __init r8a7740_add_early_devices(void)
{
early_platform_add_devices(r8a7740_early_devices,
ARRAY_SIZE(r8a7740_early_devices));
/* setup early console here as well */
shmobile_setup_console();
}
#ifdef CONFIG_USE_OF
void __init r8a7740_init_irq_of(void)
static void __init r8a7740_init_irq_of(void)
{
void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
gic_init(0, 29, gic_dist_base, gic_cpu_base);
#else
irqchip_init();
#endif
/* route signals to GIC */
iowrite32(0x0, pfc_inta_ctrl);
@ -800,5 +130,3 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
.init_late = shmobile_init_late,
.dt_compat = r8a7740_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

2
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -128,9 +128,7 @@ void __init rcar_gen2_timer_init(void)
#endif /* CONFIG_ARM_ARCH_TIMER */
rcar_gen2_clocks_init(mode);
#ifdef CONFIG_ARCH_SHMOBILE_MULTI
clocksource_of_init();
#endif
}
struct memory_reserve_config {

739
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -18,28 +18,17 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/i2c/i2c-sh_mobile.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <linux/platform_data/sh_ipmmu.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
#include "dma-register.h"
#include "intc.h"
#include "irqs.h"
#include "sh73a0.h"
static struct map_desc sh73a0_io_desc[] __initdata = {
@ -54,737 +43,12 @@ static struct map_desc sh73a0_io_desc[] __initdata = {
},
};
void __init sh73a0_map_io(void)
static void __init sh73a0_map_io(void)
{
debug_ll_io_init();
iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
}
/* PFC */
static struct resource pfc_resources[] __initdata = {
DEFINE_RES_MEM(0xe6050000, 0x8000),
DEFINE_RES_MEM(0xe605801c, 0x000c),
};
void __init sh73a0_pinmux_init(void)
{
platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
ARRAY_SIZE(pfc_resources));
}
/* SCIF */
#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
static struct plat_sci_port scif##index##_platform_data = { \
.type = scif_type, \
.flags = UPF_BOOT_AUTOCONF, \
.scscr = SCSCR_RE | SCSCR_TE, \
}; \
\
static struct resource scif##index##_resources[] = { \
DEFINE_RES_MEM(baseaddr, 0x100), \
DEFINE_RES_IRQ(irq), \
}; \
\
static struct platform_device scif##index##_device = { \
.name = "sh-sci", \
.id = index, \
.resource = scif##index##_resources, \
.num_resources = ARRAY_SIZE(scif##index##_resources), \
.dev = { \
.platform_data = &scif##index##_platform_data, \
}, \
}
SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
static struct sh_timer_config cmt1_platform_data = {
.channels_mask = 0x3f,
};
static struct resource cmt1_resources[] = {
DEFINE_RES_MEM(0xe6138000, 0x200),
DEFINE_RES_IRQ(gic_spi(65)),
};
static struct platform_device cmt1_device = {
.name = "sh-cmt-48",
.id = 1,
.dev = {
.platform_data = &cmt1_platform_data,
},
.resource = cmt1_resources,
.num_resources = ARRAY_SIZE(cmt1_resources),
};
/* TMU */
static struct sh_timer_config tmu0_platform_data = {
.channels_mask = 7,
};
static struct resource tmu0_resources[] = {
DEFINE_RES_MEM(0xfff60000, 0x2c),
DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
};
static struct platform_device tmu0_device = {
.name = "sh-tmu",
.id = 0,
.dev = {
.platform_data = &tmu0_platform_data,
},
.resource = tmu0_resources,
.num_resources = ARRAY_SIZE(tmu0_resources),
};
static struct resource i2c0_resources[] = {
[0] = DEFINE_RES_MEM(0xe6820000, 0x426),
[1] = {
.start = gic_spi(167),
.end = gic_spi(170),
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c1_resources[] = {
[0] = DEFINE_RES_MEM(0xe6822000, 0x426),
[1] = {
.start = gic_spi(51),
.end = gic_spi(54),
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c2_resources[] = {
[0] = DEFINE_RES_MEM(0xe6824000, 0x426),
[1] = {
.start = gic_spi(171),
.end = gic_spi(174),
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c3_resources[] = {
[0] = DEFINE_RES_MEM(0xe6826000, 0x426),
[1] = {
.start = gic_spi(183),
.end = gic_spi(186),
.flags = IORESOURCE_IRQ,
},
};
static struct resource i2c4_resources[] = {
[0] = DEFINE_RES_MEM(0xe6828000, 0x426),
[1] = {
.start = gic_spi(187),
.end = gic_spi(190),
.flags = IORESOURCE_IRQ,
},
};
static struct i2c_sh_mobile_platform_data i2c_platform_data = {
.clks_per_count = 2,
};
static struct platform_device i2c0_device = {
.name = "i2c-sh_mobile",
.id = 0,
.resource = i2c0_resources,
.num_resources = ARRAY_SIZE(i2c0_resources),
.dev = {
.platform_data = &i2c_platform_data,
},
};
static struct platform_device i2c1_device = {
.name = "i2c-sh_mobile",
.id = 1,
.resource = i2c1_resources,
.num_resources = ARRAY_SIZE(i2c1_resources),
.dev = {
.platform_data = &i2c_platform_data,
},
};
static struct platform_device i2c2_device = {
.name = "i2c-sh_mobile",
.id = 2,
.resource = i2c2_resources,
.num_resources = ARRAY_SIZE(i2c2_resources),
.dev = {
.platform_data = &i2c_platform_data,
},
};
static struct platform_device i2c3_device = {
.name = "i2c-sh_mobile",
.id = 3,
.resource = i2c3_resources,
.num_resources = ARRAY_SIZE(i2c3_resources),
.dev = {
.platform_data = &i2c_platform_data,
},
};
static struct platform_device i2c4_device = {
.name = "i2c-sh_mobile",
.id = 4,
.resource = i2c4_resources,
.num_resources = ARRAY_SIZE(i2c4_resources),
.dev = {
.platform_data = &i2c_platform_data,
},
};
static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
{
.slave_id = SHDMA_SLAVE_SCIF0_TX,
.addr = 0xe6c40020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x21,
}, {
.slave_id = SHDMA_SLAVE_SCIF0_RX,
.addr = 0xe6c40024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x22,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_TX,
.addr = 0xe6c50020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x25,
}, {
.slave_id = SHDMA_SLAVE_SCIF1_RX,
.addr = 0xe6c50024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x26,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_TX,
.addr = 0xe6c60020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x29,
}, {
.slave_id = SHDMA_SLAVE_SCIF2_RX,
.addr = 0xe6c60024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2a,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_TX,
.addr = 0xe6c70020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x2d,
}, {
.slave_id = SHDMA_SLAVE_SCIF3_RX,
.addr = 0xe6c70024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x2e,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_TX,
.addr = 0xe6c80020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x39,
}, {
.slave_id = SHDMA_SLAVE_SCIF4_RX,
.addr = 0xe6c80024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3a,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_TX,
.addr = 0xe6cb0020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x35,
}, {
.slave_id = SHDMA_SLAVE_SCIF5_RX,
.addr = 0xe6cb0024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x36,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_TX,
.addr = 0xe6cc0020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x1d,
}, {
.slave_id = SHDMA_SLAVE_SCIF6_RX,
.addr = 0xe6cc0024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x1e,
}, {
.slave_id = SHDMA_SLAVE_SCIF7_TX,
.addr = 0xe6cd0020,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x19,
}, {
.slave_id = SHDMA_SLAVE_SCIF7_RX,
.addr = 0xe6cd0024,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x1a,
}, {
.slave_id = SHDMA_SLAVE_SCIF8_TX,
.addr = 0xe6c30040,
.chcr = CHCR_TX(XMIT_SZ_8BIT),
.mid_rid = 0x3d,
}, {
.slave_id = SHDMA_SLAVE_SCIF8_RX,
.addr = 0xe6c30060,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3e,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xee100030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc1,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_RX,
.addr = 0xee100030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xc2,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_TX,
.addr = 0xee120030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xc9,
}, {
.slave_id = SHDMA_SLAVE_SDHI1_RX,
.addr = 0xee120030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xca,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_TX,
.addr = 0xee140030,
.chcr = CHCR_TX(XMIT_SZ_16BIT),
.mid_rid = 0xcd,
}, {
.slave_id = SHDMA_SLAVE_SDHI2_RX,
.addr = 0xee140030,
.chcr = CHCR_RX(XMIT_SZ_16BIT),
.mid_rid = 0xce,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
.addr = 0xe6bd0034,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd1,
}, {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
.addr = 0xe6bd0034,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd2,
},
};
#define DMAE_CHANNEL(_offset) \
{ \
.offset = _offset - 0x20, \
.dmars = _offset - 0x20 + 0x40, \
}
static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
DMAE_CHANNEL(0x8000),
DMAE_CHANNEL(0x8080),
DMAE_CHANNEL(0x8100),
DMAE_CHANNEL(0x8180),
DMAE_CHANNEL(0x8200),
DMAE_CHANNEL(0x8280),
DMAE_CHANNEL(0x8300),
DMAE_CHANNEL(0x8380),
DMAE_CHANNEL(0x8400),
DMAE_CHANNEL(0x8480),
DMAE_CHANNEL(0x8500),
DMAE_CHANNEL(0x8580),
DMAE_CHANNEL(0x8600),
DMAE_CHANNEL(0x8680),
DMAE_CHANNEL(0x8700),
DMAE_CHANNEL(0x8780),
DMAE_CHANNEL(0x8800),
DMAE_CHANNEL(0x8880),
DMAE_CHANNEL(0x8900),
DMAE_CHANNEL(0x8980),
};
static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
.slave = sh73a0_dmae_slaves,
.slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
.channel = sh73a0_dmae_channels,
.channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
};
static struct resource sh73a0_dmae_resources[] = {
DEFINE_RES_MEM(0xfe000020, 0x89e0),
{
.name = "error_irq",
.start = gic_spi(129),
.end = gic_spi(129),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-19 */
.start = gic_spi(109),
.end = gic_spi(128),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device dma0_device = {
.name = "sh-dma-engine",
.id = 0,
.resource = sh73a0_dmae_resources,
.num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
.dev = {
.platform_data = &sh73a0_dmae_platform_data,
},
};
/* MPDMAC */
static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
{
.slave_id = SHDMA_SLAVE_FSI2A_RX,
.addr = 0xec230020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xd6, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2A_TX,
.addr = 0xec230024,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd5, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2C_RX,
.addr = 0xec230060,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0xda, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2C_TX,
.addr = 0xec230064,
.chcr = CHCR_TX(XMIT_SZ_32BIT),
.mid_rid = 0xd9, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2B_RX,
.addr = 0xec240020,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x8e, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2B_TX,
.addr = 0xec240024,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x8d, /* CHECK ME */
}, {
.slave_id = SHDMA_SLAVE_FSI2D_RX,
.addr = 0xec240060,
.chcr = CHCR_RX(XMIT_SZ_32BIT),
.mid_rid = 0x9a, /* CHECK ME */
},
};
#define MPDMA_CHANNEL(a, b, c) \
{ \
.offset = a, \
.dmars = b, \
.dmars_bit = c, \
.chclr_offset = (0x220 - 0x20) + a \
}
static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
MPDMA_CHANNEL(0x00, 0, 0),
MPDMA_CHANNEL(0x10, 0, 8),
MPDMA_CHANNEL(0x20, 4, 0),
MPDMA_CHANNEL(0x30, 4, 8),
MPDMA_CHANNEL(0x50, 8, 0),
MPDMA_CHANNEL(0x70, 8, 8),
};
static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
.slave = sh73a0_mpdma_slaves,
.slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
.channel = sh73a0_mpdma_channels,
.channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
.ts_low_shift = TS_LOW_SHIFT,
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
.ts_high_shift = TS_HI_SHIFT,
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
.ts_shift = dma_ts_shift,
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
.dmaor_init = DMAOR_DME,
.chclr_present = 1,
};
/* Resource order important! */
static struct resource sh73a0_mpdma_resources[] = {
/* Channel registers and DMAOR */
DEFINE_RES_MEM(0xec618020, 0x270),
/* DMARSx */
DEFINE_RES_MEM(0xec619000, 0xc),
{
.name = "error_irq",
.start = gic_spi(181),
.end = gic_spi(181),
.flags = IORESOURCE_IRQ,
},
{
/* IRQ for channels 0-5 */
.start = gic_spi(175),
.end = gic_spi(180),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mpdma0_device = {
.name = "sh-dma-engine",
.id = 1,
.resource = sh73a0_mpdma_resources,
.num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
.dev = {
.platform_data = &sh73a0_mpdma_platform_data,
},
};
static struct resource pmu_resources[] = {
[0] = {
.start = gic_spi(55),
.end = gic_spi(55),
.flags = IORESOURCE_IRQ,
},
[1] = {
.start = gic_spi(56),
.end = gic_spi(56),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device pmu_device = {
.name = "armv7-pmu",
.id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
/* an IPMMU module for ICB */
static struct resource ipmmu_resources[] = {
DEFINE_RES_MEM(0xfe951000, 0x100),
};
static const char * const ipmmu_dev_names[] = {
"sh_mobile_lcdc_fb.0",
};
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
.dev_names = ipmmu_dev_names,
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
};
static struct platform_device ipmmu_device = {
.name = "ipmmu",
.id = -1,
.dev = {
.platform_data = &ipmmu_platform_data,
},
.resource = ipmmu_resources,
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
.control_parent = true,
};
static struct resource irqpin0_resources[] = {
DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
};
static struct platform_device irqpin0_device = {
.name = "renesas_intc_irqpin",
.id = 0,
.resource = irqpin0_resources,
.num_resources = ARRAY_SIZE(irqpin0_resources),
.dev = {
.platform_data = &irqpin0_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin1_platform_data = {
.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
.control_parent = true, /* Disable spurious IRQ10 */
};
static struct resource irqpin1_resources[] = {
DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
};
static struct platform_device irqpin1_device = {
.name = "renesas_intc_irqpin",
.id = 1,
.resource = irqpin1_resources,
.num_resources = ARRAY_SIZE(irqpin1_resources),
.dev = {
.platform_data = &irqpin1_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
.control_parent = true,
};
static struct resource irqpin2_resources[] = {
DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
};
static struct platform_device irqpin2_device = {
.name = "renesas_intc_irqpin",
.id = 2,
.resource = irqpin2_resources,
.num_resources = ARRAY_SIZE(irqpin2_resources),
.dev = {
.platform_data = &irqpin2_platform_data,
},
};
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
.control_parent = true,
};
static struct resource irqpin3_resources[] = {
DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
};
static struct platform_device irqpin3_device = {
.name = "renesas_intc_irqpin",
.id = 3,
.resource = irqpin3_resources,
.num_resources = ARRAY_SIZE(irqpin3_resources),
.dev = {
.platform_data = &irqpin3_platform_data,
},
};
static struct platform_device *sh73a0_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
&scif3_device,
&scif4_device,
&scif5_device,
&scif6_device,
&scif7_device,
&scif8_device,
&tmu0_device,
&ipmmu_device,
&cmt1_device,
};
static struct platform_device *sh73a0_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
&i2c2_device,
&i2c3_device,
&i2c4_device,
&dma0_device,
&mpdma0_device,
&pmu_device,
&irqpin0_device,
&irqpin1_device,
&irqpin2_device,
&irqpin3_device,
};
#define SRCR2 IOMEM(0xe61580b0)
void __init sh73a0_add_standard_devices(void)
{
/* Clear software reset bit on SY-DMAC module */
__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
platform_add_devices(sh73a0_late_devices,
ARRAY_SIZE(sh73a0_late_devices));
}
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init __weak sh73a0_register_twd(void) { }
void __init sh73a0_earlytimer_init(void)
{
shmobile_init_delay();
#ifndef CONFIG_COMMON_CLK
sh73a0_clock_init();
#endif
shmobile_earlytimer_init();
sh73a0_register_twd();
}
void __init sh73a0_add_early_devices(void)
{
early_platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
/* setup early console here as well */
shmobile_setup_console();
}
#ifdef CONFIG_USE_OF
static void __init sh73a0_generic_init(void)
{
#ifdef CONFIG_CACHE_L2X0
@ -807,4 +71,3 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.init_late = shmobile_init_late,
.dt_compat = sh73a0_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */

83
arch/arm/mach-shmobile/sh73a0.h
View File

@ -1,89 +1,6 @@
#ifndef __ASM_SH73A0_H__
#define __ASM_SH73A0_H__
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SCIF0_TX,
SHDMA_SLAVE_SCIF0_RX,
SHDMA_SLAVE_SCIF1_TX,
SHDMA_SLAVE_SCIF1_RX,
SHDMA_SLAVE_SCIF2_TX,
SHDMA_SLAVE_SCIF2_RX,
SHDMA_SLAVE_SCIF3_TX,
SHDMA_SLAVE_SCIF3_RX,
SHDMA_SLAVE_SCIF4_TX,
SHDMA_SLAVE_SCIF4_RX,
SHDMA_SLAVE_SCIF5_TX,
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
SHDMA_SLAVE_SCIF7_TX,
SHDMA_SLAVE_SCIF7_RX,
SHDMA_SLAVE_SCIF8_TX,
SHDMA_SLAVE_SCIF8_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI1_TX,
SHDMA_SLAVE_SDHI1_RX,
SHDMA_SLAVE_SDHI2_TX,
SHDMA_SLAVE_SDHI2_RX,
SHDMA_SLAVE_MMCIF_TX,
SHDMA_SLAVE_MMCIF_RX,
SHDMA_SLAVE_FSI2A_TX,
SHDMA_SLAVE_FSI2A_RX,
SHDMA_SLAVE_FSI2B_TX,
SHDMA_SLAVE_FSI2B_RX,
SHDMA_SLAVE_FSI2C_TX,
SHDMA_SLAVE_FSI2C_RX,
SHDMA_SLAVE_FSI2D_RX,
};
/*
* SH73A0 IRQ LOCATION TABLE
*
* 416 -----------------------------------------
* IRQ0-IRQ15
* 431 -----------------------------------------
* ...
* 448 -----------------------------------------
* sh73a0-intcs
* sh73a0-intca-irq-pins
* 680 -----------------------------------------
* ...
* 700 -----------------------------------------
* sh73a0-pint0
* 731 -----------------------------------------
* 732 -----------------------------------------
* sh73a0-pint1
* 739 -----------------------------------------
* ...
* 800 -----------------------------------------
* IRQ16-IRQ31
* 815 -----------------------------------------
* ...
* 928 -----------------------------------------
* sh73a0-intca-irq-pins
* 943 -----------------------------------------
*/
/* PINT interrupts are located at Linux IRQ 700 and up */
#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
extern void sh73a0_init_irq(void);
extern void sh73a0_init_irq_dt(void);
extern void sh73a0_map_io(void);
extern void sh73a0_earlytimer_init(void);
extern void sh73a0_add_early_devices(void);
extern void sh73a0_add_standard_devices(void);
extern void sh73a0_clock_init(void);
extern void sh73a0_pinmux_init(void);
extern void sh73a0_pm_init(void);
extern struct clk sh73a0_extal1_clk;
extern struct clk sh73a0_extal2_clk;
extern struct clk sh73a0_extcki_clk;
extern struct clk sh73a0_extalr_clk;
extern struct smp_operations sh73a0_smp_ops;
#endif /* __ASM_SH73A0_H__ */

8
arch/arm/mach-shmobile/smp-sh73a0.c
View File

@ -33,14 +33,6 @@
#define SH73A0_SCU_BASE 0xf0000000
#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM)
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
void __init sh73a0_register_twd(void)
{
twd_local_timer_register(&twd_local_timer);
}
#endif
static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned int lcpu = cpu_logical_map(cpu);

12
arch/arm/mach-shmobile/timer.c
View File

@ -70,18 +70,6 @@ void __init shmobile_init_delay(void)
if (!max_freq)
return;
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
/* Non-multiplatform r8a73a4 SoC cannot use arch timer due
* to GIC being initialized from C and arch timer via DT */
if (of_machine_is_compatible("renesas,r8a73a4"))
has_arch_timer = false;
/* Non-multiplatform r8a7790 SoC cannot use arch timer due
* to GIC being initialized from C and arch timer via DT */
if (of_machine_is_compatible("renesas,r8a7790"))
has_arch_timer = false;
#endif
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
if (is_a7_a8_a9)
shmobile_setup_delay_hz(max_freq, 1, 3);