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serial: pch_uart: Make port type explicit 

It used to be a gap in port definitions after PORT_MAX_8250. Since the
new drivers are coming the gap become shorter and shorter until the
commit a2d6a987bf ("serial: 8250: Add new port type for TI DA8xx/66AK2x")
completely removed it.

So, while type here is just a formality, make things a little bit more
explicit for this driver and move port types to UAPI header. Note,
it uses two types for now.

Fixes: fddceb8b53 ("tty: 8250: Add 64byte UART support for FSL platforms")
Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko 2017-08-22 16:58:20 +03:00 committed by Greg Kroah-Hartman
parent aef3ad103a
commit 63e8d4394a
2 changed files with 19 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/tty/serial/pch_uart.c
View File

@ -46,11 +46,6 @@ enum {
PCH_UART_HANDLED_LS_INT_SHIFT, PCH_UART_HANDLED_LS_INT_SHIFT,
}; };
enum {
PCH_UART_8LINE,
PCH_UART_2LINE,
};
#define PCH_UART_DRIVER_DEVICE "ttyPCH" #define PCH_UART_DRIVER_DEVICE "ttyPCH"
/* Set the max number of UART port /* Set the max number of UART port
@ -267,7 +262,7 @@ struct eg20t_port {
/** /**
* struct pch_uart_driver_data - private data structure for UART-DMA * struct pch_uart_driver_data - private data structure for UART-DMA
* @port_type: The number of DMA channel * @port_type: The type of UART port
* @line_no: UART port line number (0, 1, 2...) * @line_no: UART port line number (0, 1, 2...)
*/ */
struct pch_uart_driver_data { struct pch_uart_driver_data {
@ -290,17 +285,17 @@ enum pch_uart_num_t {
}; };
static struct pch_uart_driver_data drv_dat[] = { static struct pch_uart_driver_data drv_dat[] = {
[pch_et20t_uart0] = {PCH_UART_8LINE, 0}, [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
[pch_et20t_uart1] = {PCH_UART_2LINE, 1}, [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
[pch_et20t_uart2] = {PCH_UART_2LINE, 2}, [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
[pch_et20t_uart3] = {PCH_UART_2LINE, 3}, [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
[pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
[pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
[pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
[pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
[pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
}; };
#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
@ -1777,10 +1772,10 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
goto init_port_free_txbuf; goto init_port_free_txbuf;
switch (port_type) { switch (port_type) {
case PORT_UNKNOWN: case PORT_PCH_8LINE:
fifosize = 256; /* EG20T/ML7213: UART0 */ fifosize = 256; /* EG20T/ML7213: UART0 */
break; break;
case PORT_8250: case PORT_PCH_2LINE:
fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
break; break;
default: default:
@ -1804,7 +1799,7 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
priv->fifo_size = fifosize; priv->fifo_size = fifosize;
priv->uartclk = pch_uart_get_uartclk(); priv->uartclk = pch_uart_get_uartclk();
priv->port_type = PORT_MAX_8250 + port_type + 1; priv->port_type = port_type;
priv->port.dev = &pdev->dev; priv->port.dev = &pdev->dev;
priv->port.iobase = iobase; priv->port.iobase = iobase;
priv->port.membase = NULL; priv->port.membase = NULL;

5
include/uapi/linux/serial_core.h
View File

@ -57,7 +57,6 @@
#define PORT_RT2880 29 /* Ralink RT2880 internal UART */ #define PORT_RT2880 29 /* Ralink RT2880 internal UART */
#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
#define PORT_DA830 31 /* TI DA8xx/66AK2x */ #define PORT_DA830 31 /* TI DA8xx/66AK2x */
#define PORT_MAX_8250 31 /* max port ID */
/* /*
* ARM specific type numbers. These are not currently guaranteed * ARM specific type numbers. These are not currently guaranteed
@ -77,6 +76,10 @@
#define PORT_SUNZILOG 38 #define PORT_SUNZILOG 38
#define PORT_SUNSAB 39 #define PORT_SUNSAB 39
/* Intel EG20 */
#define PORT_PCH_8LINE 44
#define PORT_PCH_2LINE 45
/* DEC */ /* DEC */
#define PORT_DZ 46 #define PORT_DZ 46
#define PORT_ZS 47 #define PORT_ZS 47