mailbox: bcm-pdc: Performance improvements
Three changes to improve performance in the PDC driver: - disable and reenable interrupts while the interrupt handler is running - update rxin and txin descriptor indexes more efficiently - group receive descriptor context into a structure and keep context in a single array rather than five to improve locality of reference Signed-off-by: Rob Rice <rob.rice@broadcom.com> Reviewed-by: Andy Gospodarek <gospo@broadcom.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Rob Rice
Jassi Brar
parent
38ed49ed4a
commit
63bb50bdb9
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@ -260,6 +260,27 @@ struct pdc_ring_alloc {
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u32 size; /* ring allocation size in bytes */
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};
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/*
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* context associated with a receive descriptor.
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* @rxp_ctx: opaque context associated with frame that starts at each
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* rx ring index.
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* @dst_sg: Scatterlist used to form reply frames beginning at a given ring
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* index. Retained in order to unmap each sg after reply is processed.
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* @rxin_numd: Number of rx descriptors associated with the message that starts
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* at a descriptor index. Not set for every index. For example,
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* if descriptor index i points to a scatterlist with 4 entries,
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* then the next three descriptor indexes don't have a value set.
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* @resp_hdr: Virtual address of buffer used to catch DMA rx status
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* @resp_hdr_daddr: physical address of DMA rx status buffer
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*/
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struct pdc_rx_ctx {
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void *rxp_ctx;
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struct scatterlist *dst_sg;
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u32 rxin_numd;
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void *resp_hdr;
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dma_addr_t resp_hdr_daddr;
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};
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/* PDC state structure */
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struct pdc_state {
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/* Index of the PDC whose state is in this structure instance */
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@ -377,11 +398,7 @@ struct pdc_state {
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/* Index of next rx descriptor to post. */
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u32 rxout;
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/*
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* opaque context associated with frame that starts at each
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* rx ring index.
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*/
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void *rxp_ctx[PDC_RING_ENTRIES];
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struct pdc_rx_ctx rx_ctx[PDC_RING_ENTRIES];
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/*
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* Scatterlists used to form request and reply frames beginning at a
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@ -389,18 +406,6 @@ struct pdc_state {
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* is processed
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*/
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struct scatterlist *src_sg[PDC_RING_ENTRIES];
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struct scatterlist *dst_sg[PDC_RING_ENTRIES];
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/*
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* Number of rx descriptors associated with the message that starts
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* at this descriptor index. Not set for every index. For example,
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* if descriptor index i points to a scatterlist with 4 entries, then
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* the next three descriptor indexes don't have a value set.
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*/
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u32 rxin_numd[PDC_RING_ENTRIES];
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void *resp_hdr[PDC_RING_ENTRIES];
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dma_addr_t resp_hdr_daddr[PDC_RING_ENTRIES];
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struct dentry *debugfs_stats; /* debug FS stats file for this PDC */
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@ -591,11 +596,11 @@ pdc_receive_one(struct pdc_state *pdcs)
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struct brcm_message mssg;
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u32 len, rx_status;
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u32 num_frags;
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int i;
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u8 *resp_hdr; /* virtual addr of start of resp message DMA header */
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u32 frags_rdy; /* number of fragments ready to read */
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u32 rx_idx; /* ring index of start of receive frame */
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dma_addr_t resp_hdr_daddr;
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struct pdc_rx_ctx *rx_ctx;
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mbc = &pdcs->mbc;
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chan = &mbc->chans[0];
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@ -607,7 +612,8 @@ pdc_receive_one(struct pdc_state *pdcs)
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* to read.
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*/
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frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost);
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if ((frags_rdy == 0) || (frags_rdy < pdcs->rxin_numd[pdcs->rxin]))
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if ((frags_rdy == 0) ||
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(frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd))
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/* No response ready */
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return -EAGAIN;
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@ -617,24 +623,23 @@ pdc_receive_one(struct pdc_state *pdcs)
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dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin],
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sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE);
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for (i = 0; i < num_frags; i++)
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pdcs->txin = NEXTTXD(pdcs->txin, pdcs->ntxpost);
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pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost;
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dev_dbg(dev, "PDC %u reclaimed %d tx descriptors",
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pdcs->pdc_idx, num_frags);
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rx_idx = pdcs->rxin;
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num_frags = pdcs->rxin_numd[rx_idx];
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rx_ctx = &pdcs->rx_ctx[rx_idx];
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num_frags = rx_ctx->rxin_numd;
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/* Return opaque context with result */
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mssg.ctx = pdcs->rxp_ctx[rx_idx];
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pdcs->rxp_ctx[rx_idx] = NULL;
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resp_hdr = pdcs->resp_hdr[rx_idx];
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resp_hdr_daddr = pdcs->resp_hdr_daddr[rx_idx];
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dma_unmap_sg(dev, pdcs->dst_sg[rx_idx],
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sg_nents(pdcs->dst_sg[rx_idx]), DMA_FROM_DEVICE);
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mssg.ctx = rx_ctx->rxp_ctx;
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rx_ctx->rxp_ctx = NULL;
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resp_hdr = rx_ctx->resp_hdr;
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resp_hdr_daddr = rx_ctx->resp_hdr_daddr;
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dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg),
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DMA_FROM_DEVICE);
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for (i = 0; i < num_frags; i++)
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pdcs->rxin = NEXTRXD(pdcs->rxin, pdcs->nrxpost);
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pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost;
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dev_dbg(dev, "PDC %u reclaimed %d rx descriptors",
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pdcs->pdc_idx, num_frags);
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@ -826,6 +831,7 @@ static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg,
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u32 rx_pkt_cnt = 1; /* Adding a single rx buffer */
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dma_addr_t daddr;
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void *vaddr;
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struct pdc_rx_ctx *rx_ctx;
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rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,
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pdcs->nrxpost);
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@ -849,15 +855,16 @@ static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg,
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/* This is always the first descriptor in the receive sequence */
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flags = D64_CTRL1_SOF;
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pdcs->rxin_numd[pdcs->rx_msg_start] = 1;
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pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1;
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if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))
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flags |= D64_CTRL1_EOT;
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pdcs->rxp_ctx[pdcs->rxout] = ctx;
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pdcs->dst_sg[pdcs->rxout] = dst_sg;
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pdcs->resp_hdr[pdcs->rxout] = vaddr;
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pdcs->resp_hdr_daddr[pdcs->rxout] = daddr;
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rx_ctx = &pdcs->rx_ctx[pdcs->rxout];
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rx_ctx->rxp_ctx = ctx;
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rx_ctx->dst_sg = dst_sg;
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rx_ctx->resp_hdr = vaddr;
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rx_ctx->resp_hdr_daddr = daddr;
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pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags);
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return PDC_SUCCESS;
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}
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@ -925,7 +932,7 @@ static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg)
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desc_w++;
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sg = sg_next(sg);
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}
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pdcs->rxin_numd[pdcs->rx_msg_start] += desc_w;
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pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w;
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return PDC_SUCCESS;
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}
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@ -954,6 +961,9 @@ static irqreturn_t pdc_irq_handler(int irq, void *data)
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/* Clear interrupt flags in device */
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iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);
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/* Disable interrupts until soft handler runs */
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iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
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/* Wakeup IRQ thread */
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if (likely(pdcs && (irq == pdcs->pdc_irq) &&
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(intstatus & PDC_INTMASK))) {
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@ -971,6 +981,9 @@ static void pdc_tasklet_cb(unsigned long data)
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rx_int = test_and_clear_bit(PDC_RCVINT_0, &pdcs->intstatus);
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if (likely(pdcs && rx_int))
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pdc_receive(pdcs);
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/* reenable interrupts */
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iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);
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}
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/**
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