hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

m32r: Convert m32700ut pld irq chip 

Convert the irq chips to the new functions and use proper flow
handlers. handle_level_irq is appropriate.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Thomas Gleixner 2011-01-19 17:41:51 +01:00
parent 364a9ba07b
commit 63b549b655
1 changed files with 20 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/m32r/platforms/m32700ut/setup.c
View File

@ -90,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
unsigned int pldirq; unsigned int pldirq;
pldirq = irq2pldirq(irq); pldirq = irq2pldirq(irq);
// disable_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq); port = pldirq2port(pldirq);
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
outw(data, port); outw(data, port);
@ -102,37 +101,28 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
unsigned int pldirq; unsigned int pldirq;
pldirq = irq2pldirq(irq); pldirq = irq2pldirq(irq);
// enable_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq); port = pldirq2port(pldirq);
data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
outw(data, port); outw(data, port);
} }
static void mask_and_ack_m32700ut_pld(unsigned int irq) static void mask_m32700ut_pld(struct irq_data *data)
{ {
disable_m32700ut_pld_irq(irq); disable_m32700ut_pld_irq(data->irq);
// mask_and_ack_m32700ut(M32R_IRQ_INT1);
} }
static void end_m32700ut_pld_irq(unsigned int irq) static void unmask_m32700ut_pld(struct irq_data *data)
{ {
enable_m32700ut_pld_irq(irq); enable_m32700ut_pld_irq(data->irq);
enable_m32700ut_irq(M32R_IRQ_INT1); enable_m32700ut_irq(M32R_IRQ_INT1);
} }
static unsigned int startup_m32700ut_pld_irq(unsigned int irq) static void shutdown_m32700ut_pld_irq(struct irq_data *data)
{
enable_m32700ut_pld_irq(irq);
return (0);
}
static void shutdown_m32700ut_pld_irq(unsigned int irq)
{ {
unsigned long port; unsigned long port;
unsigned int pldirq; unsigned int pldirq;
pldirq = irq2pldirq(irq); pldirq = irq2pldirq(data->irq);
// shutdown_m32700ut_irq(M32R_IRQ_INT1);
port = pldirq2port(pldirq); port = pldirq2port(pldirq);
outw(PLD_ICUCR_ILEVEL7, port); outw(PLD_ICUCR_ILEVEL7, port);
} }
@ -140,12 +130,9 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq)
static struct irq_chip m32700ut_pld_irq_type = static struct irq_chip m32700ut_pld_irq_type =
{ {
.name = "M32700UT-PLD-IRQ", .name = "M32700UT-PLD-IRQ",
.startup = startup_m32700ut_pld_irq, .irq_shutdown = shutdown_m32700ut_pld_irq,
.shutdown = shutdown_m32700ut_pld_irq, .irq_mask = mask_m32700ut_pld,
.enable = enable_m32700ut_pld_irq, .irq_unmask = unmask_m32700ut_pld,
.disable = disable_m32700ut_pld_irq,
.ack = mask_and_ack_m32700ut_pld,
.end = end_m32700ut_pld_irq
}; };
/* /*
@ -333,28 +320,33 @@ void __init init_IRQ(void)
#ifdef CONFIG_SERIAL_M32R_PLDSIO #ifdef CONFIG_SERIAL_M32R_PLDSIO
/* INT#1: SIO0 Receive on PLD */ /* INT#1: SIO0 Receive on PLD */
set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
/* INT#1: SIO0 Send on PLD */ /* INT#1: SIO0 Send on PLD */
set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
#endif /* CONFIG_SERIAL_M32R_PLDSIO */ #endif /* CONFIG_SERIAL_M32R_PLDSIO */
/* INT#1: CFC IREQ on PLD */ /* INT#1: CFC IREQ on PLD */
set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
/* INT#1: CFC Insert on PLD */ /* INT#1: CFC Insert on PLD */
set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
/* INT#1: CFC Eject on PLD */ /* INT#1: CFC Eject on PLD */
set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type); set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
handle_level_irq);
pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);