m32r: Convert m32700ut pld irq chip
Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Paul Mundt <lethal@linux-sh.org>
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@ -90,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// disable_m32700ut_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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@ -102,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// enable_m32700ut_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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}
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static void mask_and_ack_m32700ut_pld(unsigned int irq)
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static void mask_m32700ut_pld(struct irq_data *data)
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{
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disable_m32700ut_pld_irq(irq);
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// mask_and_ack_m32700ut(M32R_IRQ_INT1);
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disable_m32700ut_pld_irq(data->irq);
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}
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static void end_m32700ut_pld_irq(unsigned int irq)
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static void unmask_m32700ut_pld(struct irq_data *data)
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{
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enable_m32700ut_pld_irq(irq);
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enable_m32700ut_pld_irq(data->irq);
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enable_m32700ut_irq(M32R_IRQ_INT1);
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}
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static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
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{
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enable_m32700ut_pld_irq(irq);
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return (0);
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}
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static void shutdown_m32700ut_pld_irq(unsigned int irq)
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static void shutdown_m32700ut_pld_irq(struct irq_data *data)
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{
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unsigned long port;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// shutdown_m32700ut_irq(M32R_IRQ_INT1);
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pldirq = irq2pldirq(data->irq);
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port = pldirq2port(pldirq);
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outw(PLD_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_pld_irq_type =
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{
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.name = "M32700UT-PLD-IRQ",
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.startup = startup_m32700ut_pld_irq,
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.shutdown = shutdown_m32700ut_pld_irq,
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.enable = enable_m32700ut_pld_irq,
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.disable = disable_m32700ut_pld_irq,
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.ack = mask_and_ack_m32700ut_pld,
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.end = end_m32700ut_pld_irq
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.name = "M32700UT-PLD-IRQ",
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.irq_shutdown = shutdown_m32700ut_pld_irq,
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.irq_mask = mask_m32700ut_pld,
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.irq_unmask = unmask_m32700ut_pld,
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};
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/*
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@ -333,28 +320,33 @@ void __init init_IRQ(void)
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#ifdef CONFIG_SERIAL_M32R_PLDSIO
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/* INT#1: SIO0 Receive on PLD */
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set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type);
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set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
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handle_level_irq);
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pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
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disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
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/* INT#1: SIO0 Send on PLD */
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set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type);
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set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
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handle_level_irq);
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pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
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disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
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#endif /* CONFIG_SERIAL_M32R_PLDSIO */
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/* INT#1: CFC IREQ on PLD */
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set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type);
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set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
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handle_level_irq);
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pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
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/* INT#1: CFC Insert on PLD */
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set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type);
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set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
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handle_level_irq);
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pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
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/* INT#1: CFC Eject on PLD */
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set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type);
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set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
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handle_level_irq);
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pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
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