powerpc/64: Honor swiotlb limit in coherent allocations
FSL PCI cannot directly address the whole lower 4 GiB due to conflicts with PCICSRBAR and outbound windows, and thus max_direct_dma_addr is less than 4GiB. Honor that limit in dma_direct_alloc_coherent(). Note that setting the DMA mask to 31 bits is not an option, since many PCI drivers would fail if we reject 32-bit DMA in dma_supported(), and we have no control over the setting of coherent_dma_mask if dma_supported() returns true. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
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@ -15,6 +15,7 @@
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#include <asm/vio.h>
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#include <asm/vio.h>
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#include <asm/bug.h>
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#include <asm/bug.h>
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#include <asm/machdep.h>
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#include <asm/machdep.h>
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#include <asm/swiotlb.h>
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/*
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/*
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* Generic direct DMA implementation
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* Generic direct DMA implementation
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@ -25,6 +26,18 @@
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* default the offset is PCI_DRAM_OFFSET.
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* default the offset is PCI_DRAM_OFFSET.
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*/
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*/
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static u64 __maybe_unused get_pfn_limit(struct device *dev)
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{
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u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
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struct dev_archdata __maybe_unused *sd = &dev->archdata;
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#ifdef CONFIG_SWIOTLB
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if (sd->max_direct_dma_addr && sd->dma_ops == &swiotlb_dma_ops)
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pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
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#endif
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return pfn;
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}
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void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag,
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dma_addr_t *dma_handle, gfp_t flag,
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@ -40,7 +53,7 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
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#else
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#else
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struct page *page;
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struct page *page;
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int node = dev_to_node(dev);
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int node = dev_to_node(dev);
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u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
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u64 pfn = get_pfn_limit(dev);
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int zone;
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int zone;
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zone = dma_pfn_limit_to_zone(pfn);
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zone = dma_pfn_limit_to_zone(pfn);
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