arch/tile: common DMA code for the GXIO IORPC subsystem
The dma_queue support is used by both the mPipe (networking) and Trio (PCI) hardware shims on tilegx. This common code is selected when either of those drivers is built. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
44e5696710
commit
6369798037
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@ -3,3 +3,9 @@
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config TILE_GXIO
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bool
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depends on TILEGX
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# Support direct access to the common I/O DMA facility within the
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# TILE-Gx mPIPE and Trio hardware from kernel space.
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config TILE_GXIO_DMA
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bool
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select TILE_GXIO
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@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
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obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
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@ -0,0 +1,176 @@
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/io.h>
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#include <linux/atomic.h>
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#include <linux/module.h>
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#include <gxio/dma_queue.h>
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/* Wait for a memory read to complete. */
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#define wait_for_value(val) \
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__asm__ __volatile__("move %0, %0" :: "r"(val))
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/* The index is in the low 16. */
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#define DMA_QUEUE_INDEX_MASK ((1 << 16) - 1)
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/*
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* The hardware descriptor-ring type.
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* This matches the types used by mpipe (MPIPE_EDMA_POST_REGION_VAL_t)
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* and trio (TRIO_PUSH_DMA_REGION_VAL_t or TRIO_PULL_DMA_REGION_VAL_t).
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* See those types for more documentation on the individual fields.
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*/
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typedef union {
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struct {
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#ifndef __BIG_ENDIAN__
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uint64_t ring_idx:16;
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uint64_t count:16;
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uint64_t gen:1;
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uint64_t __reserved:31;
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#else
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uint64_t __reserved:31;
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uint64_t gen:1;
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uint64_t count:16;
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uint64_t ring_idx:16;
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#endif
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};
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uint64_t word;
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} __gxio_ring_t;
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void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
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void *post_region_addr, unsigned int num_entries)
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{
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/*
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* Limit 65536 entry rings to 65535 credits because we only have a
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* 16 bit completion counter.
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*/
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int64_t credits = (num_entries < 65536) ? num_entries : 65535;
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memset(dma_queue, 0, sizeof(*dma_queue));
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dma_queue->post_region_addr = post_region_addr;
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dma_queue->hw_complete_count = 0;
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dma_queue->credits_and_next_index = credits << DMA_QUEUE_CREDIT_SHIFT;
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}
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EXPORT_SYMBOL_GPL(__gxio_dma_queue_init);
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void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue)
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{
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__gxio_ring_t val;
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uint64_t count;
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uint64_t delta;
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uint64_t new_count;
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/*
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* Read the 64-bit completion count without touching the cache, so
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* we later avoid having to evict any sharers of this cache line
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* when we update it below.
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*/
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uint64_t orig_hw_complete_count =
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cmpxchg(&dma_queue->hw_complete_count,
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-1, -1);
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/* Make sure the load completes before we access the hardware. */
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wait_for_value(orig_hw_complete_count);
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/* Read the 16-bit count of how many packets it has completed. */
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val.word = __gxio_mmio_read(dma_queue->post_region_addr);
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count = val.count;
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/*
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* Calculate the number of completions since we last updated the
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* 64-bit counter. It's safe to ignore the high bits because the
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* maximum credit value is 65535.
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*/
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delta = (count - orig_hw_complete_count) & 0xffff;
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if (delta == 0)
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return;
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/*
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* Try to write back the count, advanced by delta. If we race with
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* another thread, this might fail, in which case we return
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* immediately on the assumption that some credits are (or at least
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* were) available.
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*/
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new_count = orig_hw_complete_count + delta;
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if (cmpxchg(&dma_queue->hw_complete_count,
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orig_hw_complete_count,
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new_count) != orig_hw_complete_count)
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return;
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/*
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* We succeeded in advancing the completion count; add back the
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* corresponding number of egress credits.
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*/
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__insn_fetchadd(&dma_queue->credits_and_next_index,
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(delta << DMA_QUEUE_CREDIT_SHIFT));
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}
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EXPORT_SYMBOL_GPL(__gxio_dma_queue_update_credits);
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/*
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* A separate 'blocked' method for put() so that backtraces and
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* profiles will clearly indicate that we're wasting time spinning on
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* egress availability rather than actually posting commands.
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*/
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int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
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int64_t modifier)
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{
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int backoff = 16;
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int64_t old;
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do {
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int i;
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/* Back off to avoid spamming memory networks. */
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for (i = backoff; i > 0; i--)
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__insn_mfspr(SPR_PASS);
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/* Check credits again. */
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__gxio_dma_queue_update_credits(dma_queue);
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old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
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modifier);
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/* Calculate bounded exponential backoff for next iteration. */
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if (backoff < 256)
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backoff *= 2;
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} while (old + modifier < 0);
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return old;
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}
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EXPORT_SYMBOL_GPL(__gxio_dma_queue_wait_for_credits);
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int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
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unsigned int num, int wait)
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{
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return __gxio_dma_queue_reserve(dma_queue, num, wait != 0, true);
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}
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EXPORT_SYMBOL_GPL(__gxio_dma_queue_reserve_aux);
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int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
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int64_t completion_slot, int update)
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{
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if (update) {
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if (ACCESS_ONCE(dma_queue->hw_complete_count) >
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completion_slot)
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return 1;
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__gxio_dma_queue_update_credits(dma_queue);
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}
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return ACCESS_ONCE(dma_queue->hw_complete_count) > completion_slot;
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}
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EXPORT_SYMBOL_GPL(__gxio_dma_queue_is_complete);
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@ -0,0 +1,161 @@
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/*
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* Copyright 2012 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _GXIO_DMA_QUEUE_H_
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#define _GXIO_DMA_QUEUE_H_
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/*
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* DMA queue management APIs shared between TRIO and mPIPE.
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*/
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#include "common.h"
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/* The credit counter lives in the high 32 bits. */
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#define DMA_QUEUE_CREDIT_SHIFT 32
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/*
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* State object that tracks a DMA queue's head and tail indices, as
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* well as the number of commands posted and completed. The
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* structure is accessed via a thread-safe, lock-free algorithm.
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*/
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typedef struct {
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/*
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* Address of a MPIPE_EDMA_POST_REGION_VAL_t,
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* TRIO_PUSH_DMA_REGION_VAL_t, or TRIO_PULL_DMA_REGION_VAL_t
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* register. These register have identical encodings and provide
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* information about how many commands have been processed.
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*/
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void *post_region_addr;
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/*
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* A lazily-updated count of how many edescs the hardware has
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* completed.
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*/
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uint64_t hw_complete_count __attribute__ ((aligned(64)));
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/*
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* High 32 bits are a count of available egress command credits,
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* low 24 bits are the next egress "slot".
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*/
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int64_t credits_and_next_index;
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} __gxio_dma_queue_t;
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/* Initialize a dma queue. */
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extern void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
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void *post_region_addr,
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unsigned int num_entries);
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/*
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* Update the "credits_and_next_index" and "hw_complete_count" fields
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* based on pending hardware completions. Note that some other thread
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* may have already done this and, importantly, may still be in the
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* process of updating "credits_and_next_index".
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*/
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extern void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue);
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/* Wait for credits to become available. */
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extern int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
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int64_t modifier);
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/* Reserve slots in the queue, optionally waiting for slots to become
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* available, and optionally returning a "completion_slot" suitable for
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* direct comparison to "hw_complete_count".
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*/
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static inline int64_t __gxio_dma_queue_reserve(__gxio_dma_queue_t *dma_queue,
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unsigned int num, bool wait,
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bool completion)
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{
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uint64_t slot;
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/*
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* Try to reserve 'num' egress command slots. We do this by
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* constructing a constant that subtracts N credits and adds N to
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* the index, and using fetchaddgez to only apply it if the credits
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* count doesn't go negative.
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*/
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int64_t modifier = (((int64_t)(-num)) << DMA_QUEUE_CREDIT_SHIFT) | num;
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int64_t old =
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__insn_fetchaddgez(&dma_queue->credits_and_next_index,
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modifier);
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if (unlikely(old + modifier < 0)) {
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/*
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* We're out of credits. Try once to get more by checking for
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* completed egress commands. If that fails, wait or fail.
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*/
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__gxio_dma_queue_update_credits(dma_queue);
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old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
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modifier);
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if (old + modifier < 0) {
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if (wait)
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old = __gxio_dma_queue_wait_for_credits
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(dma_queue, modifier);
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else
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return GXIO_ERR_DMA_CREDITS;
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}
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}
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/* The bottom 24 bits of old encode the "slot". */
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slot = (old & 0xffffff);
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if (completion) {
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/*
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* A "completion_slot" is a "slot" which can be compared to
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* "hw_complete_count" at any time in the future. To convert
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* "slot" into a "completion_slot", we access "hw_complete_count"
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* once (knowing that we have reserved a slot, and thus, it will
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* be "basically" accurate), and combine its high 40 bits with
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* the 24 bit "slot", and handle "wrapping" by adding "1 << 24"
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* if the result is LESS than "hw_complete_count".
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*/
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uint64_t complete;
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complete = ACCESS_ONCE(dma_queue->hw_complete_count);
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slot |= (complete & 0xffffffffff000000);
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if (slot < complete)
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slot += 0x1000000;
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}
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/*
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* If any of our slots mod 256 were equivalent to 0, go ahead and
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* collect some egress credits, and update "hw_complete_count", and
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* make sure the index doesn't overflow into the credits.
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*/
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if (unlikely(((old + num) & 0xff) < num)) {
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__gxio_dma_queue_update_credits(dma_queue);
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/* Make sure the index doesn't overflow into the credits. */
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#ifdef __BIG_ENDIAN__
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*(((uint8_t *)&dma_queue->credits_and_next_index) + 4) = 0;
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#else
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*(((uint8_t *)&dma_queue->credits_and_next_index) + 3) = 0;
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#endif
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}
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return slot;
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}
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/* Non-inlinable "__gxio_dma_queue_reserve(..., true)". */
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extern int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
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unsigned int num, int wait);
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/* Check whether a particular "completion slot" has completed.
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*
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* Note that this function requires a "completion slot", and thus
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* cannot be used with the result of any "reserve_fast" function.
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*/
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extern int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
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int64_t completion_slot, int update);
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#endif /* !_GXIO_DMA_QUEUE_H_ */
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