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[PATCH] ppc32: fix for misreported SDRAM size on Radstone PPC7D platform 

This patch fixes the SDRAM output from /proc/cpuinfo.  The previous code
assumed that there was only one bank of SDRAM, and that the size in the memory
configuration register was the total size.

Signed-off-by: Chris Elston <chris.elston@radstone.co.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Chris Elston 2005-05-01 08:58:40 -07:00 committed by Linus Torvalds
parent 443a848cd3
commit 630710e3f7
2 changed files with 13 additions and 6 deletions
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18
arch/ppc/platforms/radstone_ppc7d.c
View File

@ -253,6 +253,8 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
u8 val1, val2;
static int flash_sizes[4] = { 64, 32, 0, 16 };
static int flash_banks[4] = { 4, 3, 2, 1 };
static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
int sdram_num_banks = 2;
static char *pci_modes[] = { "PCI33", "PCI66",
"Unknown", "Unknown",
"PCIX33", "PCIX66",
@ -279,13 +281,17 @@ static int ppc7d_show_cpuinfo(struct seq_file *m)
(val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
(val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
val = inb(PPC7D_CPLD_MEM_CONFIG);
if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
val1 = val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK;
seq_printf(m, "SDRAM\t\t: %d%c",
(val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_128M) ? 128 :
(val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_256M) ? 256 :
(val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_512M) ? 512 : 1,
(val1 == PPC7D_CPLD_SDRAM_BANK_SIZE_1G) ? 'G' : 'M');
val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
sdram_num_banks,
sdram_bank_sizes[val1],
(sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
sdram_num_banks * sdram_bank_sizes[val1],
(sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
seq_printf(m, " [ECC %sabled]",
(val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :

1
arch/ppc/platforms/radstone_ppc7d.h
View File

@ -240,6 +240,7 @@
#define PPC7D_CPLD_FLASH_CNTL 0x086E
/* MEMORY_CONFIG_EXTEND */
#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40