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ARM: SoC fixes 

We've been accruing these for a couple of weeks, so the batch is a bit
 bigger than usual.
 
 Largest delta is due to a led-bl driver that is added -- there was
 a miscommunication before the merge window and the driver didn't make it
 in. Due to this, the platforms needing it regressed. At this point, it
 seemed easier to add the new driver than unwind the changes.
 
 Besides that, there are a handful of various fixes:
 
  - AMD tee memory leak fix
 
  - A handful of fixlets for i.MX SCU communication
 
  - A few maintainers woke up and realized DEBUG_FS had been missing for
    a while, so a few updates of that.
 
  ... and the usual collection of smaller fixes to various platforms.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "We've been accruing these for a couple of weeks, so the batch is a bit
  bigger than usual.

  Largest delta is due to a led-bl driver that is added -- there was a
  miscommunication before the merge window and the driver didn't make it
  in. Due to this, the platforms needing it regressed. At this point, it
  seemed easier to add the new driver than unwind the changes.

  Besides that, there are a handful of various fixes:

   - AMD tee memory leak fix

   - A handful of fixlets for i.MX SCU communication

   - A few maintainers woke up and realized DEBUG_FS had been missing
     for a while, so a few updates of that.

  ... and the usual collection of smaller fixes to various platforms"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (37 commits)
  ARM: socfpga_defconfig: Add back DEBUG_FS
  arm64: dts: socfpga: agilex: Fix gmac compatible
  ARM: bcm2835_defconfig: Explicitly restore CONFIG_DEBUG_FS
  arm64: dts: meson: fix gxm-khadas-vim2 wifi
  arm64: dts: meson-sm1-sei610: add missing interrupt-names
  ARM: meson: Drop unneeded select of COMMON_CLK
  ARM: dts: bcm2711: Add pcie0 alias
  ARM: dts: bcm283x: Add missing properties to the PWR LED
  tee: amdtee: fix memory leak in amdtee_open_session()
  ARM: OMAP2+: Fix compile if CONFIG_HAVE_ARM_SMCCC is not set
  arm: dts: dra76x: Fix mmc3 max-frequency
  ARM: dts: dra7: Add "dma-ranges" property to PCIe RC DT nodes
  bus: ti-sysc: Fix 1-wire reset quirk
  ARM: dts: r8a7779: Remove deprecated "renesas, rcar-sata" compatible value
  soc: imx-scu: Align imx sc msg structs to 4
  firmware: imx: Align imx_sc_msg_req_cpu_start to 4
  firmware: imx: scu-pd: Align imx sc msg structs to 4
  firmware: imx: misc: Align imx sc msg structs to 4
  firmware: imx: scu: Ensure sequential TX
  ARM: dts: imx7-colibri: Fix frequency for sd/mmc
  ...
This commit is contained in:
Linus Torvalds 2020-03-08 17:36:22 -07:00
parent efe582a137 d4d89e25fc
commit 62790268e4
43 changed files with 416 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
View File

@ -23,7 +23,11 @@ properties:
description: Global reset register offset and bit offset.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- maxItems: 2
items:
- description: Register offset
- description: Register bit offset
minimum: 0
maximum: 31
"#reset-cells":
minimum: 2

2
MAINTAINERS
View File

@ -14226,7 +14226,7 @@ F: include/dt-bindings/reset/
F: include/linux/reset.h
F: include/linux/reset/
F: include/linux/reset-controller.h
K: \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
K: \b(?:devm_|of_)?reset_control(?:ler_[a-z]+|_[a-z_]+)?\b
RESTARTABLE SEQUENCES SUPPORT
M: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

4
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -526,11 +526,11 @@
* Supply voltage supervisor on board will not allow opp50 so
* disable it and set opp100 as suspend OPP.
*/
opp50@300000000 {
opp50-300000000 {
status = "disabled";
};
opp100@600000000 {
opp100-600000000 {
opp-suspend;
};
};

3
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -21,6 +21,7 @@
aliases {
ethernet0 = &genet;
pcie0 = &pcie0;
};
leds {
@ -31,6 +32,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};

2
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
View File

@ -26,6 +26,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};

2
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@ -27,6 +27,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};

4
arch/arm/boot/dts/dra7-evm.dts
View File

@ -61,10 +61,10 @@
regulator-max-microvolt = <1800000>;
};
evm_3v3: fixedregulator-evm3v3 {
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;

4
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -3474,6 +3474,7 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
@ -3501,6 +3502,7 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
@ -3528,6 +3530,7 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
@ -3555,6 +3558,7 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};

2
arch/arm/boot/dts/dra7.dtsi
View File

@ -184,6 +184,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -238,6 +239,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;

5
arch/arm/boot/dts/dra76x.dtsi
View File

@ -128,3 +128,8 @@
&usb4_tm {
status = "disabled";
};
&mmc3 {
/* dra76x is not affected by i887 */
max-frequency = <96000000>;
};

12
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -796,16 +796,6 @@
clock-div = <1>;
};
ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
assigned-clocks = <&ipu1_gfclk_mux>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -1564,6 +1554,8 @@
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
ipu_clkctrl: ipu-clkctrl@50 {

4
arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
View File

@ -275,7 +275,7 @@
/* SRAM on Colibri nEXT_CS0 */
sram@0,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <0 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
@ -286,7 +286,7 @@
/* SRAM on Colibri nEXT_CS1 */
sram@1,0 {
compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
compatible = "cypress,cy7c1019dv33-10zsxi", "mtd-ram";
reg = <1 0 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;

1
arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
View File

@ -192,7 +192,6 @@
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
vmmc-supply = <&vdd_emmc_1p8>;
status = "disabled";
};

1
arch/arm/boot/dts/imx7-colibri.dtsi
View File

@ -336,7 +336,6 @@
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-step = <2>;
max-frequency = <100000000>;
vmmc-supply = <&reg_module_3v3>;
vqmmc-supply = <&reg_DCDC3>;
non-removable;

6
arch/arm/boot/dts/imx7d.dtsi
View File

@ -44,7 +44,7 @@
opp-hz = /bits/ 64 <792000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xd>, <0xf>;
opp-supported-hw = <0xd>, <0x7>;
opp-suspend;
};
@ -52,7 +52,7 @@
opp-hz = /bits/ 64 <996000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0xc>, <0xf>;
opp-supported-hw = <0xc>, <0x7>;
opp-suspend;
};
@ -60,7 +60,7 @@
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <150000>;
opp-supported-hw = <0x8>, <0xf>;
opp-supported-hw = <0x8>, <0x3>;
opp-suspend;
};
};

4
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -747,7 +747,7 @@
};
mdio0: mdio@2d24000 {
compatible = "fsl,etsec2-mdio";
compatible = "gianfar";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;
@ -756,7 +756,7 @@
};
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
compatible = "gianfar";
device_type = "mdio";
#address-cells = <1>;
#size-cells = <0>;

13
arch/arm/boot/dts/motorola-mapphone-common.dtsi
View File

@ -182,6 +182,14 @@
pwm-names = "enable", "direction";
direction-duty-cycle-ns = <10000000>;
};
backlight: backlight {
compatible = "led-backlight";
leds = <&backlight_led>;
brightness-levels = <31 63 95 127 159 191 223 255>;
default-brightness-level = <6>;
};
};
&dss {
@ -205,6 +213,8 @@
vddi-supply = <&lcd_regulator>;
reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */
backlight = <&backlight>;
width-mm = <50>;
height-mm = <89>;
@ -393,12 +403,11 @@
ramp-up-us = <1024>;
ramp-down-us = <8193>;
led@0 {
backlight_led: led@0 {
reg = <0>;
led-sources = <2>;
ti,led-mode = <0>;
label = ":backlight";
linux,default-trigger = "backlight";
};
led@1 {

2
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -377,7 +377,7 @@
};
sata: sata@fc600000 {
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
compatible = "renesas,sata-r8a7779";
reg = <0xfc600000 0x200000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;

1
arch/arm/configs/bcm2835_defconfig
View File

@ -178,6 +178,7 @@ CONFIG_SCHED_TRACER=y
CONFIG_STACK_TRACER=y
CONFIG_FUNCTION_PROFILER=y
CONFIG_TEST_KSTRTOX=y
CONFIG_DEBUG_FS=y
CONFIG_KGDB=y
CONFIG_KGDB_KDB=y
CONFIG_STRICT_DEVMEM=y

1
arch/arm/configs/omap2plus_defconfig
View File

@ -375,6 +375,7 @@ CONFIG_BACKLIGHT_GENERIC=m
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_PANDORA=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_BACKLIGHT_LED=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y

1
arch/arm/configs/socfpga_defconfig
View File

@ -157,6 +157,7 @@ CONFIG_NLS_ISO8859_1=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_INFO=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_FUNCTION_TRACER=y

2
arch/arm/mach-imx/Makefile
View File

@ -91,6 +91,8 @@ AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
endif
AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
obj-$(CONFIG_SOC_IMX1) += mach-imx1.o

4
arch/arm/mach-imx/common.h
View File

@ -109,17 +109,17 @@ void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
#ifdef CONFIG_SUSPEND
void v7_cpu_resume(void);
void imx53_suspend(void __iomem *ocram_vbase);
extern const u32 imx53_suspend_sz;
void imx6_suspend(void __iomem *ocram_vbase);
#else
static inline void v7_cpu_resume(void) {}
static inline void imx53_suspend(void __iomem *ocram_vbase) {}
static const u32 imx53_suspend_sz;
static inline void imx6_suspend(void __iomem *ocram_vbase) {}
#endif
void v7_cpu_resume(void);
void imx6_pm_ccm_init(const char *ccm_compat);
void imx6q_pm_init(void);
void imx6dl_pm_init(void);

24
arch/arm/mach-imx/resume-imx6.S Normal file
View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
* turned into relative ones.
*/
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
#ifdef CONFIG_CACHE_L2X0
bl l2c310_early_resume
#endif
b cpu_resume
ENDPROC(v7_cpu_resume)

14
arch/arm/mach-imx/suspend-imx6.S
View File

@ -327,17 +327,3 @@ resume:
ret lr
ENDPROC(imx6_suspend)
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be
* turned into relative ones.
*/
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
#ifdef CONFIG_CACHE_L2X0
bl l2c310_early_resume
#endif
b cpu_resume
ENDPROC(v7_cpu_resume)

1
arch/arm/mach-meson/Kconfig
View File

@ -9,7 +9,6 @@ menuconfig ARCH_MESON
select CACHE_L2X0
select PINCTRL
select PINCTRL_MESON
select COMMON_CLK
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP

2
arch/arm/mach-omap2/Makefile
View File

@ -16,7 +16,7 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
clock-common = clock.o
secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)

2
arch/arm/mach-omap2/io.c
View File

@ -431,7 +431,6 @@ void __init omap2420_init_early(void)
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table;
omap_secure_init();
}
void __init omap2420_init_late(void)
@ -456,7 +455,6 @@ void __init omap2430_init_early(void)
omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table;
omap_secure_init();
}
void __init omap2430_init_late(void)

2
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
View File

@ -327,7 +327,7 @@
#size-cells = <0>;
bus-width = <4>;
max-frequency = <50000000>;
max-frequency = <60000000>;
non-removable;
disable-wp;

1
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@ -593,6 +593,7 @@
compatible = "brcm,bcm43438-bt";
interrupt-parent = <&gpio_intc>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wakeup";
shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
max-speed = <2000000>;
clocks = <&wifi32k>;

5
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -52,11 +52,6 @@
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};

6
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -102,7 +102,7 @@
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
@ -118,7 +118,7 @@
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
@ -134,7 +134,7 @@
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";

2
arch/arm64/configs/defconfig
View File

@ -773,7 +773,7 @@ CONFIG_ARCH_R8A774A1=y
CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R8A774C0=y
CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
CONFIG_ARCH_R8A77960=y
CONFIG_ARCH_R8A77961=y
CONFIG_ARCH_R8A77965=y
CONFIG_ARCH_R8A77970=y

4
drivers/bus/ti-sysc.c
View File

@ -1400,7 +1400,7 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
}
/* 1-wire needs module's internal clocks enabled for reset */
static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
{
int offset = 0x0c; /* HDQ_CTRL_STATUS */
u16 val;
@ -1488,7 +1488,7 @@ static void sysc_init_module_quirks(struct sysc *ddata)
return;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
ddata->clk_disable_quirk = sysc_pre_reset_quirk_hdq1w;
return;
}

27
drivers/firmware/imx/imx-scu.c
View File

@ -29,6 +29,7 @@ struct imx_sc_chan {
struct mbox_client cl;
struct mbox_chan *ch;
int idx;
struct completion tx_done;
};
struct imx_sc_ipc {
@ -100,6 +101,14 @@ int imx_scu_get_handle(struct imx_sc_ipc **ipc)
}
EXPORT_SYMBOL(imx_scu_get_handle);
/* Callback called when the word of a message is ack-ed, eg read by SCU */
static void imx_scu_tx_done(struct mbox_client *cl, void *mssg, int r)
{
struct imx_sc_chan *sc_chan = container_of(cl, struct imx_sc_chan, cl);
complete(&sc_chan->tx_done);
}
static void imx_scu_rx_callback(struct mbox_client *c, void *msg)
{
struct imx_sc_chan *sc_chan = container_of(c, struct imx_sc_chan, cl);
@ -149,6 +158,19 @@ static int imx_scu_ipc_write(struct imx_sc_ipc *sc_ipc, void *msg)
for (i = 0; i < hdr->size; i++) {
sc_chan = &sc_ipc->chans[i % 4];
/*
* SCU requires that all messages words are written
* sequentially but linux MU driver implements multiple
* independent channels for each register so ordering between
* different channels must be ensured by SCU API interface.
*
* Wait for tx_done before every send to ensure that no
* queueing happens at the mailbox channel level.
*/
wait_for_completion(&sc_chan->tx_done);
reinit_completion(&sc_chan->tx_done);
ret = mbox_send_message(sc_chan->ch, &data[i]);
if (ret < 0)
return ret;
@ -247,6 +269,11 @@ static int imx_scu_probe(struct platform_device *pdev)
cl->knows_txdone = true;
cl->rx_callback = imx_scu_rx_callback;
/* Initial tx_done completion as "done" */
cl->tx_done = imx_scu_tx_done;
init_completion(&sc_chan->tx_done);
complete(&sc_chan->tx_done);
sc_chan->sc_ipc = sc_ipc;
sc_chan->idx = i % 4;
sc_chan->ch = mbox_request_channel_byname(cl, chan_name);

8
drivers/firmware/imx/misc.c
View File

@ -16,7 +16,7 @@ struct imx_sc_msg_req_misc_set_ctrl {
u32 ctrl;
u32 val;
u16 resource;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_req_cpu_start {
struct imx_sc_rpc_msg hdr;
@ -24,18 +24,18 @@ struct imx_sc_msg_req_cpu_start {
u32 address_lo;
u16 resource;
u8 enable;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_req_misc_get_ctrl {
struct imx_sc_rpc_msg hdr;
u32 ctrl;
u16 resource;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_resp_misc_get_ctrl {
struct imx_sc_rpc_msg hdr;
u32 val;
} __packed;
} __packed __aligned(4);
/*
* This function sets a miscellaneous control value.

2
drivers/firmware/imx/scu-pd.c
View File

@ -61,7 +61,7 @@ struct imx_sc_msg_req_set_resource_power_mode {
struct imx_sc_rpc_msg hdr;
u16 resource;
u8 mode;
} __packed;
} __packed __aligned(4);
#define IMX_SCU_PD_NAME_SIZE 20
struct imx_sc_pm_domain {

3
drivers/reset/Kconfig
View File

@ -51,6 +51,7 @@ config RESET_BRCMSTB
config RESET_BRCMSTB_RESCAL
bool "Broadcom STB RESCAL reset controller"
depends on HAS_IOMEM
default ARCH_BRCMSTB || COMPILE_TEST
help
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
@ -73,7 +74,7 @@ config RESET_IMX7
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on OF
depends on OF && HAS_IOMEM
select REGMAP_MMIO
help
This enables the reset controller driver for Intel Gateway SoCs.

2
drivers/soc/imx/soc-imx-scu.c
View File

@ -25,7 +25,7 @@ struct imx_sc_msg_misc_get_soc_id {
u32 id;
} resp;
} data;
} __packed;
} __packed __aligned(4);
struct imx_sc_msg_misc_get_soc_uid {
struct imx_sc_rpc_msg hdr;

48
drivers/tee/amdtee/core.c
View File

@ -212,6 +212,19 @@ unlock:
return rc;
}
static void destroy_session(struct kref *ref)
{
struct amdtee_session *sess = container_of(ref, struct amdtee_session,
refcount);
/* Unload the TA from TEE */
handle_unload_ta(sess->ta_handle);
mutex_lock(&session_list_mutex);
list_del(&sess->list_node);
mutex_unlock(&session_list_mutex);
kfree(sess);
}
int amdtee_open_session(struct tee_context *ctx,
struct tee_ioctl_open_session_arg *arg,
struct tee_param *param)
@ -236,15 +249,13 @@ int amdtee_open_session(struct tee_context *ctx,
/* Load the TA binary into TEE environment */
handle_load_ta(ta, ta_size, arg);
if (arg->ret == TEEC_SUCCESS) {
mutex_lock(&session_list_mutex);
sess = alloc_session(ctxdata, arg->session);
mutex_unlock(&session_list_mutex);
}
if (arg->ret != TEEC_SUCCESS)
goto out;
mutex_lock(&session_list_mutex);
sess = alloc_session(ctxdata, arg->session);
mutex_unlock(&session_list_mutex);
if (!sess) {
rc = -ENOMEM;
goto out;
@ -259,40 +270,29 @@ int amdtee_open_session(struct tee_context *ctx,
if (i >= TEE_NUM_SESSIONS) {
pr_err("reached maximum session count %d\n", TEE_NUM_SESSIONS);
kref_put(&sess->refcount, destroy_session);
rc = -ENOMEM;
goto out;
}
/* Open session with loaded TA */
handle_open_session(arg, &session_info, param);
if (arg->ret == TEEC_SUCCESS) {
sess->session_info[i] = session_info;
set_session_id(sess->ta_handle, i, &arg->session);
} else {
if (arg->ret != TEEC_SUCCESS) {
pr_err("open_session failed %d\n", arg->ret);
spin_lock(&sess->lock);
clear_bit(i, sess->sess_mask);
spin_unlock(&sess->lock);
kref_put(&sess->refcount, destroy_session);
goto out;
}
sess->session_info[i] = session_info;
set_session_id(sess->ta_handle, i, &arg->session);
out:
free_pages((u64)ta, get_order(ta_size));
return rc;
}
static void destroy_session(struct kref *ref)
{
struct amdtee_session *sess = container_of(ref, struct amdtee_session,
refcount);
/* Unload the TA from TEE */
handle_unload_ta(sess->ta_handle);
mutex_lock(&session_list_mutex);
list_del(&sess->list_node);
mutex_unlock(&session_list_mutex);
kfree(sess);
}
int amdtee_close_session(struct tee_context *ctx, u32 session)
{
struct amdtee_context_data *ctxdata = ctx->data;

7
drivers/video/backlight/Kconfig
View File

@ -456,6 +456,13 @@ config BACKLIGHT_RAVE_SP
help
Support for backlight control on RAVE SP device.
config BACKLIGHT_LED
tristate "Generic LED based Backlight Driver"
depends on LEDS_CLASS && OF
help
If you have a LCD backlight adjustable by LED class driver, say Y
to enable this driver.
endif # BACKLIGHT_CLASS_DEVICE
endmenu

1
drivers/video/backlight/Makefile
View File

@ -57,3 +57,4 @@ obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o
obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o
obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o
obj-$(CONFIG_BACKLIGHT_RAVE_SP) += rave-sp-backlight.o
obj-$(CONFIG_BACKLIGHT_LED) += led_bl.o

260
drivers/video/backlight/led_bl.c Normal file
View File

@ -0,0 +1,260 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
*
* Based on pwm_bl.c
*/
#include <linux/backlight.h>
#include <linux/leds.h>
#include <linux/module.h>
#include <linux/platform_device.h>
struct led_bl_data {
struct device *dev;
struct backlight_device *bl_dev;
struct led_classdev **leds;
bool enabled;
int nb_leds;
unsigned int *levels;
unsigned int default_brightness;
unsigned int max_brightness;
};
static void led_bl_set_brightness(struct led_bl_data *priv, int level)
{
int i;
int bkl_brightness;
if (priv->levels)
bkl_brightness = priv->levels[level];
else
bkl_brightness = level;
for (i = 0; i < priv->nb_leds; i++)
led_set_brightness(priv->leds[i], bkl_brightness);
priv->enabled = true;
}
static void led_bl_power_off(struct led_bl_data *priv)
{
int i;
if (!priv->enabled)
return;
for (i = 0; i < priv->nb_leds; i++)
led_set_brightness(priv->leds[i], LED_OFF);
priv->enabled = false;
}
static int led_bl_update_status(struct backlight_device *bl)
{
struct led_bl_data *priv = bl_get_data(bl);
int brightness = bl->props.brightness;
if (bl->props.power != FB_BLANK_UNBLANK ||
bl->props.fb_blank != FB_BLANK_UNBLANK ||
bl->props.state & BL_CORE_FBBLANK)
brightness = 0;
if (brightness > 0)
led_bl_set_brightness(priv, brightness);
else
led_bl_power_off(priv);
return 0;
}
static const struct backlight_ops led_bl_ops = {
.update_status = led_bl_update_status,
};
static int led_bl_get_leds(struct device *dev,
struct led_bl_data *priv)
{
int i, nb_leds, ret;
struct device_node *node = dev->of_node;
struct led_classdev **leds;
unsigned int max_brightness;
unsigned int default_brightness;
ret = of_count_phandle_with_args(node, "leds", NULL);
if (ret < 0) {
dev_err(dev, "Unable to get led count\n");
return -EINVAL;
}
nb_leds = ret;
if (nb_leds < 1) {
dev_err(dev, "At least one LED must be specified!\n");
return -EINVAL;
}
leds = devm_kzalloc(dev, sizeof(struct led_classdev *) * nb_leds,
GFP_KERNEL);
if (!leds)
return -ENOMEM;
for (i = 0; i < nb_leds; i++) {
leds[i] = devm_of_led_get(dev, i);
if (IS_ERR(leds[i]))
return PTR_ERR(leds[i]);
}
/* check that the LEDs all have the same brightness range */
max_brightness = leds[0]->max_brightness;
for (i = 1; i < nb_leds; i++) {
if (max_brightness != leds[i]->max_brightness) {
dev_err(dev, "LEDs must have identical ranges\n");
return -EINVAL;
}
}
/* get the default brightness from the first LED from the list */
default_brightness = leds[0]->brightness;
priv->nb_leds = nb_leds;
priv->leds = leds;
priv->max_brightness = max_brightness;
priv->default_brightness = default_brightness;
return 0;
}
static int led_bl_parse_levels(struct device *dev,
struct led_bl_data *priv)
{
struct device_node *node = dev->of_node;
int num_levels;
u32 value;
int ret;
if (!node)
return -ENODEV;
num_levels = of_property_count_u32_elems(node, "brightness-levels");
if (num_levels > 1) {
int i;
unsigned int db;
u32 *levels = NULL;
levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
GFP_KERNEL);
if (!levels)
return -ENOMEM;
ret = of_property_read_u32_array(node, "brightness-levels",
levels,
num_levels);
if (ret < 0)
return ret;
/*
* Try to map actual LED brightness to backlight brightness
* level
*/
db = priv->default_brightness;
for (i = 0 ; i < num_levels; i++) {
if ((i && db > levels[i-1]) && db <= levels[i])
break;
}
priv->default_brightness = i;
priv->max_brightness = num_levels - 1;
priv->levels = levels;
} else if (num_levels >= 0)
dev_warn(dev, "Not enough levels defined\n");
ret = of_property_read_u32(node, "default-brightness-level", &value);
if (!ret && value <= priv->max_brightness)
priv->default_brightness = value;
else if (!ret && value > priv->max_brightness)
dev_warn(dev, "Invalid default brightness. Ignoring it\n");
return 0;
}
static int led_bl_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct led_bl_data *priv;
int ret, i;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->dev = &pdev->dev;
ret = led_bl_get_leds(&pdev->dev, priv);
if (ret)
return ret;
ret = led_bl_parse_levels(&pdev->dev, priv);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to parse DT data\n");
return ret;
}
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = priv->max_brightness;
props.brightness = priv->default_brightness;
props.power = (priv->default_brightness > 0) ? FB_BLANK_POWERDOWN :
FB_BLANK_UNBLANK;
priv->bl_dev = backlight_device_register(dev_name(&pdev->dev),
&pdev->dev, priv, &led_bl_ops, &props);
if (IS_ERR(priv->bl_dev)) {
dev_err(&pdev->dev, "Failed to register backlight\n");
return PTR_ERR(priv->bl_dev);
}
for (i = 0; i < priv->nb_leds; i++)
led_sysfs_disable(priv->leds[i]);
backlight_update_status(priv->bl_dev);
return 0;
}
static int led_bl_remove(struct platform_device *pdev)
{
struct led_bl_data *priv = platform_get_drvdata(pdev);
struct backlight_device *bl = priv->bl_dev;
int i;
backlight_device_unregister(bl);
led_bl_power_off(priv);
for (i = 0; i < priv->nb_leds; i++)
led_sysfs_enable(priv->leds[i]);
return 0;
}
static const struct of_device_id led_bl_of_match[] = {
{ .compatible = "led-backlight" },
{ }
};
MODULE_DEVICE_TABLE(of, led_bl_of_match);
static struct platform_driver led_bl_driver = {
.driver = {
.name = "led-backlight",
.of_match_table = of_match_ptr(led_bl_of_match),
},
.probe = led_bl_probe,
.remove = led_bl_remove,
};
module_platform_driver(led_bl_driver);
MODULE_DESCRIPTION("LED based Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:led-backlight");