MT2712:
- replace deprecated compatible for the usb PHY MT6797: - switch to SPDX identifier - add and enable I2C device for x20 development board - add I2C compatible to the binding description MT7622: - add Wi-Fi device and enable it for the Bananpi-R64 MT8173: - add CPU capacities based on Dhryston benchmark - fix DT build warnings - set throtteling range to limitless - add Elm and Hana devices on which several chromebooks are based - add Global Command Queue entries to the users MT8183: - split cpuidle states in two as the clusters have different target residencies -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAl7APygXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH61dQ/6AmOSIyRASzUakYIsINERDP2e OEFRy8aEDo6WG6Ww6Fc93cxb0EigzVEdZV67hTyF6/OuWfzM6UM+TI40ZqBEAbcV 4O/keVh7mT7mSU5Qbx0RkJaimPzIXX6h9otGL5cFlGkCkx4HIrg+WaF44n7mibFI y4gSTnMQSVHSQk2aU5CNnEyybYk/7L5WoPrciykNpOXKw+LCcZ6dwzyA5uA9PcFy XTnjoIwdPRSnYKw8MNVGGLe56HS2luWs0Yr4zv1sVZNczNNGcZ3HOTI1m4lrYW2A aCtLMTYiu+ujTq59fyJ9FocL+2gzwWYcRpr3RbE/ykwnWeDrm4S2hCDd3NpvyqRh /EYFYzvbPle3+uGlyWu3RNWscoo8J+C/tm3tksiObOmoZ8K8InY2QjaSnqHFPRfQ lqdNFhsi5mPPpAz1aQYtNFTwAcSZndNQFOGFYdxZZerjIOWw+I45x0O06yVtYN/9 PQSqOoMDlt2Tpyzr9CC7Fso/+e6Z7KsezC3xQhUgvUCJ9CUMmyAn2WgJx9DsVCWi N+2e1sbaimUf/Ee5i6qDRjDlnTIXulMOZQFYrj30QKuFOqSzduvfW9L5dFSH+/aR FvtpAogUreYoXvY6frNaHUaUHuo9yOgP/DIIdzAmwL5/Frgb19keQc/RFSGNh+7C d38+03KUniYJ3Kl1gCw= =tN8C -----END PGP SIGNATURE----- Merge tag 'v5.7-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt MT2712: - replace deprecated compatible for the usb PHY MT6797: - switch to SPDX identifier - add and enable I2C device for x20 development board - add I2C compatible to the binding description MT7622: - add Wi-Fi device and enable it for the Bananpi-R64 MT8173: - add CPU capacities based on Dhryston benchmark - fix DT build warnings - set throtteling range to limitless - add Elm and Hana devices on which several chromebooks are based - add Global Command Queue entries to the users MT8183: - split cpuidle states in two as the clusters have different target residencies * tag 'v5.7-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt8173: Add capacity-dmips-mhz attributes arm64: dts: mt2712: use non-empty ranges for usb-phy arm64: dts: mt8173: fix mdp aliases property name arm64: dts: mediatek: Switch to SPDX license identifier for MT6797 SoC arm64: dts: mediatek: Enable I2C support for 96Boards X20 Development board arm64: dts: mediatek: Add I2C support for MT6797 SoC dt-bindings: i2c: Document I2C controller binding for MT6797 SoC arm64: dts: mt8173: fix cooling device range arm64: dts: mediatek: add mt8173 elm and hana board arm64: dts: mt8173: fix unit name warnings arm64: dts: mt8173: add uart aliases dt-bindings: arm64: dts: mediatek: Add mt8173 elm and hana arm64: dts: mt8183: adjust cpuidle target residency arm64: dts: mt8173: Add gce setting in mmsys and display node arm64: dts: mt7622: add built-in Wi-Fi device nodes Link: https://lore.kernel.org/r/2794a8db-c14f-ac34-9e28-9f3700db6c4c@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
622a380d62
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@ -84,6 +84,28 @@ properties:
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- enum:
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- mediatek,mt8135-evbp1
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- const: mediatek,mt8135
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- description: Google Elm (Acer Chromebook R13)
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items:
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- const: google,elm-rev8
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- const: google,elm-rev7
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- const: google,elm-rev6
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- const: google,elm-rev5
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- const: google,elm-rev4
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- const: google,elm-rev3
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- const: google,elm
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- const: mediatek,mt8173
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- description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...)
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items:
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- const: google,hana-rev6
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- const: google,hana-rev5
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- const: google,hana-rev4
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- const: google,hana-rev3
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- const: google,hana
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- const: mediatek,mt8173
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- description: Google Hana rev7 (Poin2 Chromebook 11C)
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items:
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- const: google,hana-rev7
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- const: mediatek,mt8173
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- items:
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- enum:
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- mediatek,mt8173-evb
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@ -8,6 +8,7 @@ Required properties:
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"mediatek,mt2712-i2c": for MediaTek MT2712
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"mediatek,mt6577-i2c": for MediaTek MT6577
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"mediatek,mt6589-i2c": for MediaTek MT6589
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"mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
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"mediatek,mt7622-i2c": for MediaTek MT7622
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"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
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"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
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@ -6,6 +6,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
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@ -703,30 +703,31 @@
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};
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u3phy0: usb-phy@11290000 {
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compatible = "mediatek,mt2712-u3phy";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "mediatek,mt2712-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x11290000 0x9000>;
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status = "okay";
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u2port0: usb-phy@11290000 {
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reg = <0 0x11290000 0 0x700>;
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u2port0: usb-phy@0 {
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reg = <0x0 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u2port1: usb-phy@11298000 {
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reg = <0 0x11298000 0 0x700>;
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u2port1: usb-phy@8000 {
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reg = <0x8000 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port0: usb-phy@11298700 {
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reg = <0 0x11298700 0 0x900>;
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u3port0: usb-phy@8700 {
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reg = <0x8700 0x900>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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@ -766,30 +767,31 @@
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};
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u3phy1: usb-phy@112e0000 {
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compatible = "mediatek,mt2712-u3phy";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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compatible = "mediatek,mt2712-tphy",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x112e0000 0x9000>;
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status = "okay";
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u2port2: usb-phy@112e0000 {
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reg = <0 0x112e0000 0 0x700>;
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u2port2: usb-phy@0 {
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reg = <0x0 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u2port3: usb-phy@112e8000 {
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reg = <0 0x112e8000 0 0x700>;
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u2port3: usb-phy@8000 {
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reg = <0x8000 0x700>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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u3port1: usb-phy@112e8700 {
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reg = <0 0x112e8700 0 0x900>;
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u3port1: usb-phy@8700 {
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reg = <0x8700 0x900>;
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clocks = <&clk26m>;
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clock-names = "ref";
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#phy-cells = <1>;
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@ -28,6 +28,55 @@
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};
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};
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/* HDMI */
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins_a>;
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status = "okay";
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};
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/* HS - I2C2 */
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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status = "okay";
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};
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/* HS - I2C3 */
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&i2c3 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_pins_a>;
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status = "okay";
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};
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/* LS - I2C0 */
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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status = "okay";
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};
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/* LS - I2C1 */
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&i2c5 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c5_pins_a>;
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status = "okay";
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};
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/* POWER_VPROC */
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&i2c6 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6_pins_a>;
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status = "okay";
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};
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/* FAN53555 */
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&i2c7 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7_pins_a>;
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status = "okay";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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@ -1,14 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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||||
* This program is distributed in the hope that it will be useful,
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt6797-clk.h>
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@ -155,6 +148,62 @@
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<MT6797_GPIO233__FUNC_UTXD1>;
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};
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};
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i2c0_pins_a: i2c0 {
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pins0 {
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pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
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<MT6797_GPIO38__FUNC_SDA0_0>;
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};
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};
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i2c1_pins_a: i2c1 {
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pins1 {
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pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
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<MT6797_GPIO56__FUNC_SDA1_0>;
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};
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};
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i2c2_pins_a: i2c2 {
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pins2 {
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pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
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<MT6797_GPIO95__FUNC_SDA2_0>;
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};
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};
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i2c3_pins_a: i2c3 {
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pins3 {
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pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
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<MT6797_GPIO74__FUNC_SCL3_0>;
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};
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};
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i2c4_pins_a: i2c4 {
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pins4 {
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pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
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<MT6797_GPIO239__FUNC_SCL4_0>;
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};
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};
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i2c5_pins_a: i2c5 {
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pins5 {
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pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
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<MT6797_GPIO241__FUNC_SCL5_0>;
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};
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};
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i2c6_pins_a: i2c6 {
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pins6 {
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pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
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<MT6797_GPIO151__FUNC_SCL6_0>;
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};
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};
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i2c7_pins_a: i2c7 {
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pins7 {
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pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
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<MT6797_GPIO153__FUNC_SCL7_0>;
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};
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};
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};
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scpsys: power-controller@10006000 {
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@ -233,6 +282,170 @@
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt6797-i2c",
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"mediatek,mt6577-i2c";
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id = <0>;
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reg = <0 0x11007000 0 0x1000>,
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<0 0x11000100 0 0x80>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infrasys CLK_INFRA_I2C0>,
|
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<&infrasys CLK_INFRA_AP_DMA>;
|
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clock-names = "main", "dma";
|
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clock-div = <10>;
|
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
|
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt6797-i2c",
|
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"mediatek,mt6577-i2c";
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id = <1>;
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reg = <0 0x11008000 0 0x1000>,
|
||||
<0 0x11000180 0 0x80>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C1>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c8: i2c@11009000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <8>;
|
||||
reg = <0 0x11009000 0 0x1000>,
|
||||
<0 0x11000200 0 0x80>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C2>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C2_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@1100d000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <9>;
|
||||
reg = <0 0x1100d000 0 0x1000>,
|
||||
<0 0x11000280 0 0x80>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C3>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C3_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@1100e000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <6>;
|
||||
reg = <0 0x1100e000 0 0x1000>,
|
||||
<0 0x11000500 0 0x80>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C_APPM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@11010000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <7>;
|
||||
reg = <0 0x11010000 0 0x1000>,
|
||||
<0 0x11000580 0 0x80>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@11011000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <4>;
|
||||
reg = <0 0x11011000 0 0x1000>,
|
||||
<0 0x11000300 0 0x80>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C4>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@11013000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <2>;
|
||||
reg = <0 0x11013000 0 0x1000>,
|
||||
<0 0x11000400 0 0x80>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C2_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@11014000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <3>;
|
||||
reg = <0 0x11014000 0 0x1000>,
|
||||
<0 0x11000480 0 0x80>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>,
|
||||
<&infrasys CLK_INFRA_I2C3_ARB>;
|
||||
clock-names = "main", "dma", "arb";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c5: i2c@1101c000 {
|
||||
compatible = "mediatek,mt6797-i2c",
|
||||
"mediatek,mt6577-i2c";
|
||||
id = <5>;
|
||||
reg = <0 0x1101c000 0 0x1000>,
|
||||
<0 0x11000380 0 0x80>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infrasys CLK_INFRA_I2C5>,
|
||||
<&infrasys CLK_INFRA_AP_DMA>;
|
||||
clock-names = "main", "dma";
|
||||
clock-div = <10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmsys: mmsys_config@14000000 {
|
||||
compatible = "mediatek,mt6797-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -543,3 +543,7 @@
|
|||
pinctrl-0 = <&watchdog_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -506,3 +506,7 @@
|
|||
pinctrl-0 = <&watchdog_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wmac {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -699,6 +699,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
wmac: wmac@18000000 {
|
||||
compatible = "mediatek,mt7622-wmac";
|
||||
reg = <0 0x18000000 0 0x100000>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
|
||||
};
|
||||
|
||||
ssusbsys: ssusbsys@1a000000 {
|
||||
compatible = "mediatek,mt7622-ssusbsys",
|
||||
"syscon";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2019 MediaTek Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8173-elm-hana.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Hanawl";
|
||||
compatible = "google,hana-rev7", "mediatek,mt8173";
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
trips {
|
||||
cpu_crit: cpu_crit0 {
|
||||
temperature = <100000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_keys {
|
||||
/delete-node/tablet_mode;
|
||||
/delete-node/volume_down;
|
||||
/delete-node/volume_up;
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2016 MediaTek Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8173-elm-hana.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Hana";
|
||||
compatible = "google,hana-rev6", "google,hana-rev5",
|
||||
"google,hana-rev4", "google,hana-rev3",
|
||||
"google,hana", "mediatek,mt8173";
|
||||
};
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2016 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#include "mt8173-elm.dtsi"
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <200000>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
touchscreen2: touchscreen@34 {
|
||||
compatible = "melfas,mip4_ts";
|
||||
reg = <0x34>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
|
||||
* Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a
|
||||
* second source touchscreen.
|
||||
*/
|
||||
touchscreen3: touchscreen@20 {
|
||||
compatible = "hid-over-i2c";
|
||||
reg = <0x20>;
|
||||
hid-descr-addr = <0x0020>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
/*
|
||||
* Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd
|
||||
* Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a
|
||||
* second source trackpad.
|
||||
*/
|
||||
trackpad2: trackpad@2c {
|
||||
compatible = "hid-over-i2c";
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
|
||||
reg = <0x2c>;
|
||||
hid-descr-addr = <0x0020>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&pio {
|
||||
hdmi_mux_pins: hdmi_mux_pins {
|
||||
pins2 {
|
||||
pinmux = <MT8173_PIN_98_URTS1__FUNC_GPIO98>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_pins_default: mmc1default {
|
||||
pins_wp {
|
||||
pinmux = <MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2016 MediaTek Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt8173-elm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Elm";
|
||||
compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6",
|
||||
"google,elm-rev5", "google,elm-rev4", "google,elm-rev3",
|
||||
"google,elm", "mediatek,mt8173";
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -19,6 +19,7 @@
|
|||
#include <dt-bindings/power/mt8173-power.h>
|
||||
#include <dt-bindings/reset/mt8173-resets.h>
|
||||
#include <dt-bindings/gce/mt8173-gce.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include "mt8173-pinfunc.h"
|
||||
|
||||
/ {
|
||||
|
|
@ -42,14 +43,18 @@
|
|||
dpi0 = &dpi0;
|
||||
dsi0 = &dsi0;
|
||||
dsi1 = &dsi1;
|
||||
mdp_rdma0 = &mdp_rdma0;
|
||||
mdp_rdma1 = &mdp_rdma1;
|
||||
mdp_rsz0 = &mdp_rsz0;
|
||||
mdp_rsz1 = &mdp_rsz1;
|
||||
mdp_rsz2 = &mdp_rsz2;
|
||||
mdp_wdma0 = &mdp_wdma0;
|
||||
mdp_wrot0 = &mdp_wrot0;
|
||||
mdp_wrot1 = &mdp_wrot1;
|
||||
mdp-rdma0 = &mdp_rdma0;
|
||||
mdp-rdma1 = &mdp_rdma1;
|
||||
mdp-rsz0 = &mdp_rsz0;
|
||||
mdp-rsz1 = &mdp_rsz1;
|
||||
mdp-rsz2 = &mdp_rsz2;
|
||||
mdp-wdma0 = &mdp_wdma0;
|
||||
mdp-wrot0 = &mdp_wrot0;
|
||||
mdp-wrot1 = &mdp_wrot1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
|
|
@ -162,6 +167,7 @@
|
|||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <526>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
|
@ -176,6 +182,7 @@
|
|||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <526>;
|
||||
};
|
||||
|
||||
cpu2: cpu@100 {
|
||||
|
|
@ -190,6 +197,7 @@
|
|||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
cpu3: cpu@101 {
|
||||
|
|
@ -204,6 +212,7 @@
|
|||
<&apmixedsys CLK_APMIXED_MAINPLL>;
|
||||
clock-names = "cpu", "intermediate";
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
|
|
@ -242,21 +251,21 @@
|
|||
cpu_on = <0x84000003>;
|
||||
};
|
||||
|
||||
clk26m: oscillator@0 {
|
||||
clk26m: oscillator0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "clk26m";
|
||||
};
|
||||
|
||||
clk32k: oscillator@1 {
|
||||
clk32k: oscillator1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32000>;
|
||||
clock-output-names = "clk32k";
|
||||
};
|
||||
|
||||
cpum_ck: oscillator@2 {
|
||||
cpum_ck: oscillator2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
|
|
@ -272,19 +281,19 @@
|
|||
sustainable-power = <1500>; /* milliwatts */
|
||||
|
||||
trips {
|
||||
threshold: trip-point@0 {
|
||||
threshold: trip-point0 {
|
||||
temperature = <68000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
target: trip-point@1 {
|
||||
target: trip-point1 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_crit: cpu_crit@0 {
|
||||
cpu_crit: cpu_crit0 {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
|
|
@ -292,16 +301,20 @@
|
|||
};
|
||||
|
||||
cooling-maps {
|
||||
map@0 {
|
||||
map0 {
|
||||
trip = <&target>;
|
||||
cooling-device = <&cpu0 0 0>,
|
||||
<&cpu1 0 0>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
contribution = <3072>;
|
||||
};
|
||||
map@1 {
|
||||
map1 {
|
||||
trip = <&target>;
|
||||
cooling-device = <&cpu2 0 0>,
|
||||
<&cpu3 0 0>;
|
||||
cooling-device = <&cpu2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
contribution = <1024>;
|
||||
};
|
||||
};
|
||||
|
|
@ -312,7 +325,7 @@
|
|||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
vpu_dma_reserved: vpu_dma_mem_region {
|
||||
vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0 0xb7000000 0 0x500000>;
|
||||
alignment = <0x1000>;
|
||||
|
|
@ -365,7 +378,7 @@
|
|||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
pio: pinctrl@1000b000 {
|
||||
compatible = "mediatek,mt8173-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
||||
|
|
@ -549,7 +562,7 @@
|
|||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_GCE>;
|
||||
clock-names = "gce";
|
||||
#mbox-cells = <3>;
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
mipi_tx0: mipi-dphy@10215000 {
|
||||
|
|
@ -572,7 +585,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10220000 {
|
||||
gic: interrupt-controller@10221000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -916,6 +929,9 @@
|
|||
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
#clock-cells = <1>;
|
||||
mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
|
||||
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
|
||||
};
|
||||
|
||||
mdp_rdma0: rdma@14001000 {
|
||||
|
|
@ -996,6 +1012,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
|
||||
};
|
||||
|
||||
ovl1: ovl@1400d000 {
|
||||
|
|
@ -1006,6 +1023,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
|
||||
};
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
|
|
@ -1016,6 +1034,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1400f000 {
|
||||
|
|
@ -1026,6 +1045,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
|
||||
};
|
||||
|
||||
rdma2: rdma@14010000 {
|
||||
|
|
@ -1036,6 +1056,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
||||
mediatek,larb = <&larb4>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
|
||||
};
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
|
|
@ -1046,6 +1067,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
|
||||
};
|
||||
|
||||
wdma1: wdma@14012000 {
|
||||
|
|
@ -1056,6 +1078,7 @@
|
|||
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
|
||||
};
|
||||
|
||||
color0: color@14013000 {
|
||||
|
|
@ -1064,6 +1087,7 @@
|
|||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
|
||||
};
|
||||
|
||||
color1: color@14014000 {
|
||||
|
|
@ -1072,6 +1096,7 @@
|
|||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
|
||||
};
|
||||
|
||||
aal@14015000 {
|
||||
|
|
@ -1080,6 +1105,7 @@
|
|||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
|
||||
};
|
||||
|
||||
gamma@14016000 {
|
||||
|
|
@ -1088,6 +1114,7 @@
|
|||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
|
||||
};
|
||||
|
||||
merge@14017000 {
|
||||
|
|
@ -1193,6 +1220,8 @@
|
|||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
|
||||
<CMDQ_EVENT_MUTEX1_STREAM_EOF>;
|
||||
};
|
||||
|
||||
larb0: larb@14021000 {
|
||||
|
|
@ -1437,4 +1466,3 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@
|
|||
reg = <0x000>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <741>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -85,7 +85,7 @@
|
|||
reg = <0x001>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <741>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -96,7 +96,7 @@
|
|||
reg = <0x002>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <741>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -107,7 +107,7 @@
|
|||
reg = <0x003>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <741>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
|
||||
dynamic-power-coefficient = <84>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -118,7 +118,7 @@
|
|||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
|
||||
dynamic-power-coefficient = <211>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -129,7 +129,7 @@
|
|||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
|
||||
dynamic-power-coefficient = <211>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -140,7 +140,7 @@
|
|||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
|
||||
dynamic-power-coefficient = <211>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -151,7 +151,7 @@
|
|||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
capacity-dmips-mhz = <1024>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
|
||||
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
|
||||
dynamic-power-coefficient = <211>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
|
@ -168,7 +168,15 @@
|
|||
min-residency-us = <800>;
|
||||
};
|
||||
|
||||
CLUSTER_SLEEP: cluster-sleep {
|
||||
CLUSTER_SLEEP0: cluster-sleep@0 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010001>;
|
||||
entry-latency-us = <250>;
|
||||
exit-latency-us = <400>;
|
||||
min-residency-us = <1000>;
|
||||
};
|
||||
CLUSTER_SLEEP1: cluster-sleep@1 {
|
||||
compatible = "arm,idle-state";
|
||||
local-timer-stop;
|
||||
arm,psci-suspend-param = <0x01010001>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue