sh: fix the TMU code to allow a fully running NO_HZ system
This patch fixes the TMU code to allow NO_HZ to work on sh Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Francesco Virlinzi
Paul Mundt
parent
b6ad1e8c3f
commit
61c66387e6
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@ -28,43 +28,90 @@
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#define TMU_TOCR_INIT 0x00
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#define TMU_TCR_INIT 0x0020
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#define TMU0 (0)
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#define TMU1 (1)
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static inline void _tmu_start(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_set_irq(int tmu_num, int enabled)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
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}
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static inline void _tmu_stop(int tmu_num)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
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}
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static inline void _tmu_clear_status(int tmu_num)
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{
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register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
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/* Clear UNF bit */
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ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
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}
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static inline unsigned long _tmu_read(int tmu_num)
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{
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return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
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}
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static int tmu_timer_start(void)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR);
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_tmu_start(TMU0);
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_tmu_start(TMU1);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload)
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static int tmu_timer_stop(void)
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{
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ctrl_outl(interval, TMU0_TCNT);
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_tmu_stop(TMU0);
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_tmu_stop(TMU1);
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_tmu_clear_status(TMU0);
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return 0;
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}
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/*
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* also when the module_clk is scaled the TMU1
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* will show the same frequency
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*/
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static int tmus_are_scaled;
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static cycle_t tmu_timer_read(void)
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{
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return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
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}
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static unsigned long tmu_latest_interval[3];
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static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
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{
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unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
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unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
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_tmu_stop(tmu_num);
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ctrl_outl(interval, tmu_tcnt);
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tmu_latest_interval[tmu_num] = interval;
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/*
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* TCNT reloads from TCOR on underflow, clear it if we don't
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* intend to auto-reload
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*/
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if (reload)
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ctrl_outl(interval, TMU0_TCOR);
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else
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ctrl_outl(0, TMU0_TCOR);
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ctrl_outl( reload ? interval : 0 , tmu_tcor);
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tmu_timer_start();
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}
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static int tmu_timer_stop(void)
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{
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ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR);
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return 0;
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}
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static cycle_t tmu_timer_read(void)
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{
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return ~ctrl_inl(TMU1_TCNT);
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_tmu_start(tmu_num);
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}
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static int tmu_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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tmu0_timer_set_interval(cycles, 1);
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tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_set_irq(TMU0,1);
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return 0;
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}
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@ -96,12 +143,8 @@ static struct clock_event_device tmu0_clockevent = {
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static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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{
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struct clock_event_device *evt = &tmu0_clockevent;
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unsigned long timer_status;
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/* Clear UNF bit */
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timer_status = ctrl_inw(TMU0_TCR);
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timer_status &= ~0x100;
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ctrl_outw(timer_status, TMU0_TCR);
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_tmu_clear_status(TMU0);
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_tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
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evt->event_handler(evt);
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@ -109,56 +152,73 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
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}
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static struct irqaction tmu0_irq = {
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.name = "periodic timer",
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.name = "periodic/oneshot timer",
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.handler = tmu_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.mask = CPU_MASK_NONE,
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};
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static void tmu0_clk_init(struct clk *clk)
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static void __init tmu_clk_init(struct clk *clk)
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{
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u8 divisor = TMU_TCR_INIT & 0x7;
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ctrl_outw(TMU_TCR_INIT, TMU0_TCR);
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clk->rate = clk->parent->rate / (4 << (divisor << 1));
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u8 divisor = TMU_TCR_INIT & 0x7;
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int tmu_num = clk->name[3]-'0';
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ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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}
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static void tmu0_clk_recalc(struct clk *clk)
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static void tmu_clk_recalc(struct clk *clk)
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{
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u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
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clk->rate = clk->parent->rate / (4 << (divisor << 1));
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int tmu_num = clk->name[3]-'0';
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unsigned long prev_rate = clk_get_rate(clk);
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unsigned long flags;
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u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
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clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
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if(prev_rate==clk_get_rate(clk))
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return;
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if(tmu_num)
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return; /* No more work on TMU1 */
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local_irq_save(flags);
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tmus_are_scaled = (prev_rate > clk->rate);
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_tmu_stop(TMU0);
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tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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tmu0_clockevent.max_delta_ns =
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clockevent_delta2ns(-1, &tmu0_clockevent);
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tmu0_clockevent.min_delta_ns =
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clockevent_delta2ns(1, &tmu0_clockevent);
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if (tmus_are_scaled)
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tmu_latest_interval[TMU0] >>= 1;
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else
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tmu_latest_interval[TMU0] <<= 1;
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tmu_timer_set_interval(TMU0,
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tmu_latest_interval[TMU0],
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tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
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_tmu_start(TMU0);
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local_irq_restore(flags);
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}
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static struct clk_ops tmu0_clk_ops = {
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.init = tmu0_clk_init,
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.recalc = tmu0_clk_recalc,
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static struct clk_ops tmu_clk_ops = {
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.init = tmu_clk_init,
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.recalc = tmu_clk_recalc,
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};
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static struct clk tmu0_clk = {
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.name = "tmu0_clk",
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.ops = &tmu0_clk_ops,
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};
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static void tmu1_clk_init(struct clk *clk)
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{
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u8 divisor = TMU_TCR_INIT & 0x7;
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ctrl_outw(divisor, TMU1_TCR);
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clk->rate = clk->parent->rate / (4 << (divisor << 1));
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}
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static void tmu1_clk_recalc(struct clk *clk)
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{
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u8 divisor = ctrl_inw(TMU1_TCR) & 0x7;
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clk->rate = clk->parent->rate / (4 << (divisor << 1));
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}
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static struct clk_ops tmu1_clk_ops = {
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.init = tmu1_clk_init,
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.recalc = tmu1_clk_recalc,
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.ops = &tmu_clk_ops,
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};
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static struct clk tmu1_clk = {
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.name = "tmu1_clk",
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.ops = &tmu1_clk_ops,
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.ops = &tmu_clk_ops,
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};
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static int tmu_timer_init(void)
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@ -189,11 +249,12 @@ static int tmu_timer_init(void)
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frequency = clk_get_rate(&tmu0_clk);
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interval = (frequency + HZ / 2) / HZ;
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sh_hpt_frequency = clk_get_rate(&tmu1_clk);
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ctrl_outl(~0, TMU1_TCNT);
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ctrl_outl(~0, TMU1_TCOR);
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tmu_timer_set_interval(TMU0,interval, 1);
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tmu_timer_set_interval(TMU1,~0,1);
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tmu0_timer_set_interval(interval, 1);
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_tmu_start(TMU1);
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sh_hpt_frequency = clk_get_rate(&tmu1_clk);
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tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
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tmu0_clockevent.shift);
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