nios2: Add Max10 device tree
Max10 is a FPGA device. This patch adds Nios2 support for Max10. This device tree is based on Max10 hardware reference design. Signed-off-by: Chee Nouk Phoon <cnphoon@altera.com> Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Chee Nouk Phoon
Ley Foon Tan
parent
0094dc40a9
commit
61c610ec61
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/*
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* Copyright (C) 2015 Altera Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/ {
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model = "Altera NiosII Max10";
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compatible = "altr,niosii-max10";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "altr,nios2-1.1";
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reg = <0x00000000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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altr,exception-addr = <0xc8000120>;
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altr,fast-tlb-miss-addr = <0xc0000100>;
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altr,has-div = <1>;
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altr,has-initda = <1>;
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altr,has-mmu = <1>;
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altr,has-mul = <1>;
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altr,implementation = "fast";
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altr,pid-num-bits = <8>;
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altr,reset-addr = <0xd4000000>;
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altr,tlb-num-entries = <256>;
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altr,tlb-num-ways = <16>;
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altr,tlb-ptr-sz = <8>;
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clock-frequency = <75000000>;
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dcache-line-size = <32>;
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dcache-size = <32768>;
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icache-line-size = <32>;
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icache-size = <32768>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x08000000 0x08000000>,
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<0x00000000 0x00000400>;
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};
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sopc0: sopc@0 {
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device_type = "soc";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "altr,avalon", "simple-bus";
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bus-frequency = <75000000>;
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jtag_uart: serial@18001530 {
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compatible = "altr,juart-1.0";
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reg = <0x18001530 0x00000008>;
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interrupt-parent = <&cpu>;
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interrupts = <7>;
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};
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a_16550_uart_0: serial@18001600 {
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compatible = "altr,16550-FIFO32", "ns16550a";
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reg = <0x18001600 0x00000200>;
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interrupt-parent = <&cpu>;
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interrupts = <1>;
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auto-flow-control = <1>;
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clock-frequency = <50000000>;
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fifo-size = <32>;
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reg-io-width = <4>;
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reg-shift = <2>;
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};
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sysid: sysid@18001528 {
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compatible = "altr,sysid-1.0";
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reg = <0x18001528 0x00000008>;
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id = <4207856382>;
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timestamp = <1431309290>;
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};
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rgmii_0_eth_tse_0: ethernet@400 {
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compatible = "altr,tse-msgdma-1.0", "altr,tse-1.0";
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reg = <0x00000400 0x00000400>,
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<0x00000820 0x00000020>,
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<0x00000800 0x00000020>,
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<0x000008c0 0x00000008>,
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<0x00000840 0x00000020>,
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<0x00000860 0x00000020>;
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reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
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interrupt-parent = <&cpu>;
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interrupts = <2 3>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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address-bits = <48>;
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max-frame-size = <1518>;
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local-mac-address = [00 00 00 00 00 00];
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altr,has-supplementary-unicast;
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altr,enable-sup-addr = <1>;
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altr,has-hash-multicast-filter;
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altr,enable-hash = <1>;
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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rgmii_0_eth_tse_0_mdio: mdio {
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compatible = "altr,tse-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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device_type = "ethernet-phy";
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};
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};
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};
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enet_pll: clock@0 {
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compatible = "altr,pll-1.0";
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#clock-cells = <1>;
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enet_pll_c0: enet_pll_c0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "enet_pll-c0";
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};
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enet_pll_c1: enet_pll_c1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "enet_pll-c1";
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};
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enet_pll_c2: enet_pll_c2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <2500000>;
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clock-output-names = "enet_pll-c2";
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};
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};
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sys_pll: clock@1 {
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compatible = "altr,pll-1.0";
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#clock-cells = <1>;
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sys_pll_c0: sys_pll_c0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sys_pll-c0";
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};
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sys_pll_c1: sys_pll_c1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "sys_pll-c1";
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};
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sys_pll_c2: sys_pll_c2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <75000000>;
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clock-output-names = "sys_pll-c2";
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};
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};
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sys_clk_timer: timer@18001440 {
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compatible = "altr,timer-1.0";
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reg = <0x18001440 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <0>;
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clock-frequency = <75000000>;
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};
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led_pio: gpio@180014d0 {
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compatible = "altr,pio-1.0";
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reg = <0x180014d0 0x00000010>;
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altr,gpio-bank-width = <4>;
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resetvalue = <15>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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button_pio: gpio@180014c0 {
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compatible = "altr,pio-1.0";
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reg = <0x180014c0 0x00000010>;
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interrupt-parent = <&cpu>;
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interrupts = <6>;
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altr,gpio-bank-width = <3>;
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altr,interrupt-type = <2>;
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edge_type = <1>;
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level_trigger = <0>;
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resetvalue = <0>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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sys_clk_timer_1: timer@880 {
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compatible = "altr,timer-1.0";
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reg = <0x00000880 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <5>;
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clock-frequency = <75000000>;
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};
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fpga_leds: leds {
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compatible = "gpio-leds";
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led_fpga0: fpga0 {
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label = "fpga_led0";
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gpios = <&led_pio 0 1>;
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};
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led_fpga1: fpga1 {
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label = "fpga_led1";
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gpios = <&led_pio 1 1>;
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};
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led_fpga2: fpga2 {
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label = "fpga_led2";
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gpios = <&led_pio 2 1>;
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};
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led_fpga3: fpga3 {
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label = "fpga_led3";
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gpios = <&led_pio 3 1>;
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};
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};
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};
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chosen {
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bootargs = "debug console=ttyS0,115200";
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};
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};
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