dmaengine: xilinx_dma: commonize DMA copy size calculation
This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches. Suggested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -425,6 +425,7 @@ struct xilinx_dma_config {
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* @rxs_clk: DMA s2mm stream clock
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* @nr_channels: Number of channels DMA device supports
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* @chan_id: DMA channel identifier
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* @max_buffer_len: Max buffer length
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*/
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struct xilinx_dma_device {
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void __iomem *regs;
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@ -444,6 +445,7 @@ struct xilinx_dma_device {
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struct clk *rxs_clk;
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u32 nr_channels;
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u32 chan_id;
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u32 max_buffer_len;
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};
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/* Macros */
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@ -959,6 +961,25 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan)
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return 0;
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}
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/**
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* xilinx_dma_calc_copysize - Calculate the amount of data to copy
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* @chan: Driver specific DMA channel
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* @size: Total data that needs to be copied
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* @done: Amount of data that has been already copied
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*
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* Return: Amount of data that has to be copied
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*/
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static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan,
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int size, int done)
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{
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size_t copy;
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copy = min_t(size_t, size - done,
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chan->xdev->max_buffer_len);
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return copy;
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}
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/**
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* xilinx_dma_tx_status - Get DMA transaction status
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* @dchan: DMA channel
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@ -992,7 +1013,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
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list_for_each_entry(segment, &desc->segments, node) {
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hw = &segment->hw;
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residue += (hw->control - hw->status) &
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XILINX_DMA_MAX_TRANS_LEN;
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chan->xdev->max_buffer_len;
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}
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}
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spin_unlock_irqrestore(&chan->lock, flags);
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@ -1254,7 +1275,7 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
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/* Start the transfer */
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dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
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hw->control & XILINX_DMA_MAX_TRANS_LEN);
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hw->control & chan->xdev->max_buffer_len);
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}
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list_splice_tail_init(&chan->pending_list, &chan->active_list);
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@ -1357,7 +1378,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
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/* Start the transfer */
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dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
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hw->control & XILINX_DMA_MAX_TRANS_LEN);
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hw->control & chan->xdev->max_buffer_len);
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}
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list_splice_tail_init(&chan->pending_list, &chan->active_list);
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@ -1718,7 +1739,7 @@ xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst,
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struct xilinx_cdma_tx_segment *segment;
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struct xilinx_cdma_desc_hw *hw;
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if (!len || len > XILINX_DMA_MAX_TRANS_LEN)
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if (!len || len > chan->xdev->max_buffer_len)
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return NULL;
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desc = xilinx_dma_alloc_tx_descriptor(chan);
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@ -1808,8 +1829,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg(
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* Calculate the maximum number of bytes to transfer,
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* making sure it is less than the hw limit
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*/
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copy = min_t(size_t, sg_dma_len(sg) - sg_used,
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XILINX_DMA_MAX_TRANS_LEN);
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copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg),
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sg_used);
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hw = &segment->hw;
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/* Fill in the descriptor */
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@ -1913,8 +1934,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
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* Calculate the maximum number of bytes to transfer,
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* making sure it is less than the hw limit
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*/
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copy = min_t(size_t, period_len - sg_used,
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XILINX_DMA_MAX_TRANS_LEN);
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copy = xilinx_dma_calc_copysize(chan, period_len,
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sg_used);
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hw = &segment->hw;
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xilinx_axidma_buf(chan, hw, buf_addr, sg_used,
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period_len * i);
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@ -2628,6 +2649,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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/* Retrieve the DMA engine properties from the device tree */
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xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
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xdev->max_buffer_len = XILINX_DMA_MAX_TRANS_LEN;
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if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
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xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
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