amd64_edac: add F10h-and-later methods-p2
Borislav: - fix a wrong negation in f10_determine_base_addr_offset() - fix a wrong mask in f10_determine_base_addr_offset() which should select DctSelBaseAddr[31:11] and not [31:16] as it was before - remove StinkyIdentifiers, trivially simplify code. - fix/cleanup comments - fix function return value patterns Reviewed-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Doug Thompson
Borislav Petkov
parent
1afd3c98b5
commit
6163b5d4fb
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@ -1367,3 +1367,199 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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pvt->dram_limit[dram] =
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((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF);
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}
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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{
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int err = 0;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW,
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&pvt->dram_ctl_select_low);
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if (err) {
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debugf0("Reading F10_DCTL_SEL_LOW failed\n");
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} else {
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debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n",
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pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt));
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debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-"
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"sel-hi-range=%s\n",
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(dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"),
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(dct_dram_enabled(pvt) ? "Enabled" : "Disabled"),
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(dct_high_range_enabled(pvt) ? "Enabled" : "Disabled"));
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debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n",
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(dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"),
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(dct_memory_cleared(pvt) ? "True " : "False "),
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dct_sel_interleave_addr(pvt));
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}
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH,
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&pvt->dram_ctl_select_high);
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if (err)
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debugf0("Reading F10_DCTL_SEL_HIGH failed\n");
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}
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static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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int hi_range_sel, u32 intlv_en)
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{
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u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1;
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if (dct_ganging_enabled(pvt))
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cs = 0;
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else if (hi_range_sel)
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cs = dct_sel_high;
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else if (dct_interleave_enabled(pvt)) {
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if (dct_sel_interleave_addr(pvt) == 0)
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cs = sys_addr >> 6 & 1;
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else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) {
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temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2;
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if (dct_sel_interleave_addr(pvt) & 1)
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cs = (sys_addr >> 9 & 1) ^ temp;
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else
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cs = (sys_addr >> 6 & 1) ^ temp;
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} else if (intlv_en & 4)
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cs = sys_addr >> 15 & 1;
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else if (intlv_en & 2)
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cs = sys_addr >> 14 & 1;
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else if (intlv_en & 1)
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cs = sys_addr >> 13 & 1;
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else
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cs = sys_addr >> 12 & 1;
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} else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt))
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cs = ~dct_sel_high & 1;
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else
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cs = 0;
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return cs;
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}
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static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en)
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{
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if (intlv_en == 1)
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return 1;
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else if (intlv_en == 3)
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return 2;
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else if (intlv_en == 7)
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return 3;
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return 0;
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}
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static inline u64 f10_determine_base_addr_offset(u64 sys_addr, int hi_range_sel,
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u32 dct_sel_base_addr,
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u64 dct_sel_base_off,
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u32 hole_en, u32 hole_off,
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u64 dram_base)
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{
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u64 chan_off;
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if (hi_range_sel) {
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if (!(dct_sel_base_addr & 0xFFFFF800) &&
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(hole_en & 1) && (sys_addr >= 0x100000000ULL))
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chan_off = hole_off << 16;
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else
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chan_off = dct_sel_base_off;
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} else {
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if ((hole_en & 1) && (sys_addr >= 0x100000000ULL))
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chan_off = hole_off << 16;
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else
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chan_off = dram_base & 0xFFFFF8000000ULL;
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}
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return (sys_addr & 0x0000FFFFFFFFFFC0ULL) -
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(chan_off & 0x0000FFFFFF800000ULL);
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}
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/* Hack for the time being - Can we get this from BIOS?? */
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#define CH0SPARE_RANK 0
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#define CH1SPARE_RANK 1
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/*
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* checks if the csrow passed in is marked as SPARED, if so returns the new
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* spare row
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*/
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static inline int f10_process_possible_spare(int csrow,
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u32 cs, struct amd64_pvt *pvt)
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{
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u32 swap_done;
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u32 bad_dram_cs;
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/* Depending on channel, isolate respective SPARING info */
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if (cs) {
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swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare);
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bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare);
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if (swap_done && (csrow == bad_dram_cs))
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csrow = CH1SPARE_RANK;
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} else {
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swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare);
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bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare);
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if (swap_done && (csrow == bad_dram_cs))
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csrow = CH0SPARE_RANK;
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}
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return csrow;
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}
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/*
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* Iterate over the DRAM DCT "base" and "mask" registers looking for a
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* SystemAddr match on the specified 'ChannelSelect' and 'NodeID'
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*
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* Return:
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* -EINVAL: NOT FOUND
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* 0..csrow = Chip-Select Row
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*/
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static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
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{
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struct mem_ctl_info *mci;
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struct amd64_pvt *pvt;
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u32 cs_base, cs_mask;
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int cs_found = -EINVAL;
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int csrow;
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mci = mci_lookup[nid];
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if (!mci)
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return cs_found;
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pvt = mci->pvt_info;
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debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs);
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for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
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cs_base = amd64_get_dct_base(pvt, cs, csrow);
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if (!(cs_base & K8_DCSB_CS_ENABLE))
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continue;
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/*
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* We have an ENABLED CSROW, Isolate just the MASK bits of the
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* target: [28:19] and [13:5], which map to [36:27] and [21:13]
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* of the actual address.
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*/
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cs_base &= REV_F_F1Xh_DCSB_BASE_BITS;
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/*
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* Get the DCT Mask, and ENABLE the reserved bits: [18:16] and
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* [4:0] to become ON. Then mask off bits [28:0] ([36:8])
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*/
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cs_mask = amd64_get_dct_mask(pvt, cs, csrow);
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debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n",
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csrow, cs_base, cs_mask);
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cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF;
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debugf1(" Final CSMask=0x%x\n", cs_mask);
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debugf1(" (InputAddr & ~CSMask)=0x%x "
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"(CSBase & ~CSMask)=0x%x\n",
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(in_addr & ~cs_mask), (cs_base & ~cs_mask));
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if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) {
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cs_found = f10_process_possible_spare(csrow, cs, pvt);
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debugf1(" MATCH csrow=%d\n", cs_found);
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break;
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}
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}
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return cs_found;
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}
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