hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/ralf/upstream-linus 

* 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/ralf/upstream-linus:
  [MIPS] XSS1500: Fix compilation
  [MIPS] Bigsur: make defconfig more useful.
  [MIPS] Alchemy: work around clock misdetection on early Au1000
  [MIPS] Add missing 4KEC TLB refill handler
  [MIPS] BCM1480: Fix PCI/HT IO access
  [MIPS] Fix the installation condition of MIPS clocksource
  [MIPS] Check for GCC r10k-cache-barrier support
  [MIPS] I8253: Export i2853_lock to modules.
  [MIPS] VPE loader: Check result of memory allocation.
This commit is contained in:
Linus Torvalds 2008-04-01 11:31:31 -07:00
parent 0e45adb8f5 f9e8b78260
commit 61434392f7
14 changed files with 646 additions and 415 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/mips/Makefile
View File

@ -482,10 +482,13 @@ endif
# be 16kb aligned or the handling of the current variable will break.
# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
#
#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o
ifdef CONFIG_SGI_IP28
ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n)
$(error gcc doesn't support needed option -mr10k-cache-barrier=1)
endif
endif
core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28
#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28
load-$(CONFIG_SGI_IP28) += 0xa800000020004000
#

36
arch/mips/au1000/common/cputable.c
View File

@ -22,24 +22,24 @@ struct cpu_spec* cur_cpu_spec[NR_CPUS];
/* With some thought, we can probably use the mask to reduce the
* size of the table.
*/
struct cpu_spec cpu_specs[] = {
{ 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 },
{ 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 },
{ 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 },
{ 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 },
{ 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 },
{ 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 },
{ 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 },
{ 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 },
{ 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 },
{ 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 },
{ 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 },
{ 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
{ 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
{ 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
{ 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
{ 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 },
{ 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
struct cpu_spec cpu_specs[] = {
{ 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
{ 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
{ 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
{ 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
{ 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
{ 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
{ 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
{ 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
{ 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
{ 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
{ 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
{ 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
{ 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
{ 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
{ 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
{ 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
{ 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
};
void

13
arch/mips/au1000/common/setup.c
View File

@ -57,7 +57,7 @@ void __init plat_mem_setup(void)
{
struct cpu_spec *sp;
char *argptr;
unsigned long prid, cpupll, bclk = 1;
unsigned long prid, cpufreq, bclk = 1;
set_cpuspec();
sp = cur_cpu_spec[0];
@ -65,8 +65,15 @@ void __init plat_mem_setup(void)
board_setup(); /* board specific setup */
prid = read_c0_prid();
cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
if (sp->cpu_pll_wo)
#ifdef CONFIG_SOC_AU1000_FREQUENCY
cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
#else
cpufreq = 396;
#endif
else
cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
bclk = sp->cpu_bclk;
if (bclk)

26
arch/mips/au1000/common/time.c
View File

@ -209,18 +209,22 @@ unsigned long cal_r4koff(void)
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
au_writel(0, SYS_TOYWRITE);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
AU1000_SRC_CLK;
}
else {
/* The 32KHz oscillator isn't running, so assume there
* isn't one and grab the processor speed from the PLL.
* NOTE: some old silicon doesn't allow reading the PLL.
*/
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
} else
no_au1xxx_32khz = 1;
}
/*
* On early Au1000, sys_cpupll was write-only. Since these
* silicon versions of Au1000 are not sold by AMD, we don't bend
* over backwards trying to determine the frequency.
*/
if (cur_cpu_spec[0]->cpu_pll_wo)
#ifdef CONFIG_SOC_AU1000_FREQUENCY
cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
#else
cpu_speed = 396000000;
#endif
else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
mips_hpt_frequency = cpu_speed;
// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));

3
arch/mips/au1000/xxs1500/board_setup.c
View File

@ -33,11 +33,10 @@
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/keyboard.h>
#include <asm/mipsregs.h>
#include <asm/reboot.h>
#include <asm/pgtable.h>
#include <asm/au1000.h>
#include <asm/mach-au1x00/au1000.h>
void board_reset(void)
{

2
arch/mips/au1000/xxs1500/irqmap.c
View File

@ -45,7 +45,7 @@
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/au1000.h>
#include <asm/mach-au1x00/au1000.h>
struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},

921
arch/mips/configs/bigsur_defconfig
View File

File diff suppressed because it is too large Load Diff

1
arch/mips/kernel/i8253.c
View File

@ -15,6 +15,7 @@
#include <asm/time.h>
DEFINE_SPINLOCK(i8253_lock);
EXPORT_SYMBOL(i8253_lock);
/*
* Initialize the PIT timer.

2
arch/mips/kernel/time.c
View File

@ -157,6 +157,6 @@ void __init time_init(void)
{
plat_time_init();
if (mips_clockevent_init() || !cpu_has_mfc0_count_bug())
if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug())
init_mips_clocksource();
}

21
arch/mips/kernel/vpe.c
View File

@ -262,13 +262,21 @@ void dump_mtregs(void)
/* Find some VPE program space */
static void *alloc_progmem(unsigned long len)
{
void *addr;
#ifdef CONFIG_MIPS_VPE_LOADER_TOM
/* this means you must tell linux to use less memory than you physically have */
return pfn_to_kaddr(max_pfn);
/*
* This means you must tell Linux to use less memory than you
* physically have, for example by passing a mem= boot argument.
*/
addr = pfn_to_kaddr(max_pfn);
memset(addr, 0, len);
#else
// simple grab some mem for now
return kmalloc(len, GFP_KERNEL);
/* simple grab some mem for now */
addr = kzalloc(len, GFP_KERNEL);
#endif
return addr;
}
static void release_progmem(void *ptr)
@ -884,9 +892,10 @@ static int vpe_elfload(struct vpe * v)
}
v->load_addr = alloc_progmem(mod.core_size);
memset(v->load_addr, 0, mod.core_size);
if (!v->load_addr)
return -ENOMEM;
printk("VPE loader: loading to %p\n", v->load_addr);
pr_info("VPE loader: loading to %p\n", v->load_addr);
if (relocate) {
for (i = 0; i < hdr->e_shnum; i++) {

1
arch/mips/mm/tlbex.c
View File

@ -307,6 +307,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R12000:
case CPU_R14000:
case CPU_4KC:
case CPU_4KEC:
case CPU_SB1:
case CPU_SB1A:
case CPU_4KSC:

6
arch/mips/pci/pci-bcm1480.c
View File

@ -185,8 +185,8 @@ static struct resource bcm1480_mem_resource = {
static struct resource bcm1480_io_resource = {
.name = "BCM1480 PCI I/O",
.start = 0x2c000000UL,
.end = 0x2dffffffUL,
.start = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
.end = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES + 0x1ffffffUL,
.flags = IORESOURCE_IO,
};
@ -194,6 +194,7 @@ struct pci_controller bcm1480_controller = {
.pci_ops = &bcm1480_pci_ops,
.mem_resource = &bcm1480_mem_resource,
.io_resource = &bcm1480_io_resource,
.io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
};
@ -251,6 +252,7 @@ static int __init bcm1480_pcibios_init(void)
bcm1480_controller.io_map_base = (unsigned long)
ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536);
bcm1480_controller.io_map_base -= bcm1480_controller.io_offset;
set_io_port_base(bcm1480_controller.io_map_base);
isa_slot_offset = (unsigned long)
ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);

21
arch/mips/pci/pci-bcm1480ht.c
View File

@ -180,8 +180,8 @@ static struct resource bcm1480ht_mem_resource = {
static struct resource bcm1480ht_io_resource = {
.name = "BCM1480 HT I/O",
.start = 0x00000000UL,
.end = 0x01ffffffUL,
.start = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
.end = A_BCM1480_PHYS_HT_IO_MATCH_BYTES + 0x01ffffffUL,
.flags = IORESOURCE_IO,
};
@ -191,29 +191,22 @@ struct pci_controller bcm1480ht_controller = {
.io_resource = &bcm1480ht_io_resource,
.index = 1,
.get_busno = bcm1480ht_pcibios_get_busno,
.io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
};
static int __init bcm1480ht_pcibios_init(void)
{
uint32_t cmdreg;
ht_cfg_space = ioremap(A_BCM1480_PHYS_HT_CFG_MATCH_BITS, 16*1024*1024);
/*
* See if the PCI bus has been configured by the firmware.
*/
cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
PCI_COMMAND));
if (!(cmdreg & PCI_COMMAND_MASTER)) {
printk("HT: Skipping HT probe. Bus is not initialized.\n");
iounmap(ht_cfg_space);
return 1; /* XXX */
}
/* CFE doesn't always init all HT paths, so we always scan */
bcm1480ht_bus_status |= PCI_BUS_ENABLED;
ht_eoi_space = (unsigned long)
ioremap(A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES,
4 * 1024 * 1024);
bcm1480ht_controller.io_map_base = (unsigned long)
ioremap(A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 65536);
bcm1480ht_controller.io_map_base -= bcm1480ht_controller.io_offset;
register_pci_controller(&bcm1480ht_controller);

1
include/asm-mips/mach-au1x00/au1000.h
View File

@ -1786,6 +1786,7 @@ struct cpu_spec {
char *cpu_name;
unsigned char cpu_od; /* Set Config[OD] */
unsigned char cpu_bclk; /* Enable BCLK switching */
unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
};
extern struct cpu_spec cpu_specs[];