V4L/DVB: v4l: Add driver for Samsung S5P SoC video postprocessor
This driver exports a video device node per each camera interface/ video postprocessor (FIMC) device contained in Samsung S5P SoC series. The driver is based on v4l2-mem2mem framework. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Pawel Osciak <p.osciak@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sylwester Nawrocki
Mauro Carvalho Chehab
parent
70092c26dc
commit
5fd8f7388c
|
|
@ -240,6 +240,45 @@ colorspace <constant>V4L2_COLORSPACE_SRGB</constant>.</para>
|
|||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-BGR666">
|
||||
<entry><constant>V4L2_PIX_FMT_BGR666</constant></entry>
|
||||
<entry>'BGRH'</entry>
|
||||
<entry></entry>
|
||||
<entry>b<subscript>5</subscript></entry>
|
||||
<entry>b<subscript>4</subscript></entry>
|
||||
<entry>b<subscript>3</subscript></entry>
|
||||
<entry>b<subscript>2</subscript></entry>
|
||||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
<entry>g<subscript>5</subscript></entry>
|
||||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
<entry>g<subscript>2</subscript></entry>
|
||||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
<entry>r<subscript>5</subscript></entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
<entry>r<subscript>3</subscript></entry>
|
||||
<entry>r<subscript>2</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-BGR24">
|
||||
<entry><constant>V4L2_PIX_FMT_BGR24</constant></entry>
|
||||
<entry>'BGR3'</entry>
|
||||
|
|
@ -700,6 +739,45 @@ defined in error. Drivers may interpret them as in <xref
|
|||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
</row>
|
||||
<row id="V4L2-PIX-FMT-BGR666">
|
||||
<entry><constant>V4L2_PIX_FMT_BGR666</constant></entry>
|
||||
<entry>'BGRH'</entry>
|
||||
<entry></entry>
|
||||
<entry>b<subscript>5</subscript></entry>
|
||||
<entry>b<subscript>4</subscript></entry>
|
||||
<entry>b<subscript>3</subscript></entry>
|
||||
<entry>b<subscript>2</subscript></entry>
|
||||
<entry>b<subscript>1</subscript></entry>
|
||||
<entry>b<subscript>0</subscript></entry>
|
||||
<entry>g<subscript>5</subscript></entry>
|
||||
<entry>g<subscript>4</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>g<subscript>3</subscript></entry>
|
||||
<entry>g<subscript>2</subscript></entry>
|
||||
<entry>g<subscript>1</subscript></entry>
|
||||
<entry>g<subscript>0</subscript></entry>
|
||||
<entry>r<subscript>5</subscript></entry>
|
||||
<entry>r<subscript>4</subscript></entry>
|
||||
<entry>r<subscript>3</subscript></entry>
|
||||
<entry>r<subscript>2</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry>r<subscript>1</subscript></entry>
|
||||
<entry>r<subscript>0</subscript></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
<entry></entry>
|
||||
</row>
|
||||
<row><!-- id="V4L2-PIX-FMT-BGR24" -->
|
||||
<entry><constant>V4L2_PIX_FMT_BGR24</constant></entry>
|
||||
<entry>'BGR3'</entry>
|
||||
|
|
|
|||
|
|
@ -1016,4 +1016,13 @@ config VIDEO_MEM2MEM_TESTDEV
|
|||
This is a virtual test device for the memory-to-memory driver
|
||||
framework.
|
||||
|
||||
config VIDEO_SAMSUNG_S5P_FIMC
|
||||
tristate "Samsung S5P FIMC (video postprocessor) driver"
|
||||
depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
|
||||
select VIDEOBUF_DMA_CONTIG
|
||||
select V4L2_MEM2MEM_DEV
|
||||
help
|
||||
This is a v4l2 driver for the S5P camera interface
|
||||
(video postprocessor)
|
||||
|
||||
endif # V4L_MEM2MEM_DRIVERS
|
||||
|
|
|
|||
|
|
@ -163,6 +163,7 @@ obj-$(CONFIG_VIDEO_MX3) += mx3_camera.o
|
|||
obj-$(CONFIG_VIDEO_PXA27x) += pxa_camera.o
|
||||
obj-$(CONFIG_VIDEO_SH_MOBILE_CSI2) += sh_mobile_csi2.o
|
||||
obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o
|
||||
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
|
||||
|
||||
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
|
||||
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) := s5p-fimc.o
|
||||
s5p-fimc-y := fimc-core.o fimc-reg.o
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,465 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics
|
||||
*
|
||||
* Sylwester Nawrocki, <s.nawrocki@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef FIMC_CORE_H_
|
||||
#define FIMC_CORE_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <media/videobuf-core.h>
|
||||
#include <media/v4l2-device.h>
|
||||
#include <media/v4l2-mem2mem.h>
|
||||
#include <linux/videodev2.h>
|
||||
#include "regs-fimc.h"
|
||||
|
||||
#define err(fmt, args...) \
|
||||
printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
|
||||
|
||||
#ifdef DEBUG
|
||||
#define dbg(fmt, args...) \
|
||||
printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
|
||||
#else
|
||||
#define dbg(fmt, args...)
|
||||
#endif
|
||||
|
||||
#define ctx_m2m_get_frame(frame, ctx, type) do { \
|
||||
if (V4L2_BUF_TYPE_VIDEO_OUTPUT == (type)) { \
|
||||
frame = &(ctx)->s_frame; \
|
||||
} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == (type)) { \
|
||||
frame = &(ctx)->d_frame; \
|
||||
} else { \
|
||||
v4l2_err(&(ctx)->fimc_dev->m2m.v4l2_dev,\
|
||||
"Wrong buffer/video queue type (%d)\n", type); \
|
||||
return -EINVAL; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define NUM_FIMC_CLOCKS 2
|
||||
#define MODULE_NAME "s5p-fimc"
|
||||
#define FIMC_MAX_DEVS 3
|
||||
#define FIMC_MAX_OUT_BUFS 4
|
||||
#define SCALER_MAX_HRATIO 64
|
||||
#define SCALER_MAX_VRATIO 64
|
||||
|
||||
enum {
|
||||
ST_IDLE,
|
||||
ST_OUTDMA_RUN,
|
||||
ST_M2M_PEND,
|
||||
};
|
||||
|
||||
#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
|
||||
#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
|
||||
|
||||
enum fimc_datapath {
|
||||
FIMC_ITU_CAM_A,
|
||||
FIMC_ITU_CAM_B,
|
||||
FIMC_MIPI_CAM,
|
||||
FIMC_DMA,
|
||||
FIMC_LCDFIFO,
|
||||
FIMC_WRITEBACK
|
||||
};
|
||||
|
||||
enum fimc_color_fmt {
|
||||
S5P_FIMC_RGB565,
|
||||
S5P_FIMC_RGB666,
|
||||
S5P_FIMC_RGB888,
|
||||
S5P_FIMC_YCBCR420,
|
||||
S5P_FIMC_YCBCR422,
|
||||
S5P_FIMC_YCBYCR422,
|
||||
S5P_FIMC_YCRYCB422,
|
||||
S5P_FIMC_CBYCRY422,
|
||||
S5P_FIMC_CRYCBY422,
|
||||
S5P_FIMC_RGB30_LOCAL,
|
||||
S5P_FIMC_YCBCR444_LOCAL,
|
||||
S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
|
||||
S5P_FIMC_COLOR_MASK = 0x0F,
|
||||
};
|
||||
|
||||
/* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
|
||||
#define S5P_FIMC_OUT_CRYCBY S5P_CIOCTRL_ORDER422_CRYCBY
|
||||
#define S5P_FIMC_OUT_CBYCRY S5P_CIOCTRL_ORDER422_YCRYCB
|
||||
#define S5P_FIMC_OUT_YCRYCB S5P_CIOCTRL_ORDER422_CBYCRY
|
||||
#define S5P_FIMC_OUT_YCBYCR S5P_CIOCTRL_ORDER422_YCBYCR
|
||||
|
||||
/* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
|
||||
#define S5P_FIMC_IN_CRYCBY S5P_MSCTRL_ORDER422_CRYCBY
|
||||
#define S5P_FIMC_IN_CBYCRY S5P_MSCTRL_ORDER422_YCRYCB
|
||||
#define S5P_FIMC_IN_YCRYCB S5P_MSCTRL_ORDER422_CBYCRY
|
||||
#define S5P_FIMC_IN_YCBYCR S5P_MSCTRL_ORDER422_YCBYCR
|
||||
|
||||
/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
|
||||
#define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
|
||||
|
||||
/* The embedded image effect selection */
|
||||
#define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
|
||||
#define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
|
||||
#define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
|
||||
#define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
|
||||
#define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
|
||||
#define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
|
||||
|
||||
/* The hardware context state. */
|
||||
#define FIMC_PARAMS (1 << 0)
|
||||
#define FIMC_SRC_ADDR (1 << 1)
|
||||
#define FIMC_DST_ADDR (1 << 2)
|
||||
#define FIMC_SRC_FMT (1 << 3)
|
||||
#define FIMC_DST_FMT (1 << 4)
|
||||
|
||||
/* Image conversion flags */
|
||||
#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
|
||||
#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
|
||||
#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
|
||||
#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
|
||||
#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
|
||||
#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
|
||||
/* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
|
||||
#define FIMC_COLOR_RANGE_WIDE (0 << 3)
|
||||
/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
|
||||
#define FIMC_COLOR_RANGE_NARROW (1 << 3)
|
||||
|
||||
#define FLIP_NONE 0
|
||||
#define FLIP_X_AXIS 1
|
||||
#define FLIP_Y_AXIS 2
|
||||
#define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
|
||||
|
||||
/**
|
||||
* struct fimc_fmt - the driver's internal color format data
|
||||
* @name: format description
|
||||
* @fourcc: the fourcc code for this format
|
||||
* @color: the corresponding fimc_color_fmt
|
||||
* @depth: number of bits per pixel
|
||||
* @buff_cnt: number of physically non-contiguous data planes
|
||||
* @planes_cnt: number of physically contiguous data planes
|
||||
*/
|
||||
struct fimc_fmt {
|
||||
char *name;
|
||||
u32 fourcc;
|
||||
u32 color;
|
||||
u32 depth;
|
||||
u16 buff_cnt;
|
||||
u16 planes_cnt;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_dma_offset - pixel offset information for DMA
|
||||
* @y_h: y value horizontal offset
|
||||
* @y_v: y value vertical offset
|
||||
* @cb_h: cb value horizontal offset
|
||||
* @cb_v: cb value vertical offset
|
||||
* @cr_h: cr value horizontal offset
|
||||
* @cr_v: cr value vertical offset
|
||||
*/
|
||||
struct fimc_dma_offset {
|
||||
int y_h;
|
||||
int y_v;
|
||||
int cb_h;
|
||||
int cb_v;
|
||||
int cr_h;
|
||||
int cr_v;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_effect - the configuration data for the "Arbitrary" image effect
|
||||
* @type: effect type
|
||||
* @pat_cb: cr value when type is "arbitrary"
|
||||
* @pat_cr: cr value when type is "arbitrary"
|
||||
*/
|
||||
struct fimc_effect {
|
||||
u32 type;
|
||||
u8 pat_cb;
|
||||
u8 pat_cr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_scaler - the configuration data for FIMC inetrnal scaler
|
||||
*
|
||||
* @enabled: the flag set when the scaler is used
|
||||
* @hfactor: horizontal shift factor
|
||||
* @vfactor: vertical shift factor
|
||||
* @pre_hratio: horizontal ratio of the prescaler
|
||||
* @pre_vratio: vertical ratio of the prescaler
|
||||
* @pre_dst_width: the prescaler's destination width
|
||||
* @pre_dst_height: the prescaler's destination height
|
||||
* @scaleup_h: flag indicating scaling up horizontally
|
||||
* @scaleup_v: flag indicating scaling up vertically
|
||||
* @main_hratio: the main scaler's horizontal ratio
|
||||
* @main_vratio: the main scaler's vertical ratio
|
||||
* @real_width: source width - offset
|
||||
* @real_height: source height - offset
|
||||
* @copy_mode: flag set if one-to-one mode is used, i.e. no scaling
|
||||
* and color format conversion
|
||||
*/
|
||||
struct fimc_scaler {
|
||||
u32 enabled;
|
||||
u32 hfactor;
|
||||
u32 vfactor;
|
||||
u32 pre_hratio;
|
||||
u32 pre_vratio;
|
||||
u32 pre_dst_width;
|
||||
u32 pre_dst_height;
|
||||
u32 scaleup_h;
|
||||
u32 scaleup_v;
|
||||
u32 main_hratio;
|
||||
u32 main_vratio;
|
||||
u32 real_width;
|
||||
u32 real_height;
|
||||
u32 copy_mode;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_addr - the FIMC physical address set for DMA
|
||||
*
|
||||
* @y: luminance plane physical address
|
||||
* @cb: Cb plane physical address
|
||||
* @cr: Cr plane physical address
|
||||
*/
|
||||
struct fimc_addr {
|
||||
u32 y;
|
||||
u32 cb;
|
||||
u32 cr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_vid_buffer - the driver's video buffer
|
||||
* @vb: v4l videobuf buffer
|
||||
*/
|
||||
struct fimc_vid_buffer {
|
||||
struct videobuf_buffer vb;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_frame - input/output frame format properties
|
||||
*
|
||||
* @f_width: image full width (virtual screen size)
|
||||
* @f_height: image full height (virtual screen size)
|
||||
* @o_width: original image width as set by S_FMT
|
||||
* @o_height: original image height as set by S_FMT
|
||||
* @offs_h: image horizontal pixel offset
|
||||
* @offs_v: image vertical pixel offset
|
||||
* @width: image pixel width
|
||||
* @height: image pixel weight
|
||||
* @paddr: image frame buffer physical addresses
|
||||
* @buf_cnt: number of buffers depending on a color format
|
||||
* @size: image size in bytes
|
||||
* @color: color format
|
||||
* @dma_offset: DMA offset in bytes
|
||||
*/
|
||||
struct fimc_frame {
|
||||
u32 f_width;
|
||||
u32 f_height;
|
||||
u32 o_width;
|
||||
u32 o_height;
|
||||
u32 offs_h;
|
||||
u32 offs_v;
|
||||
u32 width;
|
||||
u32 height;
|
||||
u32 size;
|
||||
struct fimc_addr paddr;
|
||||
struct fimc_dma_offset dma_offset;
|
||||
struct fimc_fmt *fmt;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fimc_m2m_device - v4l2 memory-to-memory device data
|
||||
* @vfd: the video device node for v4l2 m2m mode
|
||||
* @v4l2_dev: v4l2 device for m2m mode
|
||||
* @m2m_dev: v4l2 memory-to-memory device data
|
||||
* @ctx: hardware context data
|
||||
* @refcnt: the reference counter
|
||||
*/
|
||||
struct fimc_m2m_device {
|
||||
struct video_device *vfd;
|
||||
struct v4l2_device v4l2_dev;
|
||||
struct v4l2_m2m_dev *m2m_dev;
|
||||
struct fimc_ctx *ctx;
|
||||
int refcnt;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct samsung_fimc_variant - camera interface variant information
|
||||
*
|
||||
* @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
|
||||
* @has_inp_rot: set if has input rotator
|
||||
* @has_out_rot: set if has output rotator
|
||||
* @min_inp_pixsize: minimum input pixel size
|
||||
* @min_out_pixsize: minimum output pixel size
|
||||
* @scaler_en_w: maximum input pixel width when the scaler is enabled
|
||||
* @scaler_dis_w: maximum input pixel width when the scaler is disabled
|
||||
* @in_rot_en_h: maximum input width when the input rotator is used
|
||||
* @in_rot_dis_w: maximum input width when the input rotator is used
|
||||
* @out_rot_en_w: maximum output width for the output rotator enabled
|
||||
* @out_rot_dis_w: maximum output width for the output rotator enabled
|
||||
*/
|
||||
struct samsung_fimc_variant {
|
||||
unsigned int pix_hoff:1;
|
||||
unsigned int has_inp_rot:1;
|
||||
unsigned int has_out_rot:1;
|
||||
|
||||
u16 min_inp_pixsize;
|
||||
u16 min_out_pixsize;
|
||||
u16 scaler_en_w;
|
||||
u16 scaler_dis_w;
|
||||
u16 in_rot_en_h;
|
||||
u16 in_rot_dis_w;
|
||||
u16 out_rot_en_w;
|
||||
u16 out_rot_dis_w;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct samsung_fimc_driverdata - per-device type driver data for init time.
|
||||
*
|
||||
* @variant: the variant information for this driver.
|
||||
* @dev_cnt: number of fimc sub-devices available in SoC
|
||||
*/
|
||||
struct samsung_fimc_driverdata {
|
||||
struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
|
||||
int devs_cnt;
|
||||
};
|
||||
|
||||
struct fimc_ctx;
|
||||
|
||||
/**
|
||||
* struct fimc_subdev - abstraction for a FIMC entity
|
||||
*
|
||||
* @slock: the spinlock protecting this data structure
|
||||
* @lock: the mutex protecting this data structure
|
||||
* @pdev: pointer to the FIMC platform device
|
||||
* @id: FIMC device index (0..2)
|
||||
* @clock[]: the clocks required for FIMC operation
|
||||
* @regs: the mapped hardware registers
|
||||
* @regs_res: the resource claimed for IO registers
|
||||
* @irq: interrupt number of the FIMC subdevice
|
||||
* @irqlock: spinlock protecting videbuffer queue
|
||||
* @m2m: memory-to-memory V4L2 device information
|
||||
* @state: the FIMC device state flags
|
||||
*/
|
||||
struct fimc_dev {
|
||||
spinlock_t slock;
|
||||
struct mutex lock;
|
||||
struct platform_device *pdev;
|
||||
struct samsung_fimc_variant *variant;
|
||||
int id;
|
||||
struct clk *clock[NUM_FIMC_CLOCKS];
|
||||
void __iomem *regs;
|
||||
struct resource *regs_res;
|
||||
int irq;
|
||||
spinlock_t irqlock;
|
||||
struct workqueue_struct *work_queue;
|
||||
struct fimc_m2m_device m2m;
|
||||
unsigned long state;
|
||||
};
|
||||
|
||||
/**
|
||||
* fimc_ctx - the device context data
|
||||
*
|
||||
* @lock: mutex protecting this data structure
|
||||
* @s_frame: source frame properties
|
||||
* @d_frame: destination frame properties
|
||||
* @out_order_1p: output 1-plane YCBCR order
|
||||
* @out_order_2p: output 2-plane YCBCR order
|
||||
* @in_order_1p input 1-plane YCBCR order
|
||||
* @in_order_2p: input 2-plane YCBCR order
|
||||
* @in_path: input mode (DMA or camera)
|
||||
* @out_path: output mode (DMA or FIFO)
|
||||
* @scaler: image scaler properties
|
||||
* @effect: image effect
|
||||
* @rotation: image clockwise rotation in degrees
|
||||
* @flip: image flip mode
|
||||
* @flags: an additional flags for image conversion
|
||||
* @state: flags to keep track of user configuration
|
||||
* @fimc_dev: the FIMC device this context applies to
|
||||
* @m2m_ctx: memory-to-memory device context
|
||||
*/
|
||||
struct fimc_ctx {
|
||||
spinlock_t slock;
|
||||
struct fimc_frame s_frame;
|
||||
struct fimc_frame d_frame;
|
||||
u32 out_order_1p;
|
||||
u32 out_order_2p;
|
||||
u32 in_order_1p;
|
||||
u32 in_order_2p;
|
||||
enum fimc_datapath in_path;
|
||||
enum fimc_datapath out_path;
|
||||
struct fimc_scaler scaler;
|
||||
struct fimc_effect effect;
|
||||
int rotation;
|
||||
u32 flip;
|
||||
u32 flags;
|
||||
u32 state;
|
||||
struct fimc_dev *fimc_dev;
|
||||
struct v4l2_m2m_ctx *m2m_ctx;
|
||||
};
|
||||
|
||||
|
||||
static inline int tiled_fmt(struct fimc_fmt *fmt)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_CIGCTRL);
|
||||
cfg |= S5P_CIGCTRL_IRQ_CLR;
|
||||
writel(cfg, dev->regs + S5P_CIGCTRL);
|
||||
}
|
||||
|
||||
static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_CISCCTRL);
|
||||
cfg |= S5P_CISCCTRL_SCALERSTART;
|
||||
writel(cfg, dev->regs + S5P_CISCCTRL);
|
||||
}
|
||||
|
||||
static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_CISCCTRL);
|
||||
cfg &= ~S5P_CISCCTRL_SCALERSTART;
|
||||
writel(cfg, dev->regs + S5P_CISCCTRL);
|
||||
}
|
||||
|
||||
static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
|
||||
cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
|
||||
writel(cfg, dev->regs + S5P_CIIMGCPT);
|
||||
}
|
||||
|
||||
static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_MSCTRL);
|
||||
cfg |= S5P_MSCTRL_ENVID;
|
||||
writel(cfg, dev->regs + S5P_MSCTRL);
|
||||
}
|
||||
|
||||
static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_MSCTRL);
|
||||
cfg &= ~S5P_MSCTRL_ENVID;
|
||||
writel(cfg, dev->regs + S5P_MSCTRL);
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------*/
|
||||
/* fimc-reg.c */
|
||||
void fimc_hw_reset(struct fimc_dev *dev);
|
||||
void fimc_hw_set_rotation(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_target_format(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
|
||||
void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
|
||||
void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
|
||||
void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_scaler(struct fimc_ctx *ctx);
|
||||
void fimc_hw_en_capture(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_effect(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_input_path(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_output_path(struct fimc_ctx *ctx);
|
||||
void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
|
||||
void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
|
||||
|
||||
#endif /* FIMC_CORE_H_ */
|
||||
|
|
@ -0,0 +1,527 @@
|
|||
/*
|
||||
* Register interface file for Samsung Camera Interface (FIMC) driver
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics
|
||||
*
|
||||
* Sylwester Nawrocki, s.nawrocki@samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "fimc-core.h"
|
||||
|
||||
|
||||
void fimc_hw_reset(struct fimc_dev *dev)
|
||||
{
|
||||
u32 cfg;
|
||||
|
||||
cfg = readl(dev->regs + S5P_CISRCFMT);
|
||||
cfg |= S5P_CISRCFMT_ITU601_8BIT;
|
||||
writel(cfg, dev->regs + S5P_CISRCFMT);
|
||||
|
||||
/* Software reset. */
|
||||
cfg = readl(dev->regs + S5P_CIGCTRL);
|
||||
cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
|
||||
writel(cfg, dev->regs + S5P_CIGCTRL);
|
||||
msleep(1);
|
||||
|
||||
cfg = readl(dev->regs + S5P_CIGCTRL);
|
||||
cfg &= ~S5P_CIGCTRL_SWRST;
|
||||
writel(cfg, dev->regs + S5P_CIGCTRL);
|
||||
|
||||
}
|
||||
|
||||
void fimc_hw_set_rotation(struct fimc_ctx *ctx)
|
||||
{
|
||||
u32 cfg, flip;
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
|
||||
cfg = readl(dev->regs + S5P_CITRGFMT);
|
||||
cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90);
|
||||
|
||||
flip = readl(dev->regs + S5P_MSCTRL);
|
||||
flip &= ~S5P_MSCTRL_FLIP_MASK;
|
||||
|
||||
/*
|
||||
* The input and output rotator cannot work simultaneously.
|
||||
* Use the output rotator in output DMA mode or the input rotator
|
||||
* in direct fifo output mode.
|
||||
*/
|
||||
if (ctx->rotation == 90 || ctx->rotation == 270) {
|
||||
if (ctx->out_path == FIMC_LCDFIFO) {
|
||||
cfg |= S5P_CITRGFMT_INROT90;
|
||||
if (ctx->rotation == 270)
|
||||
flip |= S5P_MSCTRL_FLIP_180;
|
||||
} else {
|
||||
cfg |= S5P_CITRGFMT_OUTROT90;
|
||||
if (ctx->rotation == 270)
|
||||
cfg |= S5P_CITRGFMT_FLIP_180;
|
||||
}
|
||||
} else if (ctx->rotation == 180) {
|
||||
if (ctx->out_path == FIMC_LCDFIFO)
|
||||
flip |= S5P_MSCTRL_FLIP_180;
|
||||
else
|
||||
cfg |= S5P_CITRGFMT_FLIP_180;
|
||||
}
|
||||
if (ctx->rotation == 180 || ctx->rotation == 270)
|
||||
writel(flip, dev->regs + S5P_MSCTRL);
|
||||
writel(cfg, dev->regs + S5P_CITRGFMT);
|
||||
}
|
||||
|
||||
static u32 fimc_hw_get_in_flip(u32 ctx_flip)
|
||||
{
|
||||
u32 flip = S5P_MSCTRL_FLIP_NORMAL;
|
||||
|
||||
switch (ctx_flip) {
|
||||
case FLIP_X_AXIS:
|
||||
flip = S5P_MSCTRL_FLIP_X_MIRROR;
|
||||
break;
|
||||
case FLIP_Y_AXIS:
|
||||
flip = S5P_MSCTRL_FLIP_Y_MIRROR;
|
||||
break;
|
||||
case FLIP_XY_AXIS:
|
||||
flip = S5P_MSCTRL_FLIP_180;
|
||||
break;
|
||||
}
|
||||
|
||||
return flip;
|
||||
}
|
||||
|
||||
static u32 fimc_hw_get_target_flip(u32 ctx_flip)
|
||||
{
|
||||
u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
|
||||
|
||||
switch (ctx_flip) {
|
||||
case FLIP_X_AXIS:
|
||||
flip = S5P_CITRGFMT_FLIP_X_MIRROR;
|
||||
break;
|
||||
case FLIP_Y_AXIS:
|
||||
flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
|
||||
break;
|
||||
case FLIP_XY_AXIS:
|
||||
flip = S5P_CITRGFMT_FLIP_180;
|
||||
break;
|
||||
case FLIP_NONE:
|
||||
break;
|
||||
|
||||
}
|
||||
return flip;
|
||||
}
|
||||
|
||||
void fimc_hw_set_target_format(struct fimc_ctx *ctx)
|
||||
{
|
||||
u32 cfg;
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_frame *frame = &ctx->d_frame;
|
||||
|
||||
dbg("w= %d, h= %d color: %d", frame->width,
|
||||
frame->height, frame->fmt->color);
|
||||
|
||||
cfg = readl(dev->regs + S5P_CITRGFMT);
|
||||
cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
|
||||
S5P_CITRGFMT_VSIZE_MASK);
|
||||
|
||||
switch (frame->fmt->color) {
|
||||
case S5P_FIMC_RGB565:
|
||||
case S5P_FIMC_RGB666:
|
||||
case S5P_FIMC_RGB888:
|
||||
cfg |= S5P_CITRGFMT_RGB;
|
||||
break;
|
||||
case S5P_FIMC_YCBCR420:
|
||||
cfg |= S5P_CITRGFMT_YCBCR420;
|
||||
break;
|
||||
case S5P_FIMC_YCBYCR422:
|
||||
case S5P_FIMC_YCRYCB422:
|
||||
case S5P_FIMC_CBYCRY422:
|
||||
case S5P_FIMC_CRYCBY422:
|
||||
if (frame->fmt->planes_cnt == 1)
|
||||
cfg |= S5P_CITRGFMT_YCBCR422_1P;
|
||||
else
|
||||
cfg |= S5P_CITRGFMT_YCBCR422;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
cfg |= S5P_CITRGFMT_HSIZE(frame->width);
|
||||
cfg |= S5P_CITRGFMT_VSIZE(frame->height);
|
||||
|
||||
if (ctx->rotation == 0) {
|
||||
cfg &= ~S5P_CITRGFMT_FLIP_MASK;
|
||||
cfg |= fimc_hw_get_target_flip(ctx->flip);
|
||||
}
|
||||
writel(cfg, dev->regs + S5P_CITRGFMT);
|
||||
|
||||
cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
|
||||
cfg |= (frame->width * frame->height);
|
||||
writel(cfg, dev->regs + S5P_CITAREA);
|
||||
}
|
||||
|
||||
static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_frame *frame = &ctx->d_frame;
|
||||
u32 cfg = 0;
|
||||
|
||||
if (ctx->rotation == 90 || ctx->rotation == 270) {
|
||||
cfg |= S5P_ORIG_SIZE_HOR(frame->f_height);
|
||||
cfg |= S5P_ORIG_SIZE_VER(frame->f_width);
|
||||
} else {
|
||||
cfg |= S5P_ORIG_SIZE_HOR(frame->f_width);
|
||||
cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
|
||||
}
|
||||
writel(cfg, dev->regs + S5P_ORGOSIZE);
|
||||
}
|
||||
|
||||
void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
|
||||
{
|
||||
u32 cfg;
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_frame *frame = &ctx->d_frame;
|
||||
struct fimc_dma_offset *offset = &frame->dma_offset;
|
||||
|
||||
/* Set the input dma offsets. */
|
||||
cfg = 0;
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->y_v);
|
||||
writel(cfg, dev->regs + S5P_CIOYOFF);
|
||||
|
||||
cfg = 0;
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
|
||||
writel(cfg, dev->regs + S5P_CIOCBOFF);
|
||||
|
||||
cfg = 0;
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
|
||||
writel(cfg, dev->regs + S5P_CIOCROFF);
|
||||
|
||||
fimc_hw_set_out_dma_size(ctx);
|
||||
|
||||
/* Configure chroma components order. */
|
||||
cfg = readl(dev->regs + S5P_CIOCTRL);
|
||||
|
||||
cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
|
||||
S5P_CIOCTRL_YCBCR_PLANE_MASK);
|
||||
|
||||
if (frame->fmt->planes_cnt == 1)
|
||||
cfg |= ctx->out_order_1p;
|
||||
else if (frame->fmt->planes_cnt == 2)
|
||||
cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
|
||||
else if (frame->fmt->planes_cnt == 3)
|
||||
cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
|
||||
|
||||
writel(cfg, dev->regs + S5P_CIOCTRL);
|
||||
}
|
||||
|
||||
static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
|
||||
{
|
||||
u32 cfg = readl(dev->regs + S5P_ORGISIZE);
|
||||
if (enable)
|
||||
cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
|
||||
else
|
||||
cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
|
||||
writel(cfg, dev->regs + S5P_ORGISIZE);
|
||||
}
|
||||
|
||||
void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 cfg;
|
||||
|
||||
spin_lock_irqsave(&dev->slock, flags);
|
||||
|
||||
cfg = readl(dev->regs + S5P_CIOCTRL);
|
||||
if (enable)
|
||||
cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
|
||||
else
|
||||
cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
|
||||
writel(cfg, dev->regs + S5P_CIOCTRL);
|
||||
|
||||
spin_unlock_irqrestore(&dev->slock, flags);
|
||||
}
|
||||
|
||||
void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_scaler *sc = &ctx->scaler;
|
||||
u32 cfg = 0, shfactor;
|
||||
|
||||
shfactor = 10 - (sc->hfactor + sc->vfactor);
|
||||
|
||||
cfg |= S5P_CISCPRERATIO_SHFACTOR(shfactor);
|
||||
cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
|
||||
cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
|
||||
writel(cfg, dev->regs + S5P_CISCPRERATIO);
|
||||
|
||||
cfg = 0;
|
||||
cfg |= S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
|
||||
cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
|
||||
writel(cfg, dev->regs + S5P_CISCPREDST);
|
||||
}
|
||||
|
||||
void fimc_hw_set_scaler(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_scaler *sc = &ctx->scaler;
|
||||
struct fimc_frame *src_frame = &ctx->s_frame;
|
||||
struct fimc_frame *dst_frame = &ctx->d_frame;
|
||||
u32 cfg = 0;
|
||||
|
||||
if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
|
||||
cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
|
||||
|
||||
if (!sc->enabled)
|
||||
cfg |= S5P_CISCCTRL_SCALERBYPASS;
|
||||
|
||||
if (sc->scaleup_h)
|
||||
cfg |= S5P_CISCCTRL_SCALEUP_H;
|
||||
|
||||
if (sc->scaleup_v)
|
||||
cfg |= S5P_CISCCTRL_SCALEUP_V;
|
||||
|
||||
if (sc->copy_mode)
|
||||
cfg |= S5P_CISCCTRL_ONE2ONE;
|
||||
|
||||
|
||||
if (ctx->in_path == FIMC_DMA) {
|
||||
if (src_frame->fmt->color == S5P_FIMC_RGB565)
|
||||
cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
|
||||
else if (src_frame->fmt->color == S5P_FIMC_RGB666)
|
||||
cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
|
||||
else if (src_frame->fmt->color == S5P_FIMC_RGB888)
|
||||
cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
|
||||
}
|
||||
|
||||
if (ctx->out_path == FIMC_DMA) {
|
||||
if (dst_frame->fmt->color == S5P_FIMC_RGB565)
|
||||
cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
|
||||
else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
|
||||
cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
|
||||
else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
|
||||
cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
|
||||
} else {
|
||||
cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
|
||||
|
||||
if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
|
||||
cfg |= S5P_CISCCTRL_INTERLACE;
|
||||
}
|
||||
|
||||
dbg("main_hratio= 0x%X main_vratio= 0x%X",
|
||||
sc->main_hratio, sc->main_vratio);
|
||||
|
||||
cfg |= S5P_CISCCTRL_SC_HORRATIO(sc->main_hratio);
|
||||
cfg |= S5P_CISCCTRL_SC_VERRATIO(sc->main_vratio);
|
||||
|
||||
writel(cfg, dev->regs + S5P_CISCCTRL);
|
||||
}
|
||||
|
||||
void fimc_hw_en_capture(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
u32 cfg;
|
||||
|
||||
cfg = readl(dev->regs + S5P_CIIMGCPT);
|
||||
/* One shot mode for output DMA or freerun for FIFO. */
|
||||
if (ctx->out_path == FIMC_DMA)
|
||||
cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE;
|
||||
else
|
||||
cfg &= ~S5P_CIIMGCPT_CPT_FREN_ENABLE;
|
||||
|
||||
if (ctx->scaler.enabled)
|
||||
cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
|
||||
|
||||
writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
|
||||
}
|
||||
|
||||
void fimc_hw_set_effect(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_effect *effect = &ctx->effect;
|
||||
u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
|
||||
|
||||
cfg |= effect->type;
|
||||
|
||||
if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
|
||||
cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
|
||||
cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
|
||||
}
|
||||
|
||||
writel(cfg, dev->regs + S5P_CIIMGEFF);
|
||||
}
|
||||
|
||||
static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_frame *frame = &ctx->s_frame;
|
||||
u32 cfg_o = 0;
|
||||
u32 cfg_r = 0;
|
||||
|
||||
if (FIMC_LCDFIFO == ctx->out_path)
|
||||
cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
|
||||
|
||||
cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
|
||||
cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
|
||||
cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
|
||||
cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
|
||||
|
||||
writel(cfg_o, dev->regs + S5P_ORGISIZE);
|
||||
writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
|
||||
}
|
||||
|
||||
void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
struct fimc_frame *frame = &ctx->s_frame;
|
||||
struct fimc_dma_offset *offset = &frame->dma_offset;
|
||||
u32 cfg = 0;
|
||||
|
||||
/* Set the pixel offsets. */
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->y_v);
|
||||
writel(cfg, dev->regs + S5P_CIIYOFF);
|
||||
|
||||
cfg = 0;
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
|
||||
writel(cfg, dev->regs + S5P_CIICBOFF);
|
||||
|
||||
cfg = 0;
|
||||
cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
|
||||
cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
|
||||
writel(cfg, dev->regs + S5P_CIICROFF);
|
||||
|
||||
/* Input original and real size. */
|
||||
fimc_hw_set_in_dma_size(ctx);
|
||||
|
||||
/* Autoload is used currently only in FIFO mode. */
|
||||
fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
|
||||
|
||||
/* Set the input DMA to process single frame only. */
|
||||
cfg = readl(dev->regs + S5P_MSCTRL);
|
||||
cfg &= ~(S5P_MSCTRL_FLIP_MASK
|
||||
| S5P_MSCTRL_INFORMAT_MASK
|
||||
| S5P_MSCTRL_IN_BURST_COUNT_MASK
|
||||
| S5P_MSCTRL_INPUT_MASK
|
||||
| S5P_MSCTRL_C_INT_IN_MASK
|
||||
| S5P_MSCTRL_2P_IN_ORDER_MASK);
|
||||
|
||||
cfg |= (S5P_MSCTRL_FRAME_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY);
|
||||
|
||||
switch (frame->fmt->color) {
|
||||
case S5P_FIMC_RGB565:
|
||||
case S5P_FIMC_RGB666:
|
||||
case S5P_FIMC_RGB888:
|
||||
cfg |= S5P_MSCTRL_INFORMAT_RGB;
|
||||
break;
|
||||
case S5P_FIMC_YCBCR420:
|
||||
cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
|
||||
|
||||
if (frame->fmt->planes_cnt == 2)
|
||||
cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
|
||||
else
|
||||
cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
|
||||
|
||||
break;
|
||||
case S5P_FIMC_YCBYCR422:
|
||||
case S5P_FIMC_YCRYCB422:
|
||||
case S5P_FIMC_CBYCRY422:
|
||||
case S5P_FIMC_CRYCBY422:
|
||||
if (frame->fmt->planes_cnt == 1) {
|
||||
cfg |= ctx->in_order_1p
|
||||
| S5P_MSCTRL_INFORMAT_YCBCR422_1P;
|
||||
} else {
|
||||
cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
|
||||
|
||||
if (frame->fmt->planes_cnt == 2)
|
||||
cfg |= ctx->in_order_2p
|
||||
| S5P_MSCTRL_C_INT_IN_2PLANE;
|
||||
else
|
||||
cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Input DMA flip mode (and rotation).
|
||||
* Do not allow simultaneous rotation and flipping.
|
||||
*/
|
||||
if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
|
||||
cfg |= fimc_hw_get_in_flip(ctx->flip);
|
||||
|
||||
writel(cfg, dev->regs + S5P_MSCTRL);
|
||||
|
||||
/* Input/output DMA linear/tiled mode. */
|
||||
cfg = readl(dev->regs + S5P_CIDMAPARAM);
|
||||
cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
|
||||
|
||||
if (tiled_fmt(ctx->s_frame.fmt))
|
||||
cfg |= S5P_CIDMAPARAM_R_64X32;
|
||||
|
||||
if (tiled_fmt(ctx->d_frame.fmt))
|
||||
cfg |= S5P_CIDMAPARAM_W_64X32;
|
||||
|
||||
writel(cfg, dev->regs + S5P_CIDMAPARAM);
|
||||
}
|
||||
|
||||
|
||||
void fimc_hw_set_input_path(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
|
||||
u32 cfg = readl(dev->regs + S5P_MSCTRL);
|
||||
cfg &= ~S5P_MSCTRL_INPUT_MASK;
|
||||
|
||||
if (ctx->in_path == FIMC_DMA)
|
||||
cfg |= S5P_MSCTRL_INPUT_MEMORY;
|
||||
else
|
||||
cfg |= S5P_MSCTRL_INPUT_EXTCAM;
|
||||
|
||||
writel(cfg, dev->regs + S5P_MSCTRL);
|
||||
}
|
||||
|
||||
void fimc_hw_set_output_path(struct fimc_ctx *ctx)
|
||||
{
|
||||
struct fimc_dev *dev = ctx->fimc_dev;
|
||||
|
||||
u32 cfg = readl(dev->regs + S5P_CISCCTRL);
|
||||
cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
|
||||
if (ctx->out_path == FIMC_LCDFIFO)
|
||||
cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
|
||||
writel(cfg, dev->regs + S5P_CISCCTRL);
|
||||
}
|
||||
|
||||
void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
|
||||
{
|
||||
u32 cfg = 0;
|
||||
|
||||
cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
|
||||
cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
|
||||
writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
|
||||
|
||||
writel(paddr->y, dev->regs + S5P_CIIYSA0);
|
||||
writel(paddr->cb, dev->regs + S5P_CIICBSA0);
|
||||
writel(paddr->cr, dev->regs + S5P_CIICRSA0);
|
||||
|
||||
cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
|
||||
writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
|
||||
}
|
||||
|
||||
void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
|
||||
{
|
||||
int i;
|
||||
/* Set all the output register sets to point to single video buffer. */
|
||||
for (i = 0; i < FIMC_MAX_OUT_BUFS; i++) {
|
||||
writel(paddr->y, dev->regs + S5P_CIOYSA(i));
|
||||
writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
|
||||
writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,293 @@
|
|||
/*
|
||||
* Register definition file for Samsung Camera Interface (FIMC) driver
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef REGS_FIMC_H_
|
||||
#define REGS_FIMC_H_
|
||||
|
||||
#define S5P_CIOYSA(__x) (0x18 + (__x) * 4)
|
||||
#define S5P_CIOCBSA(__x) (0x28 + (__x) * 4)
|
||||
#define S5P_CIOCRSA(__x) (0x38 + (__x) * 4)
|
||||
|
||||
/* Input source format */
|
||||
#define S5P_CISRCFMT 0x00
|
||||
#define S5P_CISRCFMT_ITU601_8BIT (1 << 31)
|
||||
#define S5P_CISRCFMT_ITU601_16BIT (1 << 29)
|
||||
#define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14)
|
||||
#define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14)
|
||||
#define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14)
|
||||
#define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14)
|
||||
#define S5P_CISRCFMT_HSIZE(x) ((x) << 16)
|
||||
#define S5P_CISRCFMT_VSIZE(x) ((x) << 0)
|
||||
|
||||
/* Window offset */
|
||||
#define S5P_CIWDOFST 0x04
|
||||
#define S5P_CIWDOFST_WINOFSEN (1 << 31)
|
||||
#define S5P_CIWDOFST_CLROVFIY (1 << 30)
|
||||
#define S5P_CIWDOFST_CLROVRLB (1 << 29)
|
||||
#define S5P_CIWDOFST_WINHOROFST_MASK (0x7ff << 16)
|
||||
#define S5P_CIWDOFST_CLROVFICB (1 << 15)
|
||||
#define S5P_CIWDOFST_CLROVFICR (1 << 14)
|
||||
#define S5P_CIWDOFST_WINHOROFST(x) ((x) << 16)
|
||||
#define S5P_CIWDOFST_WINVEROFST(x) ((x) << 0)
|
||||
#define S5P_CIWDOFST_WINVEROFST_MASK (0xfff << 0)
|
||||
|
||||
/* Global control */
|
||||
#define S5P_CIGCTRL 0x08
|
||||
#define S5P_CIGCTRL_SWRST (1 << 31)
|
||||
#define S5P_CIGCTRL_CAMRST_A (1 << 30)
|
||||
#define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29)
|
||||
#define S5P_CIGCTRL_SELCAM_ITU_MASK (1 << 29)
|
||||
#define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27)
|
||||
#define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
|
||||
#define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
|
||||
#define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27)
|
||||
#define S5P_CIGCTRL_TESTPAT_MASK (3 << 27)
|
||||
#define S5P_CIGCTRL_TESTPAT_SHIFT (27)
|
||||
#define S5P_CIGCTRL_INVPOLPCLK (1 << 26)
|
||||
#define S5P_CIGCTRL_INVPOLVSYNC (1 << 25)
|
||||
#define S5P_CIGCTRL_INVPOLHREF (1 << 24)
|
||||
#define S5P_CIGCTRL_IRQ_OVFEN (1 << 22)
|
||||
#define S5P_CIGCTRL_HREF_MASK (1 << 21)
|
||||
#define S5P_CIGCTRL_IRQ_LEVEL (1 << 20)
|
||||
#define S5P_CIGCTRL_IRQ_CLR (1 << 19)
|
||||
#define S5P_CIGCTRL_IRQ_ENABLE (1 << 16)
|
||||
#define S5P_CIGCTRL_SHDW_DISABLE (1 << 12)
|
||||
#define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7)
|
||||
#define S5P_CIGCTRL_CAMIF_SELWB (1 << 6)
|
||||
#define S5P_CIGCTRL_INVPOLHSYNC (1 << 4)
|
||||
#define S5P_CIGCTRL_SELCAM_MIPI (1 << 3)
|
||||
#define S5P_CIGCTRL_INTERLACE (1 << 0)
|
||||
|
||||
/* Window offset 2 */
|
||||
#define S5P_CIWDOFST2 0x14
|
||||
#define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16)
|
||||
#define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0)
|
||||
#define S5P_CIWDOFST2_HOROFF(x) ((x) << 16)
|
||||
#define S5P_CIWDOFST2_VEROFF(x) ((x) << 0)
|
||||
|
||||
/* Output DMA Y plane start address */
|
||||
#define S5P_CIOYSA1 0x18
|
||||
#define S5P_CIOYSA2 0x1c
|
||||
#define S5P_CIOYSA3 0x20
|
||||
#define S5P_CIOYSA4 0x24
|
||||
|
||||
/* Output DMA Cb plane start address */
|
||||
#define S5P_CIOCBSA1 0x28
|
||||
#define S5P_CIOCBSA2 0x2c
|
||||
#define S5P_CIOCBSA3 0x30
|
||||
#define S5P_CIOCBSA4 0x34
|
||||
|
||||
/* Output DMA Cr plane start address */
|
||||
#define S5P_CIOCRSA1 0x38
|
||||
#define S5P_CIOCRSA2 0x3c
|
||||
#define S5P_CIOCRSA3 0x40
|
||||
#define S5P_CIOCRSA4 0x44
|
||||
|
||||
/* Target image format */
|
||||
#define S5P_CITRGFMT 0x48
|
||||
#define S5P_CITRGFMT_INROT90 (1 << 31)
|
||||
#define S5P_CITRGFMT_YCBCR420 (0 << 29)
|
||||
#define S5P_CITRGFMT_YCBCR422 (1 << 29)
|
||||
#define S5P_CITRGFMT_YCBCR422_1P (2 << 29)
|
||||
#define S5P_CITRGFMT_RGB (3 << 29)
|
||||
#define S5P_CITRGFMT_FMT_MASK (3 << 29)
|
||||
#define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16)
|
||||
#define S5P_CITRGFMT_FLIP_SHIFT (14)
|
||||
#define S5P_CITRGFMT_FLIP_NORMAL (0 << 14)
|
||||
#define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14)
|
||||
#define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
|
||||
#define S5P_CITRGFMT_FLIP_180 (3 << 14)
|
||||
#define S5P_CITRGFMT_FLIP_MASK (3 << 14)
|
||||
#define S5P_CITRGFMT_OUTROT90 (1 << 13)
|
||||
#define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0)
|
||||
#define S5P_CITRGFMT_HSIZE(x) ((x) << 16)
|
||||
#define S5P_CITRGFMT_VSIZE(x) ((x) << 0)
|
||||
|
||||
/* Output DMA control */
|
||||
#define S5P_CIOCTRL 0x4c
|
||||
#define S5P_CIOCTRL_ORDER422_MASK (3 << 0)
|
||||
#define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0)
|
||||
#define S5P_CIOCTRL_ORDER422_YCRYCB (1 << 0)
|
||||
#define S5P_CIOCTRL_ORDER422_CBYCRY (2 << 0)
|
||||
#define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0)
|
||||
#define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
|
||||
#define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3)
|
||||
#define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3)
|
||||
#define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
|
||||
#define S5P_CIOCTRL_ORDER2P_SHIFT (24)
|
||||
#define S5P_CIOCTRL_ORDER2P_MASK (3 << 24)
|
||||
#define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
|
||||
|
||||
/* Pre-scaler control 1 */
|
||||
#define S5P_CISCPRERATIO 0x50
|
||||
#define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
|
||||
#define S5P_CISCPRERATIO_HOR(x) ((x) << 16)
|
||||
#define S5P_CISCPRERATIO_VER(x) ((x) << 0)
|
||||
|
||||
#define S5P_CISCPREDST 0x54
|
||||
#define S5P_CISCPREDST_WIDTH(x) ((x) << 16)
|
||||
#define S5P_CISCPREDST_HEIGHT(x) ((x) << 0)
|
||||
|
||||
/* Main scaler control */
|
||||
#define S5P_CISCCTRL 0x58
|
||||
#define S5P_CISCCTRL_SCALERBYPASS (1 << 31)
|
||||
#define S5P_CISCCTRL_SCALEUP_H (1 << 30)
|
||||
#define S5P_CISCCTRL_SCALEUP_V (1 << 29)
|
||||
#define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28)
|
||||
#define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27)
|
||||
#define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
|
||||
#define S5P_CISCCTRL_INTERLACE (1 << 25)
|
||||
#define S5P_CISCCTRL_SCALERSTART (1 << 15)
|
||||
#define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
|
||||
#define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
|
||||
#define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
|
||||
#define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13)
|
||||
#define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
|
||||
#define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
|
||||
#define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
|
||||
#define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
|
||||
#define S5P_CISCCTRL_RGB_EXT (1 << 10)
|
||||
#define S5P_CISCCTRL_ONE2ONE (1 << 9)
|
||||
#define S5P_CISCCTRL_SC_HORRATIO(x) ((x) << 16)
|
||||
#define S5P_CISCCTRL_SC_VERRATIO(x) ((x) << 0)
|
||||
|
||||
/* Target area */
|
||||
#define S5P_CITAREA 0x5c
|
||||
#define S5P_CITAREA_MASK 0x0fffffff
|
||||
|
||||
/* General status */
|
||||
#define S5P_CISTATUS 0x64
|
||||
#define S5P_CISTATUS_OVFIY (1 << 31)
|
||||
#define S5P_CISTATUS_OVFICB (1 << 30)
|
||||
#define S5P_CISTATUS_OVFICR (1 << 29)
|
||||
#define S5P_CISTATUS_VSYNC (1 << 28)
|
||||
#define S5P_CISTATUS_WINOFF_EN (1 << 25)
|
||||
#define S5P_CISTATUS_IMGCPT_EN (1 << 22)
|
||||
#define S5P_CISTATUS_IMGCPT_SCEN (1 << 21)
|
||||
#define S5P_CISTATUS_VSYNC_A (1 << 20)
|
||||
#define S5P_CISTATUS_VSYNC_B (1 << 19)
|
||||
#define S5P_CISTATUS_OVRLB (1 << 18)
|
||||
#define S5P_CISTATUS_FRAME_END (1 << 17)
|
||||
#define S5P_CISTATUS_LASTCAPT_END (1 << 16)
|
||||
#define S5P_CISTATUS_VVALID_A (1 << 15)
|
||||
#define S5P_CISTATUS_VVALID_B (1 << 14)
|
||||
|
||||
/* Image capture control */
|
||||
#define S5P_CIIMGCPT 0xc0
|
||||
#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
|
||||
#define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30)
|
||||
#define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
|
||||
#define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
|
||||
|
||||
/* Frame capture sequence */
|
||||
#define S5P_CICPTSEQ 0xc4
|
||||
|
||||
/* Image effect */
|
||||
#define S5P_CIIMGEFF 0xd0
|
||||
#define S5P_CIIMGEFF_IE_DISABLE (0 << 30)
|
||||
#define S5P_CIIMGEFF_IE_ENABLE (1 << 30)
|
||||
#define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29)
|
||||
#define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29)
|
||||
#define S5P_CIIMGEFF_FIN_BYPASS (0 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
|
||||
#define S5P_CIIMGEFF_FIN_MASK (7 << 26)
|
||||
#define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
|
||||
#define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13)
|
||||
#define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0)
|
||||
|
||||
/* Input DMA Y/Cb/Cr plane start address 0 */
|
||||
#define S5P_CIIYSA0 0xd4
|
||||
#define S5P_CIICBSA0 0xd8
|
||||
#define S5P_CIICRSA0 0xdc
|
||||
|
||||
/* Real input DMA image size */
|
||||
#define S5P_CIREAL_ISIZE 0xf8
|
||||
#define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
|
||||
#define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
|
||||
#define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
|
||||
#define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
|
||||
|
||||
|
||||
/* Input DMA control */
|
||||
#define S5P_MSCTRL 0xfc
|
||||
#define S5P_MSCTRL_IN_BURST_COUNT_MASK (3 << 24)
|
||||
#define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
|
||||
#define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16
|
||||
#define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15)
|
||||
#define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15)
|
||||
#define S5P_MSCTRL_C_INT_IN_MASK (1 << 15)
|
||||
#define S5P_MSCTRL_FLIP_SHIFT 13
|
||||
#define S5P_MSCTRL_FLIP_MASK (3 << 13)
|
||||
#define S5P_MSCTRL_FLIP_NORMAL (0 << 13)
|
||||
#define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
|
||||
#define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
|
||||
#define S5P_MSCTRL_FLIP_180 (3 << 13)
|
||||
#define S5P_MSCTRL_ORDER422_SHIFT 4
|
||||
#define S5P_MSCTRL_ORDER422_CRYCBY (0 << 4)
|
||||
#define S5P_MSCTRL_ORDER422_YCRYCB (1 << 4)
|
||||
#define S5P_MSCTRL_ORDER422_CBYCRY (2 << 4)
|
||||
#define S5P_MSCTRL_ORDER422_YCBYCR (3 << 4)
|
||||
#define S5P_MSCTRL_ORDER422_MASK (3 << 4)
|
||||
#define S5P_MSCTRL_INPUT_EXTCAM (0 << 3)
|
||||
#define S5P_MSCTRL_INPUT_MEMORY (1 << 3)
|
||||
#define S5P_MSCTRL_INPUT_MASK (1 << 3)
|
||||
#define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
|
||||
#define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
|
||||
#define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
|
||||
#define S5P_MSCTRL_INFORMAT_RGB (3 << 1)
|
||||
#define S5P_MSCTRL_INFORMAT_MASK (3 << 1)
|
||||
#define S5P_MSCTRL_ENVID (1 << 0)
|
||||
#define S5P_MSCTRL_FRAME_COUNT(x) ((x) << 24)
|
||||
|
||||
/* Input DMA Y/Cb/Cr plane start address 1 */
|
||||
#define S5P_CIIYSA1 0x144
|
||||
#define S5P_CIICBSA1 0x148
|
||||
#define S5P_CIICRSA1 0x14c
|
||||
|
||||
/* Output DMA Y/Cb/Cr offset */
|
||||
#define S5P_CIOYOFF 0x168
|
||||
#define S5P_CIOCBOFF 0x16c
|
||||
#define S5P_CIOCROFF 0x170
|
||||
|
||||
/* Input DMA Y/Cb/Cr offset */
|
||||
#define S5P_CIIYOFF 0x174
|
||||
#define S5P_CIICBOFF 0x178
|
||||
#define S5P_CIICROFF 0x17c
|
||||
|
||||
#define S5P_CIO_OFFS_VER(x) ((x) << 16)
|
||||
#define S5P_CIO_OFFS_HOR(x) ((x) << 0)
|
||||
|
||||
/* Input DMA original image size */
|
||||
#define S5P_ORGISIZE 0x180
|
||||
|
||||
/* Output DMA original image size */
|
||||
#define S5P_ORGOSIZE 0x184
|
||||
|
||||
#define S5P_ORIG_SIZE_VER(x) ((x) << 16)
|
||||
#define S5P_ORIG_SIZE_HOR(x) ((x) << 0)
|
||||
|
||||
/* Real output DMA image size (extension register) */
|
||||
#define S5P_CIEXTEN 0x188
|
||||
|
||||
#define S5P_CIDMAPARAM 0x18c
|
||||
#define S5P_CIDMAPARAM_R_LINEAR (0 << 29)
|
||||
#define S5P_CIDMAPARAM_R_64X32 (3 << 29)
|
||||
#define S5P_CIDMAPARAM_W_LINEAR (0 << 13)
|
||||
#define S5P_CIDMAPARAM_W_64X32 (3 << 13)
|
||||
#define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
|
||||
|
||||
/* MIPI CSI image format */
|
||||
#define S5P_CSIIMGFMT 0x194
|
||||
|
||||
#endif /* REGS_FIMC_H_ */
|
||||
|
|
@ -277,6 +277,7 @@ struct v4l2_pix_format {
|
|||
#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R', 'G', 'B', 'P') /* 16 RGB-5-6-5 */
|
||||
#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5 BE */
|
||||
#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5 BE */
|
||||
#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6 */
|
||||
#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8 */
|
||||
#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8 */
|
||||
#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue