ARM: S5P: Fix the platform external interrupt issues.
This patch does the following: 1. Corrects the common platform code for external interrupts for using the VIC mask/unmask bits also. 2. Moves the common defines related to external interrupt for plat-s5p to common files. 3. Based on the new common defines, corresponding changes are made in the affected platforms (S5P6440, S5P6442 and S5PC100). Signed-off-by: Pannaga Bhushan <p.bhushan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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@ -72,7 +72,14 @@
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#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
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#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
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#define IRQ_EINT(x) S5P_EINT(x)
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#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
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/*
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* S5P6440 has 0-15 external interrupts in group 0. Only these can be used
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* to wake up from sleep. If request is beyond this range, by mistake, a large
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* return value for an irq number should be indication of something amiss.
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*/
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#define S5P_EINT_BASE2 (0xf0000000)
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/*
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* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
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@ -77,8 +77,9 @@
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#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1)
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#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \
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(S5P_IRQ_EINT_BASE + (x)-16))
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#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
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#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE)
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT(31) + 1)
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@ -100,9 +100,6 @@
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#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
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#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
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#define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \
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(S5P_EINT_BASE2 + (x) - 16))
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#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
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#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
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@ -118,22 +118,12 @@
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#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
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#define IRQ_VIC_END S5P_IRQ_VIC3(31)
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#define S5P_EINT_16_31_BASE (IRQ_VIC_END + 1)
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#define EINT_MODE S3C_GPIO_SFN(0xf)
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#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_IRQ_VIC0(0)) \
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: ((x) + S5P_EINT_16_31_BASE))
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#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
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#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
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/* Set the default NR_IRQS */
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#define NR_IRQS (IRQ_EINT(31) + 1)
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#define EINT_GPIO_0(x) S5PV210_GPH0(x)
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#define EINT_GPIO_1(x) S5PV210_GPH1(x)
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#define EINT_GPIO_2(x) S5PV210_GPH2(x)
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#define EINT_GPIO_3(x) S5PV210_GPH3(x)
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/* Compatibility */
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#define IRQ_LCD_FIFO IRQ_LCD0
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#define IRQ_LCD_VSYNC IRQ_LCD1
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@ -27,12 +27,9 @@
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#define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40)
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#define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4))
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#define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \
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: ((irq) - S5P_EINT_16_31_BASE))
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#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
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#define EINT_REG_NR(x) (eint_offset(x) >> 3)
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#define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7))
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#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
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/* values for S5P_EXTINT0 */
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#define S5P_EXTINT_LOWLEV (0x00)
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@ -41,4 +38,11 @@
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#define S5P_EXTINT_RISEEDGE (0x03)
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#define S5P_EXTINT_BOTHEDGE (0x04)
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#define EINT_MODE S3C_GPIO_SFN(0xf)
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#define EINT_GPIO_0(x) S5PV210_GPH0(x)
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#define EINT_GPIO_1(x) S5PV210_GPH1(x)
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#define EINT_GPIO_2(x) S5PV210_GPH2(x)
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#define EINT_GPIO_3(x) S5PV210_GPH3(x)
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#endif /* __ASM_ARCH_REGS_GPIO_H */
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@ -29,3 +29,4 @@ config S5P_EXT_INT
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bool
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help
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Use the external interrupts (other than GPIO interrupts.)
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Note: Do not choose this for S5P6440.
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@ -87,4 +87,11 @@
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#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
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#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
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#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
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: ((x) - 16 + S5P_EINT_BASE2))
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#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
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((irq) - S5P_EINT_BASE1) : \
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((irq) + 16 - S5P_EINT_BASE2))
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#endif /* __ASM_PLAT_S5P_IRQS_H */
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@ -60,7 +60,7 @@ static void s5p_irq_eint_maskack(unsigned int irq)
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static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
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{
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int offs = eint_offset(irq);
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int offs = EINT_OFFSET(irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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@ -139,17 +139,16 @@ static struct irq_chip s5p_irq_eint = {
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*/
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static inline void s5p_irq_demux_eint(unsigned int start)
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{
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u32 status;
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u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
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u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
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unsigned int irq;
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status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
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status &= ~mask;
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status &= 0xff;
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while (status) {
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irq = fls(status);
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generic_handle_irq(irq - 1 + start);
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irq = fls(status) - 1;
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generic_handle_irq(irq + start);
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status &= ~(1 << irq);
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}
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}
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@ -162,12 +161,18 @@ static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
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static inline void s5p_irq_vic_eint_mask(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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s5p_irq_eint_mask(irq);
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writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR);
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}
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static void s5p_irq_vic_eint_unmask(unsigned int irq)
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{
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void __iomem *base = get_irq_chip_data(irq);
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s5p_irq_eint_unmask(irq);
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writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE);
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}
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static inline void s5p_irq_vic_eint_ack(unsigned int irq)
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