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A couple fixes to the core framework logic that finds clk parents, a 

handful of samsung clk driver fixes for audio and display clks, and a
 small fix for the Stratix10 SoC driver that was checking the wrong
 register for validity.
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A couple fixes to the core framework logic that finds clk parents, a
  handful of samsung clk driver fixes for audio and display clks, and a
  small fix for the Stratix10 SoC driver that was checking the wrong
  register for validity"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: Fix potential NULL dereference in clk_fetch_parent_index()
  clk: Fix falling back to legacy parent string matching
  clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
  clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU
  clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU
  clk: samsung: Change signature of exynos5_subcmus_init() function
This commit is contained in:
Linus Torvalds 2019-08-19 16:28:25 -07:00
parent 287c55ed7d 24876f09a7
commit 5f97cbe22b
6 changed files with 163 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/clk/clk.c
View File

@ -324,6 +324,25 @@ static struct clk_core *clk_core_lookup(const char *name)
return NULL;
}
#ifdef CONFIG_OF
static int of_parse_clkspec(const struct device_node *np, int index,
const char *name, struct of_phandle_args *out_args);
static struct clk_hw *
of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec);
#else
static inline int of_parse_clkspec(const struct device_node *np, int index,
const char *name,
struct of_phandle_args *out_args)
{
return -ENOENT;
}
static inline struct clk_hw *
of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec)
{
return ERR_PTR(-ENOENT);
}
#endif
/**
* clk_core_get - Find the clk_core parent of a clk
* @core: clk to find parent of
@ -355,8 +374,9 @@ static struct clk_core *clk_core_lookup(const char *name)
* };
*
* Returns: -ENOENT when the provider can't be found or the clk doesn't
* exist in the provider. -EINVAL when the name can't be found. NULL when the
* provider knows about the clk but it isn't provided on this system.
* exist in the provider or the name can't be found in the DT node or
* in a clkdev lookup. NULL when the provider knows about the clk but it
* isn't provided on this system.
* A valid clk_core pointer when the clk can be found in the provider.
*/
static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
@ -367,17 +387,19 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
struct device *dev = core->dev;
const char *dev_id = dev ? dev_name(dev) : NULL;
struct device_node *np = core->of_node;
struct of_phandle_args clkspec;
if (np && (name || index >= 0))
hw = of_clk_get_hw(np, index, name);
/*
* If the DT search above couldn't find the provider or the provider
* didn't know about this clk, fallback to looking up via clkdev based
* clk_lookups
*/
if (PTR_ERR(hw) == -ENOENT && name)
if (np && (name || index >= 0) &&
!of_parse_clkspec(np, index, name, &clkspec)) {
hw = of_clk_get_hw_from_clkspec(&clkspec);
of_node_put(clkspec.np);
} else if (name) {
/*
* If the DT search above couldn't find the provider fallback to
* looking up via clkdev based clk_lookups.
*/
hw = clk_find_hw(dev_id, name);
}
if (IS_ERR(hw))
return ERR_CAST(hw);
@ -401,7 +423,7 @@ static void clk_core_fill_parent_index(struct clk_core *core, u8 index)
parent = ERR_PTR(-EPROBE_DEFER);
} else {
parent = clk_core_get(core, index);
if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT)
if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT && entry->name)
parent = clk_core_lookup(entry->name);
}
@ -1632,7 +1654,8 @@ static int clk_fetch_parent_index(struct clk_core *core,
break;
/* Fallback to comparing globally unique names */
if (!strcmp(parent->name, core->parents[i].name))
if (core->parents[i].name &&
!strcmp(parent->name, core->parents[i].name))
break;
}

16
drivers/clk/samsung/clk-exynos5-subcmu.c
View File

@ -14,7 +14,7 @@
#include "clk-exynos5-subcmu.h"
static struct samsung_clk_provider *ctx;
static const struct exynos5_subcmu_info *cmu;
static const struct exynos5_subcmu_info **cmu;
static int nr_cmus;
static void exynos5_subcmu_clk_save(void __iomem *base,
@ -56,17 +56,17 @@ static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
* when OF-core populates all device-tree nodes.
*/
void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
const struct exynos5_subcmu_info *_cmu)
const struct exynos5_subcmu_info **_cmu)
{
ctx = _ctx;
cmu = _cmu;
nr_cmus = _nr_cmus;
for (; _nr_cmus--; _cmu++) {
exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks,
_cmu->nr_gate_clks);
exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs,
_cmu->nr_suspend_regs);
exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
(*_cmu)->nr_gate_clks);
exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
(*_cmu)->nr_suspend_regs);
}
}
@ -163,9 +163,9 @@ static int __init exynos5_clk_probe(struct platform_device *pdev)
if (of_property_read_string(np, "label", &name) < 0)
continue;
for (i = 0; i < nr_cmus; i++)
if (strcmp(cmu[i].pd_name, name) == 0)
if (strcmp(cmu[i]->pd_name, name) == 0)
exynos5_clk_register_subcmu(&pdev->dev,
&cmu[i], np);
cmu[i], np);
}
return 0;
}

2
drivers/clk/samsung/clk-exynos5-subcmu.h
View File

@ -21,6 +21,6 @@ struct exynos5_subcmu_info {
};
void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus,
const struct exynos5_subcmu_info *cmu);
const struct exynos5_subcmu_info **cmu);
#endif

7
drivers/clk/samsung/clk-exynos5250.c
View File

@ -681,6 +681,10 @@ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
.pd_name = "DISP1",
};
static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
&exynos5250_disp_subcmu,
};
static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
/* sorted in descending order */
/* PLL_36XX_RATE(rate, m, p, s, k) */
@ -843,7 +847,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
ARRAY_SIZE(exynos5250_clk_regs));
exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
exynos5250_subcmus);
samsung_clk_of_add_provider(np, ctx);

162
drivers/clk/samsung/clk-exynos5420.c
View File

@ -534,8 +534,6 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
GATE_BUS_TOP, 24, 0, 0),
GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
@ -577,8 +575,13 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
/* Maudio Block */
GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
};
static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
@ -890,9 +893,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
/* GSCL Block */
DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
/* MSCL Block */
DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
/* PSGEN */
DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
@ -1017,12 +1017,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
/* Maudio Block */
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
/* FSYS Block */
GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
@ -1162,17 +1156,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
GATE_IP_GSCL1, 17, 0, 0),
/* MSCL Block */
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
GATE_IP_MSCL, 8, 0, 0),
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
GATE_IP_MSCL, 9, 0, 0),
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
GATE_IP_MSCL, 10, 0, 0),
/* ISP */
GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
@ -1281,32 +1264,103 @@ static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
{ DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
};
static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
{
.div_clks = exynos5x_disp_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
.gate_clks = exynos5x_disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
.suspend_regs = exynos5x_disp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
.pd_name = "DISP",
}, {
.div_clks = exynos5x_gsc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
.gate_clks = exynos5x_gsc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
.suspend_regs = exynos5x_gsc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
.pd_name = "GSC",
}, {
.div_clks = exynos5x_mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
.gate_clks = exynos5x_mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
.suspend_regs = exynos5x_mfc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
.pd_name = "MFC",
},
static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
/* MSCL Block */
GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
GATE_IP_MSCL, 8, 0, 0),
GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
GATE_IP_MSCL, 9, 0, 0),
GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
GATE_IP_MSCL, 10, 0, 0),
};
static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
};
static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
{ GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
{ SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
{ DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
};
static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
};
static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
{ SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
};
static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
.div_clks = exynos5x_disp_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
.gate_clks = exynos5x_disp_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
.suspend_regs = exynos5x_disp_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
.pd_name = "DISP",
};
static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
.div_clks = exynos5x_gsc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
.gate_clks = exynos5x_gsc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
.suspend_regs = exynos5x_gsc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
.pd_name = "GSC",
};
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
.div_clks = exynos5x_mfc_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
.gate_clks = exynos5x_mfc_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
.suspend_regs = exynos5x_mfc_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
.pd_name = "MFC",
};
static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
.div_clks = exynos5x_mscl_div_clks,
.nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
.gate_clks = exynos5x_mscl_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
.suspend_regs = exynos5x_mscl_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
.pd_name = "MSC",
};
static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
.gate_clks = exynos5800_mau_gate_clks,
.nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
.suspend_regs = exynos5800_mau_suspend_regs,
.nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
.pd_name = "MAU",
};
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
&exynos5x_disp_subcmu,
&exynos5x_gsc_subcmu,
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
};
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
&exynos5x_disp_subcmu,
&exynos5x_gsc_subcmu,
&exynos5x_mfc_subcmu,
&exynos5x_mscl_subcmu,
&exynos5800_mau_subcmu,
};
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
@ -1539,11 +1593,17 @@ static void __init exynos5x_clk_init(struct device_node *np,
samsung_clk_extended_sleep_init(reg_base,
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
if (soc == EXYNOS5800)
if (soc == EXYNOS5800) {
samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
ARRAY_SIZE(exynos5800_clk_regs));
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
exynos5x_subcmus);
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
exynos5800_subcmus);
} else {
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
exynos5x_subcmus);
}
samsung_clk_of_add_provider(np, ctx);
}

2
drivers/clk/socfpga/clk-periph-s10.c
View File

@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
if (socfpgaclk->fixed_div) {
div = socfpgaclk->fixed_div;
} else {
if (!socfpgaclk->bypass_reg)
if (socfpgaclk->hw.reg)
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
}