ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction
The custom suspend callback is removed for this change. The extra call to exynos_cpu_power_up(() that was present at the end of exynos_suspend() is now relocated to the cpu_is_up callback. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Nicolas Pitre
Olof Johansson
parent
323ab95339
commit
5f493ace72
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@ -61,25 +61,7 @@ static void __iomem *ns_sram_base_addr;
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
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"r9", "r10", "lr", "memory")
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/*
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* We can't use regular spinlocks. In the switcher case, it is possible
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* for an outbound CPU to call power_down() after its inbound counterpart
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* is already live using the same logical CPU number which trips lockdep
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* debugging.
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*/
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static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static int
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cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
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#define exynos_cluster_usecnt(cluster) \
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(cpu_use_count[0][cluster] + \
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cpu_use_count[1][cluster] + \
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cpu_use_count[2][cluster] + \
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cpu_use_count[3][cluster])
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#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
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static int exynos_power_up(unsigned int cpu, unsigned int cluster)
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static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
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{
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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@ -88,127 +70,65 @@ static int exynos_power_up(unsigned int cpu, unsigned int cluster)
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cluster >= EXYNOS5420_NR_CLUSTERS)
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return -EINVAL;
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/*
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* Since this is called with IRQs enabled, and no arch_spin_lock_irq
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* variant exists, we need to disable IRQs manually here.
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*/
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local_irq_disable();
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arch_spin_lock(&exynos_mcpm_lock);
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cpu_use_count[cpu][cluster]++;
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if (cpu_use_count[cpu][cluster] == 1) {
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bool was_cluster_down =
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(exynos_cluster_usecnt(cluster) == 1);
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/*
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* Turn on the cluster (L2/COMMON) and then power on the
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* cores.
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*/
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if (was_cluster_down)
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exynos_cluster_power_up(cluster);
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exynos_cpu_power_up(cpunr);
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} else if (cpu_use_count[cpu][cluster] != 2) {
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/*
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* The only possible values are:
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* 0 = CPU down
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* 1 = CPU (still) up
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* 2 = CPU requested to be up before it had a chance
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* to actually make itself down.
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* Any other value is a bug.
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*/
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BUG();
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}
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arch_spin_unlock(&exynos_mcpm_lock);
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local_irq_enable();
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exynos_cpu_power_up(cpunr);
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return 0;
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}
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/*
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* NOTE: This function requires the stack data to be visible through power down
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* and can only be executed on processors like A15 and A7 that hit the cache
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* with the C bit clear in the SCTLR register.
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*/
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static void exynos_power_down(void)
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static int exynos_cluster_powerup(unsigned int cluster)
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{
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unsigned int mpidr, cpu, cluster;
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bool last_man = false, skip_wfi = false;
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unsigned int cpunr;
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pr_debug("%s: cluster %u\n", __func__, cluster);
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if (cluster >= EXYNOS5420_NR_CLUSTERS)
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return -EINVAL;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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exynos_cluster_power_up(cluster);
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return 0;
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}
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static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
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{
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS);
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exynos_cpu_power_down(cpunr);
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}
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__mcpm_cpu_going_down(cpu, cluster);
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static void exynos_cluster_powerdown_prepare(unsigned int cluster)
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{
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pr_debug("%s: cluster %u\n", __func__, cluster);
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BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
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exynos_cluster_power_down(cluster);
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}
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arch_spin_lock(&exynos_mcpm_lock);
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BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
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cpu_use_count[cpu][cluster]--;
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if (cpu_use_count[cpu][cluster] == 0) {
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exynos_cpu_power_down(cpunr);
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static void exynos_cpu_cache_disable(void)
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{
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/* Disable and flush the local CPU cache. */
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exynos_v7_exit_coherency_flush(louis);
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}
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if (exynos_cluster_unused(cluster)) {
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exynos_cluster_power_down(cluster);
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last_man = true;
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}
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} else if (cpu_use_count[cpu][cluster] == 1) {
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static void exynos_cluster_cache_disable(void)
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{
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* A power_up request went ahead of us.
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* Even if we do not want to shut this CPU down,
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* the caller expects a certain state as if the WFI
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* was aborted. So let's continue with cache cleaning.
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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skip_wfi = true;
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} else {
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BUG();
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3\n\t"
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"isb\n\t"
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"dsb"
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: : "r" (0x400));
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}
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if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
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arch_spin_unlock(&exynos_mcpm_lock);
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/* Flush all cache levels for this cluster. */
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exynos_v7_exit_coherency_flush(all);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
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/*
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* On the Cortex-A15 we need to disable
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* L2 prefetching before flushing the cache.
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*/
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3\n\t"
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"isb\n\t"
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"dsb"
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: : "r" (0x400));
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}
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/* Flush all cache levels for this cluster. */
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exynos_v7_exit_coherency_flush(all);
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(mpidr);
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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} else {
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arch_spin_unlock(&exynos_mcpm_lock);
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/* Disable and flush the local CPU cache. */
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exynos_v7_exit_coherency_flush(louis);
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}
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__mcpm_cpu_down(cpu, cluster);
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/* Now we are prepared for power-down, do it: */
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if (!skip_wfi)
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wfi();
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/* Not dead at this point? Let our caller cope. */
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/*
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* Disable cluster-level coherency by masking
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* incoming snoops and DVM messages:
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*/
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cci_disable_port_by_cpu(read_cpuid_mpidr());
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}
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static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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@ -222,10 +142,8 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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/* Wait for the core state to be OFF */
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while (tries--) {
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if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
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if ((exynos_cpu_power_state(cpunr) == 0))
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return 0; /* success: the CPU is halted */
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}
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if ((exynos_cpu_power_state(cpunr) == 0))
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return 0; /* success: the CPU is halted */
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/* Otherwise, wait and retry: */
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msleep(1);
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@ -234,63 +152,23 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
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return -ETIMEDOUT; /* timeout */
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}
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static void exynos_powered_up(void)
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static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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arch_spin_lock(&exynos_mcpm_lock);
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if (cpu_use_count[cpu][cluster] == 0)
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cpu_use_count[cpu][cluster] = 1;
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arch_spin_unlock(&exynos_mcpm_lock);
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}
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static void exynos_suspend(u64 residency)
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{
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unsigned int mpidr, cpunr;
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exynos_power_down();
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/*
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* Execution reaches here only if cpu did not power down.
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* Hence roll back the changes done in exynos_power_down function.
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*
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* CAUTION: "This function requires the stack data to be visible through
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* power down and can only be executed on processors like A15 and A7
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* that hit the cache with the C bit clear in the SCTLR register."
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*/
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mpidr = read_cpuid_mpidr();
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cpunr = exynos_pmu_cpunr(mpidr);
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exynos_cpu_power_up(cpunr);
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/* especially when resuming: make sure power control is set */
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exynos_cpu_powerup(cpu, cluster);
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}
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static const struct mcpm_platform_ops exynos_power_ops = {
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.power_up = exynos_power_up,
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.power_down = exynos_power_down,
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.cpu_powerup = exynos_cpu_powerup,
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.cluster_powerup = exynos_cluster_powerup,
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.cpu_powerdown_prepare = exynos_cpu_powerdown_prepare,
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.cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
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.cpu_cache_disable = exynos_cpu_cache_disable,
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.cluster_cache_disable = exynos_cluster_cache_disable,
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.wait_for_powerdown = exynos_wait_for_powerdown,
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.suspend = exynos_suspend,
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.powered_up = exynos_powered_up,
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.cpu_is_up = exynos_cpu_is_up,
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};
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static void __init exynos_mcpm_usage_count_init(void)
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{
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unsigned int mpidr, cpu, cluster;
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mpidr = read_cpuid_mpidr();
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
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cluster >= EXYNOS5420_NR_CLUSTERS);
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cpu_use_count[cpu][cluster] = 1;
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}
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/*
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* Enable cluster-level coherency, in preparation for turning on the MMU.
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*/
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@ -302,19 +180,6 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
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"b cci_enable_port_for_self");
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}
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static void __init exynos_cache_off(void)
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{
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
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/* disable L2 prefetching on the Cortex-A15 */
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asm volatile(
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"mcr p15, 1, %0, c15, c0, 3\n\t"
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"isb\n\t"
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"dsb"
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: : "r" (0x400));
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}
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exynos_v7_exit_coherency_flush(all);
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}
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static const struct of_device_id exynos_dt_mcpm_match[] = {
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{ .compatible = "samsung,exynos5420" },
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{ .compatible = "samsung,exynos5800" },
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@ -370,13 +235,11 @@ static int __init exynos_mcpm_init(void)
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*/
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pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
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exynos_mcpm_usage_count_init();
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ret = mcpm_platform_register(&exynos_power_ops);
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if (!ret)
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ret = mcpm_sync_init(exynos_pm_power_up_setup);
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if (!ret)
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ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
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ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
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if (ret) {
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iounmap(ns_sram_base_addr);
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return ret;
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