xtensa: fix ATOMCTL register documentation
Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5). Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -40,5 +40,5 @@ See Section 4.3.12.4 of ISA; Bits:
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--------- --------------- ----------------- ----------------
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--------- --------------- ----------------- ----------------
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0 Exception Exception Exception
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0 Exception Exception Exception
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1 RCW Transaction RCW Transaction RCW Transaction
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1 RCW Transaction RCW Transaction RCW Transaction
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2 Internal Operation Exception Reserved
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2 Internal Operation Internal Operation Reserved
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3 Reserved Reserved Reserved
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3 Reserved Reserved Reserved
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