ARM: cns3xxx: Add support for PCI Express ports
This patch adds PCIe support for CNS3xxx-based boards. The support was tested with a directly attached SKY2 NIC, and EHCI USB controller behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles work as expected). Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
This commit is contained in:
Anton Vorontsov
parent
6eb5d146d4
commit
5f32f7a028
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@ -301,6 +301,7 @@ config ARCH_CNS3XXX
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select CPU_V6
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select GENERIC_CLOCKEVENTS
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select ARM_GIC
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select PCI_DOMAINS if PCI
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help
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Support for Cavium Networks CNS3XXX platform.
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@ -1059,7 +1060,7 @@ config ISA_DMA_API
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bool
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config PCI
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bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
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bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
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help
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Find out whether you have a PCI motherboard. PCI is the name of a
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bus system, i.e. the way the CPU talks to the other stuff inside
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@ -1,2 +1,3 @@
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obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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@ -0,0 +1,389 @@
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/*
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* PCI-E support for CNS3xxx
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*
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* Copyright 2008 Cavium Networks
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* Richard Liu <richard.liu@caviumnetworks.com>
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* Copyright 2010 MontaVista Software, LLC.
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* Anton Vorontsov <avorontsov@mvista.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/mach/map.h>
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#include <mach/cns3xxx.h>
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#include "core.h"
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enum cns3xxx_access_type {
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CNS3XXX_HOST_TYPE = 0,
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CNS3XXX_CFG0_TYPE,
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CNS3XXX_CFG1_TYPE,
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CNS3XXX_NUM_ACCESS_TYPES,
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};
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struct cns3xxx_pcie {
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struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
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unsigned int irqs[2];
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struct resource res_io;
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struct resource res_mem;
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struct hw_pci hw_pci;
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bool linked;
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};
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static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
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static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
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{
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struct pci_sys_data *root = sysdata;
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return &cns3xxx_pcie[root->domain];
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}
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static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
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{
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return sysdata_to_cnspci(dev->sysdata);
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}
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static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
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{
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return sysdata_to_cnspci(bus->sysdata);
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}
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static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
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int busno = bus->number;
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int slot = PCI_SLOT(devfn);
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int offset;
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enum cns3xxx_access_type type;
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void __iomem *base;
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/* If there is no link, just show the CNS PCI bridge. */
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if (!cnspci->linked && (busno > 0 || slot > 0))
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return NULL;
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/*
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* The CNS PCI bridge doesn't fit into the PCI hierarchy, though
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* we still want to access it. For this to work, we must place
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* the first device on the same bus as the CNS PCI bridge.
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*/
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if (busno == 0) {
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if (slot > 1)
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return NULL;
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type = slot;
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} else {
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type = CNS3XXX_CFG1_TYPE;
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}
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base = (void __iomem *)cnspci->cfg_bases[type].virtual;
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offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
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return base + offset;
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}
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static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 v;
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void __iomem *base;
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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base = cns3xxx_pci_cfg_base(bus, devfn, where);
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if (!base) {
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*val = 0xffffffff;
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return PCIBIOS_SUCCESSFUL;
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}
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v = __raw_readl(base);
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if (bus->number == 0 && devfn == 0 &&
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(where & 0xffc) == PCI_CLASS_REVISION) {
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/*
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* RC's class is 0xb, but Linux PCI driver needs 0x604
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* for a PCIe bridge. So we must fixup the class code
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* to 0x604 here.
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*/
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v &= 0xff;
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v |= 0x604 << 16;
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}
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*val = (v >> shift) & mask;
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return PCIBIOS_SUCCESSFUL;
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}
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static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 v;
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void __iomem *base;
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u32 mask = (0x1ull << (size * 8)) - 1;
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int shift = (where % 4) * 8;
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base = cns3xxx_pci_cfg_base(bus, devfn, where);
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if (!base)
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return PCIBIOS_SUCCESSFUL;
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v = __raw_readl(base);
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v &= ~(mask << shift);
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v |= (val & mask) << shift;
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__raw_writel(v, base);
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return PCIBIOS_SUCCESSFUL;
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}
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static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
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struct resource *res_io = &cnspci->res_io;
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struct resource *res_mem = &cnspci->res_mem;
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struct resource **sysres = sys->resource;
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BUG_ON(request_resource(&iomem_resource, res_io) ||
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request_resource(&iomem_resource, res_mem));
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sysres[0] = res_io;
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sysres[1] = res_mem;
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return 1;
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}
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static struct pci_ops cns3xxx_pcie_ops = {
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.read = cns3xxx_pci_read_config,
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.write = cns3xxx_pci_write_config,
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};
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static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
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}
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static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
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int irq = cnspci->irqs[slot];
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pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
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pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), slot, pin, irq);
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return irq;
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}
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static struct cns3xxx_pcie cns3xxx_pcie[] = {
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[0] = {
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.cfg_bases = {
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[CNS3XXX_HOST_TYPE] = {
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.virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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[CNS3XXX_CFG0_TYPE] = {
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.virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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[CNS3XXX_CFG1_TYPE] = {
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.virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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},
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.res_io = {
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.name = "PCIe0 I/O space",
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.start = CNS3XXX_PCIE0_IO_BASE,
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.end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
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.flags = IORESOURCE_IO,
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},
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.res_mem = {
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.name = "PCIe0 non-prefetchable",
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.start = CNS3XXX_PCIE0_MEM_BASE,
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.end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
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.hw_pci = {
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.domain = 0,
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.swizzle = pci_std_swizzle,
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.nr_controllers = 1,
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.setup = cns3xxx_pci_setup,
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.scan = cns3xxx_pci_scan_bus,
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.map_irq = cns3xxx_pcie_map_irq,
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},
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},
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[1] = {
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.cfg_bases = {
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[CNS3XXX_HOST_TYPE] = {
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.virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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[CNS3XXX_CFG0_TYPE] = {
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.virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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[CNS3XXX_CFG1_TYPE] = {
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.virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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},
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.res_io = {
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.name = "PCIe1 I/O space",
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.start = CNS3XXX_PCIE1_IO_BASE,
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.end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
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.flags = IORESOURCE_IO,
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},
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.res_mem = {
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.name = "PCIe1 non-prefetchable",
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.start = CNS3XXX_PCIE1_MEM_BASE,
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.end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
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.hw_pci = {
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.domain = 1,
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.swizzle = pci_std_swizzle,
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.nr_controllers = 1,
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.setup = cns3xxx_pci_setup,
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.scan = cns3xxx_pci_scan_bus,
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.map_irq = cns3xxx_pcie_map_irq,
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},
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},
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};
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static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
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{
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int port = cnspci->hw_pci.domain;
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u32 reg;
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unsigned long time;
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reg = __raw_readl(MISC_PCIE_CTRL(port));
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/*
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* Enable Application Request to 1, it will exit L1 automatically,
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* but when chip back, it will use another clock, still can use 0x1.
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*/
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reg |= 0x3;
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__raw_writel(reg, MISC_PCIE_CTRL(port));
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pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
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pr_info("PCIe: Port[%d] Check data link layer...", port);
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time = jiffies;
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while (1) {
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reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
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if (reg & 0x1) {
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pr_info("Link up.\n");
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cnspci->linked = 1;
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break;
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} else if (time_after(jiffies, time + 50)) {
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pr_info("Device not found.\n");
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break;
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}
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}
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}
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static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
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{
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int port = cnspci->hw_pci.domain;
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struct pci_sys_data sd = {
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.domain = port,
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};
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struct pci_bus bus = {
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.number = 0,
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.ops = &cns3xxx_pcie_ops,
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.sysdata = &sd,
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};
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u32 io_base = cnspci->res_io.start >> 16;
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u32 mem_base = cnspci->res_mem.start >> 16;
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u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
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u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
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u32 devfn = 0;
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u8 tmp8;
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u16 pos;
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u16 dc;
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host_base = (__pfn_to_phys(host_base) - 1) >> 16;
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cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
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pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
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pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
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pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
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pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
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pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
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pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
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pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
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pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
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pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
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pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
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if (!cnspci->linked)
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return;
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/* Set Device Max_Read_Request_Size to 128 byte */
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devfn = PCI_DEVFN(1, 0);
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pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
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dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
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pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
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pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
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if (!(dc & (0x3 << 12)))
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pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
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/* Disable PCIe0 Interrupt Mask INTA to INTD */
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__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
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}
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static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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static int __init cns3xxx_pcie_init(void)
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{
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int i;
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hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
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"imprecise external abort");
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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iotable_init(cns3xxx_pcie[i].cfg_bases,
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ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
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cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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pci_common_init(&cns3xxx_pcie[i].hw_pci);
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}
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pci_assign_unassigned_resources();
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return 0;
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}
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device_initcall(cns3xxx_pcie_init);
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