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[ALSA] hda-intel - Fix HDA buffer alignment 

From the HDA spec it appears that the buffers written to the BDL and
sent to a codec must be 128 byte aligned (section 4.5.1).  The alignment
was not happening especially when playing 6 channels.  This patch set
the alignment of buffers and periods to 128 bytes.

Signed-off-by: Joachim Deguara <joachim.deguara@amd.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Joachim Deguara 2007-03-16 15:01:36 +01:00 committed by Jaroslav Kysela
parent a8a5d06775
commit 5f1545bc45
1 changed files with 4 additions and 0 deletions
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4
sound/pci/hda/hda_intel.c
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@ -1087,6 +1087,10 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
runtime->hw.rates = hinfo->rates;
snd_pcm_limit_hw_rates(runtime);
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
128);
snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
128);
if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
azx_release_device(azx_dev);
mutex_unlock(&chip->open_mutex);