[ALSA] hda-intel - Fix HDA buffer alignment
From the HDA spec it appears that the buffers written to the BDL and sent to a codec must be 128 byte aligned (section 4.5.1). The alignment was not happening especially when playing 6 channels. This patch set the alignment of buffers and periods to 128 bytes. Signed-off-by: Joachim Deguara <joachim.deguara@amd.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
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@ -1087,6 +1087,10 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
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runtime->hw.rates = hinfo->rates;
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runtime->hw.rates = hinfo->rates;
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snd_pcm_limit_hw_rates(runtime);
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snd_pcm_limit_hw_rates(runtime);
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snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
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snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
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128);
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snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
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128);
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if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
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if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
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azx_release_device(azx_dev);
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azx_release_device(azx_dev);
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mutex_unlock(&chip->open_mutex);
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mutex_unlock(&chip->open_mutex);
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