From b0ff9b590733079f7f9453e5976a9dd2630949e3 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Wed, 15 Apr 2020 09:13:17 +0800 Subject: [PATCH 1/9] dt-bindings: display: mediatek: control dpi pins mode to avoid leakage Add property "pinctrl-names" to swap pin mode between gpio and dpi mode. Set the dpi pins to gpio mode and output-low to avoid leakage current when dpi disabled. Acked-by: Rob Herring Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dpi.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt index 58914cf681b8..77def4456706 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt @@ -17,6 +17,9 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached HDMI or LVDS encoder chip. +Optional properties: +- pinctrl-names: Contain "default" and "sleep". + Example: dpi0: dpi@1401d000 { @@ -27,6 +30,9 @@ dpi0: dpi@1401d000 { <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dpi_pin_func>; + pinctrl-1 = <&dpi_pin_idle>; port { dpi0_out: endpoint { From 6bd4763fd532cff43f9b15704f324c45a9806f53 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Wed, 15 Apr 2020 09:13:19 +0800 Subject: [PATCH 2/9] drm/mediatek: set dpi pin mode to gpio low to avoid leakage current Config dpi pins mode to output and pull low when dpi is disabled. Aovid leakage current from some dpi pins (Hsync Vsync DE ... ). Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4f0ce4cd5b8c..2994c63ea279 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -10,7 +10,9 @@ #include #include #include +#include #include +#include #include #include @@ -74,6 +76,9 @@ struct mtk_dpi { enum mtk_dpi_out_yc_map yc_map; enum mtk_dpi_out_bit_num bit_num; enum mtk_dpi_out_channel_swap channel_swap; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_gpio; + struct pinctrl_state *pins_dpi; int refcount; }; @@ -379,6 +384,9 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) if (--dpi->refcount != 0) return; + if (dpi->pinctrl && dpi->pins_gpio) + pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); + mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); @@ -403,6 +411,9 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) goto err_pixel; } + if (dpi->pinctrl && dpi->pins_dpi) + pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); + mtk_dpi_enable(dpi); return 0; @@ -705,6 +716,26 @@ static int mtk_dpi_probe(struct platform_device *pdev) dpi->dev = dev; dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev); + dpi->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(dpi->pinctrl)) { + dpi->pinctrl = NULL; + dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); + } + if (dpi->pinctrl) { + dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep"); + if (IS_ERR(dpi->pins_gpio)) { + dpi->pins_gpio = NULL; + dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); + } + if (dpi->pins_gpio) + pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); + + dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default"); + if (IS_ERR(dpi->pins_dpi)) { + dpi->pins_dpi = NULL; + dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); + } + } mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); dpi->regs = devm_ioremap_resource(dev, mem); if (IS_ERR(dpi->regs)) { From da2a97323133d0c7caeee399881a590eb8e83c34 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Sat, 11 Apr 2020 15:44:05 +0800 Subject: [PATCH 3/9] dt-bindings: display: mediatek: add property to control mipi tx drive current Add a property to control mipi tx drive current: "drive-strength-microamp" Signed-off-by: Jitao Shi Reviewed-by: Rob Herring Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index a19a6cc375ed..d78b6d6d8fab 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -33,6 +33,10 @@ Required properties: - #clock-cells: must be <0>; - #phy-cells: must be <0>. +Optional properties: +- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And + the step is 200. + Example: mipi_tx0: mipi-dphy@10215000 { @@ -42,6 +46,7 @@ mipi_tx0: mipi-dphy@10215000 { clock-output-names = "mipi_tx0_pll"; #clock-cells = <0>; #phy-cells = <0>; + drive-strength-microamp = <4600>; }; dsi0: dsi@1401b000 { From 6d3a4aeff2fb4f41ab32cc0d445eebdaa01059df Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Sat, 11 Apr 2020 15:44:06 +0800 Subject: [PATCH 4/9] dt-bindings: display: mediatek: get mipitx calibration data from nvmem Add properties to get get mipitx calibration data. Reviewed-by: Rob Herring Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index d78b6d6d8fab..8e4729de8c85 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -36,6 +36,9 @@ Required properties: Optional properties: - drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And the step is 200. +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If + unspecified default values shall be used. +- nvmem-cell-names: Should be "calibration-data" Example: @@ -47,6 +50,8 @@ mipi_tx0: mipi-dphy@10215000 { #clock-cells = <0>; #phy-cells = <0>; drive-strength-microamp = <4600>; + nvmem-cells= <&mipi_tx_calibration>; + nvmem-cell-names = "calibration-data"; }; dsi0: dsi@1401b000 { From 3d50b59abf64dcaee8595a7c12185a5a75a0782a Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Sat, 11 Apr 2020 15:44:07 +0800 Subject: [PATCH 5/9] drm/mediatek: add the mipitx driving control Add a property in device tree to control the driving by different board. Reviewed-by: Matthias Brugger Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 14 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 1 + drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 7 +++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index e4d34484ecc8..e301af64809e 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) return ret; } + ret = of_property_read_u32(dev->of_node, "drive-strength-microamp", + &mipi_tx->mipitx_drive); + /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */ + if (ret < 0) + mipi_tx->mipitx_drive = 4600; + + /* check the mipitx_drive valid */ + if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) { + dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n", + mipi_tx->mipitx_drive); + mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000, + 6000); + } + ref_clk_name = __clk_get_name(ref_clk); ret = of_property_read_string(dev->of_node, "clock-output-names", diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h index 413f35d86219..eea44327fe9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h @@ -27,6 +27,7 @@ struct mtk_mipi_tx { struct device *dev; void __iomem *regs; u32 data_rate; + u32 mipitx_drive; const struct mtk_mipitx_data *driver_data; struct clk_hw pll_hw; struct clk *pll; diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index 91f08a351fd0..e4cc967750cb 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -17,6 +17,9 @@ #define RG_DSI_BG_CORE_EN BIT(7) #define RG_DSI_PAD_TIEL_SEL BIT(8) +#define MIPITX_VOLTAGE_SEL 0x0010 +#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6) + #define MIPITX_PLL_PWR 0x0028 #define MIPITX_PLL_CON0 0x002c #define MIPITX_PLL_CON1 0x0030 @@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL, + RG_DSI_HSTX_LDO_REF_SEL, + (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); } From 424a3a706aac4ec70de4414f5bce62c09a3d76e1 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Sat, 11 Apr 2020 15:44:08 +0800 Subject: [PATCH 6/9] drm/mediatek: config mipitx impedance with calibration data Read calibration data from nvmem, and config mipitx impedance with calibration data to make sure their impedance are 100ohm. Signed-off-by: Jitao Shi Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 40 +++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 3 ++ drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 21 ++++++++++ 3 files changed, 64 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index e301af64809e..8cee2591e728 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -88,6 +88,44 @@ static const struct phy_ops mtk_mipi_tx_ops = { .owner = THIS_MODULE, }; +static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx) +{ + struct nvmem_cell *cell; + size_t len; + u32 *buf; + + cell = nvmem_cell_get(mipi_tx->dev, "calibration-data"); + if (IS_ERR(cell)) { + dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n"); + return; + } + buf = (u32 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) { + dev_info(mipi_tx->dev, "can't get data, ignore it\n"); + return; + } + + if (len < 3 * sizeof(u32)) { + dev_info(mipi_tx->dev, "invalid calibration data\n"); + kfree(buf); + return; + } + + mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | + (buf[0] >> 11 & 0x1f); + mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | + (buf[0] >> 1 & 0x1f); + mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | + (buf[1] >> 22 & 0x1f); + mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | + (buf[1] >> 12 & 0x1f); + mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | + (buf[1] >> 2 & 0x1f); + kfree(buf); +} + static int mtk_mipi_tx_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -174,6 +212,8 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) mipi_tx->dev = dev; + mtk_mipi_tx_get_calibration_datal(mipi_tx); + return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, mipi_tx->pll); } diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h index eea44327fe9f..c76f07c3fdeb 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h @@ -12,9 +12,11 @@ #include #include #include +#include #include #include #include +#include struct mtk_mipitx_data { const u32 mppll_preserve; @@ -28,6 +30,7 @@ struct mtk_mipi_tx { void __iomem *regs; u32 data_rate; u32 mipitx_drive; + u32 rt_code[5]; const struct mtk_mipitx_data *driver_data; struct clk_hw pll_hw; struct clk *pll; diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index e4cc967750cb..9f3e55aeebb2 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -28,6 +28,7 @@ #define MIPITX_PLL_CON4 0x003c #define RG_DSI_PLL_IBIAS (3 << 10) +#define MIPITX_D2P_RTCODE 0x0100 #define MIPITX_D2_SW_CTL_EN 0x0144 #define MIPITX_D0_SW_CTL_EN 0x0244 #define MIPITX_CK_CKMODE_EN 0x0328 @@ -108,6 +109,24 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { .recalc_rate = mtk_mipi_tx_pll_recalc_rate, }; +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) +{ + int i, j; + + for (i = 0; i < 5; i++) { + if ((mipi_tx->rt_code[i] & 0x1f) == 0) + mipi_tx->rt_code[i] |= 0x10; + + if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0) + mipi_tx->rt_code[i] |= 0x10 << 5; + + for (j = 0; j < 10; j++) + mtk_mipi_tx_update_bits(mipi_tx, + MIPITX_D2P_RTCODE * (i + 1) + j * 4, + 1, mipi_tx->rt_code[i] >> j & 1); + } +} + static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); @@ -130,6 +149,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) RG_DSI_HSTX_LDO_REF_SEL, (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_mipi_tx_config_calibration_data(mipi_tx); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); } From 9a67bc4aac82d18132e8a5677926f05d43e44e77 Mon Sep 17 00:00:00 2001 From: Anand K Mistry Date: Mon, 20 Apr 2020 16:08:34 +1000 Subject: [PATCH 7/9] drm/mediatek: Stop iterating dma addresses when sg_dma_len() == 0 If dma_map_sg() merges pages when creating the mapping, only the first entries will have a valid sg_dma_address() and sg_dma_len(), followed by entries with sg_dma_len() == 0. Signed-off-by: Anand K Mistry Signed-off-by: Anand K Mistry Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_drm_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index b04a3c2b111e..f8fd8b98c30e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c @@ -224,6 +224,9 @@ struct drm_gem_object *mtk_gem_prime_import_sg_table(struct drm_device *dev, expected = sg_dma_address(sg->sgl); for_each_sg(sg->sgl, s, sg->nents, i) { + if (!sg_dma_len(s)) + break; + if (sg_dma_address(s) != expected) { DRM_ERROR("sg_table is not contiguous"); ret = -EINVAL; From 3cda3d31c50cb03d41880d8c5d83ed16e16b3a9d Mon Sep 17 00:00:00 2001 From: Bernard Zhao Date: Wed, 6 May 2020 05:33:55 -0700 Subject: [PATCH 8/9] drm/mediatek: Cleanup coding style in mediatek a bit This code change is to make code bit more readable. Signed-off-by: Bernard Zhao Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index ff43a3d80410..43e9876fd50c 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -311,14 +311,10 @@ static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, u8 checksum; int ctrl_frame_en = 0; - frame_type = *buffer; - buffer += 1; - frame_ver = *buffer; - buffer += 1; - frame_len = *buffer; - buffer += 1; - checksum = *buffer; - buffer += 1; + frame_type = *buffer++; + frame_ver = *buffer++; + frame_len = *buffer++; + checksum = *buffer++; frame_data = buffer; dev_dbg(hdmi->dev, From 3852489c79abe31101f07e395c63cce64de0c6d6 Mon Sep 17 00:00:00 2001 From: Bernard Zhao Date: Wed, 6 May 2020 05:42:55 -0700 Subject: [PATCH 9/9] drm/mediatek: Eliminate the magic number in array size Eiminate the magic number in array size, there macro defines in hdmi.h. Signed-off-by: Bernard Zhao Signed-off-by: Chun-Kuang Hu --- drivers/gpu/drm/mediatek/mtk_hdmi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c index 43e9876fd50c..7bc086ec74f7 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c @@ -978,7 +978,7 @@ static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, struct drm_display_mode *mode) { struct hdmi_avi_infoframe frame; - u8 buffer[17]; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; ssize_t err; err = drm_hdmi_avi_infoframe_from_display_mode(&frame, @@ -1004,7 +1004,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, const char *product) { struct hdmi_spd_infoframe frame; - u8 buffer[29]; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; ssize_t err; err = hdmi_spd_infoframe_init(&frame, vendor, product); @@ -1027,7 +1027,7 @@ static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) { struct hdmi_audio_infoframe frame; - u8 buffer[14]; + u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; ssize_t err; err = hdmi_audio_infoframe_init(&frame);