ce4100: Add errata fixes for UART on CE4100
This patch enables the UART on the CE4100. The UART has a couple of issues that need to be worked around. First the UART is mostly PC compatible except that it is clocked eight times faster than a standard PC so the default configuration provided in arch/x86/include/asm/serial.h needs to be overridden. Second the TX interrupt may not be set correctly all the time. Lastly accessing the UART via I/O space for early_prink() hangs the chip when the IOAPIC is enabled. A custom mem_serial_in() is provided to work around the TX interrupt issue. The configuration issues are dealt with in the call back registered with the 8250 driver via serial8250_set_isa_configurator() Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com> LKML-Reference: <1290436128-17958-1-git-send-email-dirk.brandewie@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -12,20 +12,110 @@
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/serial_reg.h>
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#include <linux/serial_8250.h>
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#include <asm/setup.h>
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#include <asm/io.h>
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static int ce4100_i8042_detect(void)
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{
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return 0;
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}
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static void __init sdv_arch_setup(void)
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static void __init sdv_find_smp_config(void)
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{
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}
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static void __init sdv_find_smp_config(void)
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#ifdef CONFIG_SERIAL_8250
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static unsigned int mem_serial_in(struct uart_port *p, int offset)
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{
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offset = offset << p->regshift;
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return readl(p->membase + offset);
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}
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/*
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* The UART Tx interrupts are not set under some conditions and therefore serial
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* transmission hangs. This is a silicon issue and has not been root caused. The
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* workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
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* bit of LSR register in interrupt handler to see whether at least one of these
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* two bits is set, if so then process the transmit request. If this workaround
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* is not applied, then the serial transmission may hang. This workaround is for
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* errata number 9 in Errata - B step.
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*/
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static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
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{
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unsigned int ret, ier, lsr;
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if (offset == UART_IIR) {
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offset = offset << p->regshift;
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ret = readl(p->membase + offset);
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if (ret & UART_IIR_NO_INT) {
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/* see if the TX interrupt should have really set */
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ier = mem_serial_in(p, UART_IER);
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/* see if the UART's XMIT interrupt is enabled */
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if (ier & UART_IER_THRI) {
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lsr = mem_serial_in(p, UART_LSR);
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/* now check to see if the UART should be
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generating an interrupt (but isn't) */
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if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
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ret &= ~UART_IIR_NO_INT;
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}
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}
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} else
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ret = mem_serial_in(p, offset);
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return ret;
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}
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static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
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{
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offset = offset << p->regshift;
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writel(value, p->membase + offset);
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}
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static void ce4100_serial_fixup(int port, struct uart_port *up,
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unsigned short *capabilites)
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{
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#ifdef CONFIG_EARLY_PRINTK
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/*
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* Over ride the legacy port configuration that comes from
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* asm/serial.h. Using the ioport driver then switching to the
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* PCI memmaped driver hangs the IOAPIC
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*/
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if (up->iotype != UPIO_MEM32) {
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up->uartclk = 14745600;
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up->mapbase = 0xdffe0200;
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set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
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up->mapbase & PAGE_MASK);
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up->membase =
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(void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
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up->membase += up->mapbase & ~PAGE_MASK;
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up->iotype = UPIO_MEM32;
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up->regshift = 2;
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}
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#endif
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up->iobase = 0;
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up->serial_in = ce4100_mem_serial_in;
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up->serial_out = ce4100_mem_serial_out;
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*capabilites |= (1 << 12);
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}
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static __init void sdv_serial_fixup(void)
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{
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serial8250_set_isa_configurator(ce4100_serial_fixup);
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}
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#else
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static inline void sdv_serial_fixup(void);
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#endif
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static void __init sdv_arch_setup(void)
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{
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sdv_serial_fixup();
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}
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/*
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