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ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x 

Use a generic name for this kind of PLL

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
This commit is contained in:
Gabriel Fernandez 2015-06-23 16:09:00 +02:00 committed by Maxime Coquelin
parent 0a8c739c06
commit 5eb26c6059
4 changed files with 8 additions and 8 deletions
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4
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
View File

@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"

4
arch/arm/boot/dts/stih407-clock.dtsi
View File

@ -134,7 +134,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@ -143,7 +143,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;

4
arch/arm/boot/dts/stih410-clock.dtsi
View File

@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;

4
arch/arm/boot/dts/stih418-clock.dtsi
View File

@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;