soc/tegra: Implement Tegra186 PMC support
The power management controller on Tegra186 has changed in backwards- incompatible ways with respect to earlier generations. This implements a new driver that supports inversion of the PMU interrupt as well as the "recovery", "bootloader" and "forced-recovery" reboot commands. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
c1ae3cfa0e
commit
5e7d4c6529
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@ -0,0 +1,34 @@
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NVIDIA Tegra Power Management Controller (PMC)
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Required properties:
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- compatible: Should contain one of the following:
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- "nvidia,tegra186-pmc": for Tegra186
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- reg: Must contain an (offset, length) pair of the register set for each
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entry in reg-names.
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- reg-names: Must include the following entries:
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- "pmc"
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- "wake"
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- "aotag"
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- "scratch"
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Optional properties:
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- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
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Example:
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SoC DTSI:
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pmc@c3600000 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0 0x0c360000 0 0x10000>,
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<0 0x0c370000 0 0x10000>,
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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};
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Board DTS:
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pmc@c360000 {
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nvidia,invert-interrupt;
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};
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@ -12,6 +12,7 @@ config ARCH_TEGRA_2x_SOC
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select PINCTRL_TEGRA20
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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@ -23,6 +24,7 @@ config ARCH_TEGRA_3x_SOC
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA30
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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@ -33,6 +35,7 @@ config ARCH_TEGRA_114_SOC
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA114
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T114 processor family, based on the
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@ -42,6 +45,7 @@ config ARCH_TEGRA_124_SOC
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bool "Enable support for Tegra124 family"
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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@ -55,6 +59,7 @@ if ARM64
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config ARCH_TEGRA_132_SOC
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bool "NVIDIA Tegra132 SoC"
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select PINCTRL_TEGRA124
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select SOC_TEGRA_PMC
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help
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Enable support for NVIDIA Tegra132 SoC, based on the Denver
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ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
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@ -64,6 +69,7 @@ config ARCH_TEGRA_132_SOC
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config ARCH_TEGRA_210_SOC
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bool "NVIDIA Tegra210 SoC"
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select PINCTRL_TEGRA210
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select SOC_TEGRA_PMC
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help
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Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
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the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
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@ -83,6 +89,7 @@ config ARCH_TEGRA_186_SOC
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select TEGRA_BPMP
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select TEGRA_HSP_MBOX
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select TEGRA_IVC
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select SOC_TEGRA_PMC_TEGRA186
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help
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Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
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combination of Denver and Cortex-A57 CPU cores and a GPU based on
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@ -93,3 +100,9 @@ config ARCH_TEGRA_186_SOC
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endif
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endif
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config SOC_TEGRA_PMC
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bool
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config SOC_TEGRA_PMC_TEGRA186
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bool
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@ -1,4 +1,5 @@
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obj-y += fuse/
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obj-y += common.o
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obj-y += pmc.o
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obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
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obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o
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@ -0,0 +1,169 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#define pr_fmt(fmt) "tegra-pmc: " fmt
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <asm/system_misc.h>
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#define PMC_CNTRL 0x000
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define PMC_RST_STATUS 0x070
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#define WAKE_AOWAKE_CTRL 0x4f4
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#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
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#define SCRATCH_SCRATCH0 0x2000
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#define SCRATCH_SCRATCH0_MODE_RECOVERY BIT(31)
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#define SCRATCH_SCRATCH0_MODE_BOOTLOADER BIT(30)
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#define SCRATCH_SCRATCH0_MODE_RCM BIT(1)
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#define SCRATCH_SCRATCH0_MODE_MASK (SCRATCH_SCRATCH0_MODE_RECOVERY | \
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SCRATCH_SCRATCH0_MODE_BOOTLOADER | \
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SCRATCH_SCRATCH0_MODE_RCM)
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struct tegra_pmc {
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struct device *dev;
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void __iomem *regs;
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void __iomem *wake;
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void __iomem *aotag;
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void __iomem *scratch;
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void (*system_restart)(enum reboot_mode mode, const char *cmd);
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struct notifier_block restart;
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};
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static int tegra186_pmc_restart_notify(struct notifier_block *nb,
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unsigned long action,
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void *data)
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{
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struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, restart);
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const char *cmd = data;
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u32 value;
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value = readl(pmc->scratch + SCRATCH_SCRATCH0);
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value &= ~SCRATCH_SCRATCH0_MODE_MASK;
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if (cmd) {
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if (strcmp(cmd, "recovery") == 0)
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value |= SCRATCH_SCRATCH0_MODE_RECOVERY;
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if (strcmp(cmd, "bootloader") == 0)
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value |= SCRATCH_SCRATCH0_MODE_BOOTLOADER;
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if (strcmp(cmd, "forced-recovery") == 0)
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value |= SCRATCH_SCRATCH0_MODE_RCM;
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}
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writel(value, pmc->scratch + SCRATCH_SCRATCH0);
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/*
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* If available, call the system restart implementation that was
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* registered earlier (typically PSCI).
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*/
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if (pmc->system_restart) {
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pmc->system_restart(reboot_mode, cmd);
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return NOTIFY_DONE;
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}
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/* reset everything but SCRATCH0_SCRATCH0 and PMC_RST_STATUS */
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value = readl(pmc->regs + PMC_CNTRL);
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value |= PMC_CNTRL_MAIN_RST;
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writel(value, pmc->regs + PMC_CNTRL);
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return NOTIFY_DONE;
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}
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static int tegra186_pmc_setup(struct tegra_pmc *pmc)
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{
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struct device_node *np = pmc->dev->of_node;
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bool invert;
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u32 value;
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invert = of_property_read_bool(np, "nvidia,invert-interrupt");
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value = readl(pmc->wake + WAKE_AOWAKE_CTRL);
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if (invert)
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value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
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else
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value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
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writel(value, pmc->wake + WAKE_AOWAKE_CTRL);
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/*
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* We need to hook any system restart implementation registered
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* previously so we can write SCRATCH_SCRATCH0 before reset.
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*/
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pmc->system_restart = arm_pm_restart;
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arm_pm_restart = NULL;
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pmc->restart.notifier_call = tegra186_pmc_restart_notify;
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pmc->restart.priority = 128;
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return register_restart_handler(&pmc->restart);
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}
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static int tegra186_pmc_probe(struct platform_device *pdev)
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{
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struct tegra_pmc *pmc;
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struct resource *res;
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pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL);
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if (!pmc)
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return -ENOMEM;
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pmc->dev = &pdev->dev;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmc");
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pmc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pmc->regs))
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return PTR_ERR(pmc->regs);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
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pmc->wake = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pmc->wake))
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return PTR_ERR(pmc->wake);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
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pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pmc->aotag))
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return PTR_ERR(pmc->aotag);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
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pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pmc->scratch))
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return PTR_ERR(pmc->scratch);
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return tegra186_pmc_setup(pmc);
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}
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static const struct of_device_id tegra186_pmc_of_match[] = {
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{ .compatible = "nvidia,tegra186-pmc" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, tegra186_pmc_of_match);
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static struct platform_driver tegra186_pmc_driver = {
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.driver = {
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.name = "tegra186-pmc",
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.of_match_table = tegra186_pmc_of_match,
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},
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.probe = tegra186_pmc_probe,
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};
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builtin_platform_driver(tegra186_pmc_driver);
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