phy: miphy28lp: Add Device Tree bindings for the MiPHY28lp
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Gabriel FERNANDEZ
Kishon Vijay Abraham I
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2fbbc96d16
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STMicroelectronics STi MIPHY28LP PHY binding
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============================================
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This binding describes a miphy device that is used to control PHY hardware
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for SATA, PCIe or USB3.
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Required properties (controller (parent) node):
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- compatible : Should be "st,miphy28lp-phy".
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- st,syscfg : Should be a phandle of the system configuration register group
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which contain the SATA, PCIe or USB3 mode setting bits.
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Required nodes : A sub-node is required for each channel the controller
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provides. Address range information including the usual
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'reg' and 'reg-names' properties are used inside these
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nodes to describe the controller's topology. These nodes
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are translated by the driver's .xlate() function.
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Required properties (port (child) node):
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- #phy-cells : Should be 1 (See second example)
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Cell after port phandle is device type from:
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- PHY_TYPE_SATA
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- PHY_TYPE_PCI
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- PHY_TYPE_USB3
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- reg : Address and length of the register set for the device.
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- reg-names : The names of the register addresses corresponding to the registers
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filled in "reg". It can also contain the offset of the system configuration
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registers used as glue-logic to setup the device for SATA/PCIe or USB3
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devices.
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- resets : phandle to the parent reset controller.
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- reset-names : Associated name must be "miphy-sw-rst".
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Optional properties (port (child) node):
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- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
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is not available in all the MiPHY. For example, for STiH407, only the
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MiPHY0 has this bit.
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- st,osc-force-ext : to select the external oscillator. This can change from
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different MiPHY inside the same SoC.
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- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
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register.
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- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
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line).
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example:
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miphy28lp_phy: miphy28lp@9b22000 {
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compatible = "st,miphy28lp-phy";
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st,syscfg = <&syscfg_core>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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phy_port0: port@9b22000 {
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reg = <0x9b22000 0xff>,
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<0x9b09000 0xff>,
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<0x9b04000 0xff>,
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<0x114 0x4>, /* sysctrl MiPHY cntrl */
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<0x818 0x4>, /* sysctrl MiPHY status*/
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<0xe0 0x4>, /* sysctrl PCIe */
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<0xec 0x4>; /* sysctrl SATA */
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reg-names = "sata-up",
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"pcie-up",
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"pipew",
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"miphy-ctrl-glue",
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"miphy-status-glue",
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"pcie-glue",
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"sata-glue";
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#phy-cells = <1>;
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st,osc-rdy;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
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};
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phy_port1: port@9b2a000 {
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reg = <0x9b2a000 0xff>,
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<0x9b19000 0xff>,
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<0x9b14000 0xff>,
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<0x118 0x4>,
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<0x81c 0x4>,
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<0xe4 0x4>,
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<0xf0 0x4>;
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reg-names = "sata-up",
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"pcie-up",
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"pipew",
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"miphy-ctrl-glue",
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"miphy-status-glue",
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"pcie-glue",
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"sata-glue";
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#phy-cells = <1>;
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st,osc-force-ext;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
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};
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phy_port2: port@8f95000 {
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reg = <0x8f95000 0xff>,
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<0x8f90000 0xff>,
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<0x11c 0x4>,
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<0x820 0x4>;
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reg-names = "pipew",
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"usb3-up",
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"miphy-ctrl-glue",
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"miphy-status-glue";
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#phy-cells = <1>;
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reset-names = "miphy-sw-rst";
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resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
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};
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};
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Specifying phy control of devices
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=================================
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Device nodes should specify the configuration required in their "phys"
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property, containing a phandle to the miphy device node and an index
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specifying which configuration to use, as described in phy-bindings.txt.
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example:
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sata0: sata@9b20000 {
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...
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phys = <&phy_port0 PHY_TYPE_SATA>;
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...
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};
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Macro definitions for the supported miphy configuration can be found in:
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include/dt-bindings/phy/phy-miphy28lp.h
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