brcmsmac: remove references to PCI
There are no devices which are using bcma and have a PCI bus, just a PCIe bus or something else. bcma does not support PCI devices, so lets also remove PCI support from brcmsmac. All devices currently supported by brcmsmac are PCIe based. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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5d661a740a
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@ -320,7 +320,6 @@
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#define IS_SIM(chippkg) \
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#define IS_SIM(chippkg) \
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((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
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((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
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#define PCI(sih) (ai_get_buscoretype(sih) == PCI_CORE_ID)
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#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
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#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
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#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
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#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
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@ -453,36 +452,9 @@ struct aidmp {
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u32 componentid3; /* 0xffc */
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u32 componentid3; /* 0xffc */
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};
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};
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/* return true if PCIE capability exists in the pci config space */
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static bool ai_ispcie(struct si_info *sii)
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{
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u8 cap_ptr;
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cap_ptr =
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pcicore_find_pci_capability(sii->pcibus, PCI_CAP_ID_EXP, NULL,
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NULL);
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if (!cap_ptr)
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return false;
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return true;
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}
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static bool ai_buscore_prep(struct si_info *sii)
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{
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/* kludge to enable the clock on the 4306 which lacks a slowclock */
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if (!ai_ispcie(sii))
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ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
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return true;
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}
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static bool
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static bool
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ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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{
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{
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struct bcma_device *pci = NULL;
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struct bcma_device *pcie = NULL;
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struct bcma_device *core;
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/* no cores found, bail out */
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/* no cores found, bail out */
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if (cc->bus->nr_cores == 0)
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if (cc->bus->nr_cores == 0)
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return false;
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return false;
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@ -504,30 +476,7 @@ ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
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}
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}
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/* figure out buscore */
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/* figure out buscore */
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list_for_each_entry(core, &cc->bus->cores, list) {
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sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
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uint cid, crev;
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cid = core->id.id;
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crev = core->id.rev;
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if (cid == PCI_CORE_ID) {
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pci = core;
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} else if (cid == PCIE_CORE_ID) {
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pcie = core;
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}
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}
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if (pci && pcie) {
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if (ai_ispcie(sii))
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pci = NULL;
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else
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pcie = NULL;
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}
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if (pci) {
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sii->buscore = pci;
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} else if (pcie) {
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sii->buscore = pcie;
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}
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/* fixup necessary chip/core configurations */
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/* fixup necessary chip/core configurations */
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if (!sii->pch) {
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if (!sii->pch) {
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@ -557,10 +506,6 @@ static struct si_info *ai_doattach(struct si_info *sii,
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/* switch to Chipcommon core */
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/* switch to Chipcommon core */
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cc = pbus->drv_cc.core;
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cc = pbus->drv_cc.core;
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/* bus/core/clk setup for register access */
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if (!ai_buscore_prep(sii))
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return NULL;
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sih->chip = pbus->chipinfo.id;
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sih->chip = pbus->chipinfo.id;
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sih->chiprev = pbus->chipinfo.rev;
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sih->chiprev = pbus->chipinfo.rev;
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sih->chippkg = pbus->chipinfo.pkg;
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sih->chippkg = pbus->chipinfo.pkg;
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@ -816,69 +761,6 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
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return fpdelay;
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return fpdelay;
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}
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}
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/* turn primary xtal and/or pll off/on */
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int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
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{
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struct si_info *sii;
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u32 in, out, outen;
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sii = (struct si_info *)sih;
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/* pcie core doesn't have any mapping to control the xtal pu */
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if (PCIE(sih))
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return -1;
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pci_read_config_dword(sii->pcibus, PCI_GPIO_IN, &in);
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pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, &out);
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pci_read_config_dword(sii->pcibus, PCI_GPIO_OUTEN, &outen);
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/*
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* Avoid glitching the clock if GPRS is already using it.
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* We can't actually read the state of the PLLPD so we infer it
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* by the value of XTAL_PU which *is* readable via gpioin.
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*/
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if (on && (in & PCI_CFG_GPIO_XTAL))
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return 0;
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if (what & XTAL)
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outen |= PCI_CFG_GPIO_XTAL;
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if (what & PLL)
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outen |= PCI_CFG_GPIO_PLL;
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if (on) {
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/* turn primary xtal on */
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if (what & XTAL) {
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out |= PCI_CFG_GPIO_XTAL;
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if (what & PLL)
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out |= PCI_CFG_GPIO_PLL;
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pci_write_config_dword(sii->pcibus,
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PCI_GPIO_OUT, out);
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pci_write_config_dword(sii->pcibus,
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PCI_GPIO_OUTEN, outen);
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udelay(XTAL_ON_DELAY);
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}
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/* turn pll on */
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if (what & PLL) {
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out &= ~PCI_CFG_GPIO_PLL;
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pci_write_config_dword(sii->pcibus,
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PCI_GPIO_OUT, out);
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mdelay(2);
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}
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} else {
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if (what & XTAL)
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out &= ~PCI_CFG_GPIO_XTAL;
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if (what & PLL)
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out |= PCI_CFG_GPIO_PLL;
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pci_write_config_dword(sii->pcibus,
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PCI_GPIO_OUT, out);
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pci_write_config_dword(sii->pcibus,
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PCI_GPIO_OUTEN, outen);
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}
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return 0;
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}
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/* clk control mechanism through chipcommon, no policy checking */
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/* clk control mechanism through chipcommon, no policy checking */
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static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
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{
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{
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@ -985,16 +867,12 @@ void ai_pci_setup(struct si_pub *sih, uint coremask)
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* Enable sb->pci interrupts. Assume
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* Enable sb->pci interrupts. Assume
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* PCI rev 2.3 support was added in pci core rev 6 and things changed..
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* PCI rev 2.3 support was added in pci core rev 6 and things changed..
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*/
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*/
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if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
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if (PCIE(sih)) {
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/* pci config write to set this core bit in PCIIntMask */
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/* pci config write to set this core bit in PCIIntMask */
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pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
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pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
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w |= (coremask << PCI_SBIM_SHIFT);
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w |= (coremask << PCI_SBIM_SHIFT);
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pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
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pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
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}
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}
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if (PCI(sih)) {
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pcicore_pci_setup(sii->pch);
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}
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}
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}
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/*
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/*
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@ -200,7 +200,6 @@ extern void ai_pci_setup(struct si_pub *sih, uint coremask);
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extern void ai_clkctl_init(struct si_pub *sih);
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extern void ai_clkctl_init(struct si_pub *sih);
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extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
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extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
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extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
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extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
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extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
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extern bool ai_deviceremoved(struct si_pub *sih);
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extern bool ai_deviceremoved(struct si_pub *sih);
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extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
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extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
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u8 priority);
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u8 priority);
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@ -1910,9 +1910,6 @@ static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
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if (!want && wlc_hw->pllreq)
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if (!want && wlc_hw->pllreq)
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return;
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return;
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if (wlc_hw->sih)
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ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
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wlc_hw->sbclk = want;
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wlc_hw->sbclk = want;
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if (!wlc_hw->sbclk) {
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if (!wlc_hw->sbclk) {
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wlc_hw->clk = false;
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wlc_hw->clk = false;
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@ -240,6 +240,7 @@ static void pr28829_delay(void)
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struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
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struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
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{
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{
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struct pcicore_info *pi;
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struct pcicore_info *pi;
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u8 cap_ptr;
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/* alloc struct pcicore_info */
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/* alloc struct pcicore_info */
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pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
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pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
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@ -250,12 +251,9 @@ struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
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pi->dev = core->bus->host_pci;
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pi->dev = core->bus->host_pci;
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pi->core = core;
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pi->core = core;
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if (core->id.id == PCIE_CORE_ID) {
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cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
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u8 cap_ptr;
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cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
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NULL, NULL);
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NULL, NULL);
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pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
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pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
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}
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return pi;
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return pi;
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}
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}
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@ -791,18 +789,7 @@ void pcicore_fixcfg(struct pcicore_info *pi)
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u16 val16;
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u16 val16;
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uint regoff;
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uint regoff;
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switch (pi->core->id.id) {
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regoff = PCIEREGOFFS(sprom[SRSH_PI_OFFSET]);
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case BCMA_CORE_PCI:
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regoff = PCIREGOFFS(sprom[SRSH_PI_OFFSET]);
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break;
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case BCMA_CORE_PCIE:
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regoff = PCIEREGOFFS(sprom[SRSH_PI_OFFSET]);
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break;
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default:
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return;
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}
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val16 = bcma_read16(pi->core, regoff);
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val16 = bcma_read16(pi->core, regoff);
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if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) !=
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if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) !=
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bcma_write16(pi->core, regoff, val16);
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bcma_write16(pi->core, regoff, val16);
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}
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}
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}
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}
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/* precondition: current core is pci core */
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void
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pcicore_pci_setup(struct pcicore_info *pi)
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{
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bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
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SBTOPCI_PREF | SBTOPCI_BURST);
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if (pi->core->id.rev >= 11) {
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bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
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SBTOPCI_RC_READMULTI);
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bcma_set32(pi->core, PCIREGOFFS(clkrun), PCI_CLKRUN_DSBL);
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(void)bcma_read32(pi->core, PCIREGOFFS(clkrun));
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}
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}
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@ -72,6 +72,5 @@ extern void pcicore_down(struct pcicore_info *pch, int state);
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extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
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extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
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unsigned char *buf, u32 *buflen);
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unsigned char *buf, u32 *buflen);
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extern void pcicore_fixcfg(struct pcicore_info *pch);
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extern void pcicore_fixcfg(struct pcicore_info *pch);
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extern void pcicore_pci_setup(struct pcicore_info *pch);
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#endif /* _BRCM_NICPCI_H_ */
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#endif /* _BRCM_NICPCI_H_ */
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