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Pin control changes for kernel v4.6: 

An almost purely driver related set of changes with no
 major changes to the framework, only one patch adding
 an unlocked version of the pinctrl_find_gpio_range_from_pin()
 library call.
 
 New drivers:
 - ST Microelectronics STM32 MCU support: this is a non-MMU
   low-end platform for IoT things (etc).
 - Microchip PIC32 MCU support: same story as for STM32.
 
 New subdrivers:
 - Allwinner SunXi H3 R_PIO controller support.
 - Qualcomm IPQ4019 support.
 - MediaTek MT2701 and MT7623.
 - Allwinner A64
 
 Non-critical fixes:
 - gpio_disable_free() for the Vybrid.
 - pinctrl single: use a separate lockdep class.
 
 Misc:
 - Substantial cleanups and rewrites for the Super-H PFC
   driver and subdrivers.
 - Various fixes and cleanups, especially Paul Gortmakers
   work to make nonmodular drivers nonmodular.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJW5rS1AAoJEEEQszewGV1zskIQALNriHdVmPGNIuSZOUk2gqAv
 hFNIzFUYM6BK6AL2wD+ZVqQe/EbZtWUF2RqhI2juP8j2WBVMxo8B9ypGjm8qDZ7q
 Xtdnd8l22VP0fEmYKTwDgrjSCcMxbXFiPurZBlqCCyb/9raFqLKwx2kcxWqD4PR2
 dcC8i/t2JSjGYRRCMcGn+zcKW2zja36xci/ZOExdioHYgFmorCZb9+4NYz+coijv
 VEjEy98CG6itBFJ0MS3jHT949TyxpDzWp7hO8LiOAiLR50xCxTlZRT1dObOUQJqk
 qhiLK2sTUFJFlTNBUGN0gfMoJo2MpfJIkVre4EV5QNkfy8vjtXeLrbjnSnTXf0r7
 5OLMEJPK7mfHd7jsw/nwJMYUoqgeRO9VBXtL2JyGWpsNFBFlJv1YRXaT0AZXkgUq
 63BfhTrbtge2xECJ9iqWVdGmmNv2x7lMK6RWqDr72fjONdtmNLDusfNdgYaBWc50
 K910IijMX2t2HGQFzuqwQC5HgADPhqBRb2eMcilwwUs5rxzLXX/wer1rhc8guUtK
 4DvGZ+wPZd2znQvNAWxsG5azoSfO8J3ibVIkMmaW3NTqyLvnbT9KiNvYuUVg/9NQ
 Vcb1d9UnrhAIWzpfpeo4rzr+QIq4j46YHBqreiW/l952Apxpp2lJmV/btK0noPmA
 MDTknHc2772QYIBtn01D
 =TsdU
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "An almost purely driver related set of changes with no major changes
  to the framework, only one patch adding an unlocked version of the
  pinctrl_find_gpio_range_from_pin() library call.

  New drivers:
   - ST Microelectronics STM32 MCU support: this is a non-MMU low-end
     platform for IoT things (etc).
   - Microchip PIC32 MCU support: same story as for STM32.

  New subdrivers:
   - Allwinner SunXi H3 R_PIO controller support.
   - Qualcomm IPQ4019 support.
   - MediaTek MT2701 and MT7623.
   - Allwinner A64

  Non-critical fixes:
   - gpio_disable_free() for the Vybrid.
   - pinctrl single: use a separate lockdep class.

  Misc:
   - Substantial cleanups and rewrites for the Super-H PFC driver and
     subdrivers.
   - Various fixes and cleanups, especially Paul Gortmakers work to make
     nonmodular drivers nonmodular"

* tag 'pinctrl-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits)
  pinctrl: single: Use a separate lockdep class
  drivers: pinctrl: add driver for Allwinner A64 SoC
  pinctrl: Broadcom Northstar2 pinctrl device tree bindings
  pinctrl: amlogic: Make driver independent from two-domain configuration
  pinctrl: amlogic: Separate some pin functions for Meson8 / Meson8b
  pinctrl: at91: use __maybe_unused to hide pm functions
  pinctrl: sh-pfc: core: don't open code of_device_get_match_data()
  pinctrl: uniphier: rename CONFIG options and file names
  pinctrl: sunxi: make A80 explicitly non-modular
  pinctrl: stm32: make explicitly non-modular
  pinctrl: sh-pfc: make explicitly non-modular
  pinctrl: meson: make explicitly non-modular
  pinctrl: pinctrl-mt6397 driver explicitly non-modular
  pinctrl: sunxi: does not need module.h
  pinctrl: pxa2xx: export symbols
  pinctrl: sunxi: Change mux setting on PI irq pins
  pinctrl: sunxi: Remove non existing irq's
  pinctrl: imx: attach iomuxc device to gpr syscon
  pinctrl-bcm2835: Fix cut-and-paste error in "pull" parsing
  pinctrl: lpc1850-scu: document nxp,gpio-pin-interrupt
  ...
This commit is contained in:
Linus Torvalds 2016-03-15 20:23:13 -07:00
parent 710d60cbf1 3c177a1662
commit 5ca5446ec5
100 changed files with 17641 additions and 3017 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt Normal file
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@ -0,0 +1,49 @@
* Microchip PIC32 GPIO devices (PIO).
Required properties:
- compatible: "microchip,pic32mzda-gpio"
- reg: Base address and length for the device.
- interrupts: The port interrupt shared by all pins.
- gpio-controller: Marks the port as GPIO controller.
- #gpio-cells: Two. The first cell is the pin number and
the second cell is used to specify the gpio polarity as defined in
defined in <dt-bindings/gpio/gpio.h>:
0 = GPIO_ACTIVE_HIGH
1 = GPIO_ACTIVE_LOW
2 = GPIO_OPEN_DRAIN
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Two. The first cell is the GPIO number and second cell
is used to specify the trigger type as defined in
<dt-bindings/interrupt-controller/irq.h>:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
- clocks: Clock specifier (see clock bindings for details).
- microchip,gpio-bank: Specifies which bank a controller owns.
- gpio-ranges: Interaction with the PINCTRL subsystem.
Example:
/* PORTA */
gpio0: gpio0@1f860000 {
compatible = "microchip,pic32mzda-gpio";
reg = <0x1f860000 0x100>;
interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&PBCLK4>;
microchip,gpio-bank = <0>;
gpio-ranges = <&pic32_pinctrl 0 0 16>;
};
keys {
...
button@sw1 {
label = "ESC";
linux,code = <1>;
gpios = <&gpio0 12 0>;
};
};

2
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
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@ -21,6 +21,8 @@ Required properties:
"allwinner,sun9i-a80-r-pinctrl"
"allwinner,sun8i-a83t-pinctrl"
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun50i-a64-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.

102
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@ -0,0 +1,102 @@
Broadcom Northstar2 IOMUX Controller
The Northstar2 IOMUX controller supports group based mux configuration. There
are some individual pins that support modifying the pinconf parameters.
Required properties:
- compatible:
Must be "brcm,ns2-pinmux"
- reg:
Define the base and range of the I/O address space that contains the
Northstar2 IOMUX and pin configuration registers.
Properties in sub nodes:
- function:
The mux function to select
- groups:
The list of groups to select with a given function
- pins:
List of pin names to change configuration
The generic properties bias-disable, bias-pull-down, bias-pull-up,
drive-strength, slew-rate, input-enable, input-disable are supported
for some individual pins listed at the end.
For more details, refer to
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
For example:
pinctrl: pinctrl@6501d130 {
compatible = "brcm,ns2-pinmux";
reg = <0x6501d130 0x08>,
<0x660a0028 0x04>,
<0x660009b0 0x40>;
pinctrl-names = "default";
pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>;
/* Select nand function */
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
/* Pull up the uart3 rx pin */
uart3_rx: uart3_rx {
pins = "uart3_sin";
bias-pull-up;
};
/* Set the drive strength of sdio d4 pin */
sdio0_d4: sdio0_d4 {
pins = "sdio0_data4";
drive-strength = <8>;
};
};
List of supported functions and groups in Northstar2:
"nand": "nand_grp"
"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
"nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
"nor_addr_12_15_grp"
"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
"gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
"gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
"gpio_28_29_grp", "gpio_30_31_grp"
"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
"pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
"uart1_rts_cts_grp", "uart1_in_out_grp"
"uart2": "uart2_rts_cts_grp"
"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
List of pins that support pinconf parameters:
"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
"usb2_overcurrent", "sata_led1", "sata_led0"

60
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt Normal file
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@ -0,0 +1,60 @@
* Microchip PIC32 Pin Controller
Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.
PIC32 'pin configuration node' is a node of a group of pins which can be
used for a specific device or function. This node represents configuraions of
pins, optional function, and optional mux related configuration.
Required properties for pin controller node:
- compatible: "microchip,pic32mada-pinctrl"
- reg: Address range of the pinctrl registers.
- clocks: Clock specifier (see clock bindings for details)
Required properties for pin configuration sub-nodes:
- pins: List of pins to which the configuration applies.
Optional properties for pin configuration sub-nodes:
----------------------------------------------------
- function: Mux function for the specified pins.
- bias-pull-up: Enable weak pull-up.
- bias-pull-down: Enable weak pull-down.
- input-enable: Set the pin as an input.
- output-low: Set the pin as an output level low.
- output-high: Set the pin as an output level high.
- microchip,digital: Enable digital I/O.
- microchip,analog: Enable analog I/O.
Example:
pic32_pinctrl: pinctrl@1f801400{
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,pic32mzda-pinctrl";
reg = <0x1f801400 0x400>;
clocks = <&PBCLK1>;
pinctrl_uart2: pinctrl_uart2 {
uart2-tx {
pins = "G9";
function = "U2TX";
microchip,digital;
output-low;
};
uart2-rx {
pins = "B0";
function = "U2RX";
microchip,digital;
input-enable;
};
};
};
uart2: serial@1f822200 {
compatible = "microchip,pic32mzda-uart";
reg = <0x1f822200 0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
};

14
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
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@ -22,6 +22,10 @@ The following generic nodes are supported:
- input-schmitt-disable
- slew-rate
NXP specific properties:
- nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller
irq number 0 to 7. See example below.
Not all pins support all properties so either refer to the NXP 1850/4350
user manual or the pin table in the pinctrl-lpc18xx driver for supported
pin properties.
@ -54,4 +58,14 @@ pinctrl: pinctrl@40086000 {
bias-disable;
};
};
gpio_joystick_pins: gpio-joystick-pins {
gpio_joystick_1_cfg {
pins = "p9_0";
function = "gpio";
nxp,gpio-pin-interrupt = <0>;
input-enable;
bias-disable;
};
};
};

1
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
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@ -6,6 +6,7 @@ Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.

74
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt Normal file
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@ -0,0 +1,74 @@
Qualcomm Atheros IPQ4019 TLMM block
This is the Top Level Mode Multiplexor block found on the Qualcomm IPQ8019
platform, it provides pinctrl, pinmux, pinconf, and gpiolib facilities.
Required properties:
- compatible: "qcom,ipq4019-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
The first cell is the gpio pin number and the
second cell is used for optional parameters.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an abitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength.
Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
Valid values for qcom,pins are:
gpio0-gpio99
Supports mux, bias and drive-strength
Valid values for qcom,function are:
gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
Example:
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x1000000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
};

2
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
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@ -22,7 +22,7 @@ Required properties for iomux controller:
- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
"rockchip,rk3228-pinctrl", "rockchip,rk3288-pinctrl"
"rockchip,rk3368-pinctrl"
"rockchip,rk3368-pinctrl", "rockchip,rk3399-pinctrl"
- rockchip,grf: phandle referencing a syscon providing the
"general register files"

126
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt Normal file
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@ -0,0 +1,126 @@
* STM32 GPIO and Pin Mux/Config controller
STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
controller. It controls the input/output settings on the available pins and
also provides ability to multiplex and configure the output of various on-chip
controllers onto these pads.
Pin controller node:
Required properies:
- compatible: value should be one of the following:
(a) "st,stm32f429-pinctrl"
- #address-cells: The value of this property must be 1
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
GPIO controller/bank node:
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
- #gpio-cells : Should be two.
The first cell is the pin number
The second one is the polarity:
- 0 for active high
- 1 for active low
- reg : The gpio address range, relative to the pinctrl range
- clocks : clock that drives this bank
- st,bank-name : Should be a name string for this bank as specified in
the datasheet
Optional properties:
- reset: : Reference to the reset controller
Example:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
...
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x40020000 0x3000>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
resets = <&reset_ahb1 0>;
st,bank-name = "GPIOA";
};
...
pin-functions nodes follow...
};
Contents of function subnode node:
----------------------------------
Subnode format
A pinctrl node should contain at least one subnode representing the
pinctrl group available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive, output high/low and output speed.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are defined in
dt-bindings/pinctrl/<soc>-pinfunc.h directly.
These defines are calculated as:
((port * 16 + line) << 8) | function
With:
- port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
- line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
- function: The function number, can be:
* 0 : GPIO
* 1 : Alternate Function 0
* 2 : Alternate Function 1
* 3 : Alternate Function 2
* ...
* 16 : Alternate Function 15
* 17 : Analog
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
Available options are:
- bias-disable,
- bias-pull-down,
- bias-pull-up,
- drive-push-pull,
- drive-open-drain,
- output-low
- output-high
- slew-rate = <x>, with x being:
< 0 > : Low speed
< 1 > : Medium speed
< 2 > : Fast speed
< 3 > : High speed
Example:
pin-controller {
...
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
};
&usart1 {
pinctrl-0 = <&usart1_pins_a>;
pinctrl-names = "default";
status = "okay";
};

735
arch/arm/boot/dts/mt2701-pinfunc.h Normal file
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@ -0,0 +1,735 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Biao Huang <biao.huang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DTS_MT2701_PINFUNC_H
#define __DTS_MT2701_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
#endif /* __DTS_MT2701_PINFUNC_H */

52
drivers/pinctrl/Kconfig
View File

@ -79,7 +79,7 @@ config PINCTRL_AT91PIO4
controller available on sama5d2 SoC.
config PINCTRL_AMD
bool "AMD GPIO pin control"
tristate "AMD GPIO pin control"
depends on GPIOLIB
select GPIOLIB_IRQCHIP
select PINCONF
@ -168,37 +168,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_TEGRA
bool
select PINMUX
select PINCONF
config PINCTRL_TEGRA20
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA30
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA114
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA124
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA210
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA_XUSB
def_bool y if ARCH_TEGRA
select GENERIC_PHY
select PINCONF
select PINMUX
config PINCTRL_TZ1090
bool "Toumaz Xenif TZ1090 pin control driver"
depends on SOC_TZ1090
@ -238,6 +207,23 @@ config PINCTRL_PALMAS
open drain configuration for the Palmas series devices like
TPS65913, TPS80036 etc.
config PINCTRL_PIC32
bool "Microchip PIC32 pin controller driver"
depends on OF
depends on MACH_PIC32
select PINMUX
select GENERIC_PINCONF
select GPIOLIB_IRQCHIP
select OF_GPIO
help
This is the pin controller and gpio driver for Microchip PIC32
microcontrollers. This option is selected automatically when specific
machine and arch are selected to build.
config PINCTRL_PIC32MZDA
def_bool y if PIC32MZDA
select PINCTRL_PIC32
config PINCTRL_ZYNQ
bool "Pinctrl driver for Xilinx Zynq"
depends on ARCH_ZYNQ
@ -257,7 +243,9 @@ source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/tegra/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/vt8500/Kconfig"
source "drivers/pinctrl/mediatek/Kconfig"

16
drivers/pinctrl/Makefile
View File

@ -18,17 +18,12 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_SIRF) += sirf/
obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
obj-$(CONFIG_PINCTRL_TEGRA) += tegra/
obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
@ -46,12 +41,13 @@ obj-y += freescale/
obj-$(CONFIG_X86) += intel/
obj-$(CONFIG_PINCTRL_MVEBU) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_PXA) += pxa/
obj-$(CONFIG_PINCTRL_PXA) += pxa/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_PINCTRL_MTK) += mediatek/

2
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View File

@ -779,7 +779,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
}
if (num_pulls) {
err = of_property_read_u32_index(np, "brcm,pull",
(num_funcs > 1) ? i : 0, &pull);
(num_pulls > 1) ? i : 0, &pull);
if (err)
goto out;
err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,

41
drivers/pinctrl/core.c
View File

@ -481,6 +481,30 @@ int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
}
EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
unsigned int pin)
{
struct pinctrl_gpio_range *range;
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
if (range->pins) {
int a;
for (a = 0; a < range->npins; a++) {
if (range->pins[a] == pin)
return range;
}
} else if (pin >= range->pin_base &&
pin < range->pin_base + range->npins)
return range;
}
return NULL;
}
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin_nolock);
/**
* pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
* @pctldev: the pin controller device to look in
@ -493,22 +517,9 @@ pinctrl_find_gpio_range_from_pin(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range;
mutex_lock(&pctldev->mutex);
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if we're in the valid range */
if (range->pins) {
int a;
for (a = 0; a < range->npins; a++) {
if (range->pins[a] == pin)
goto out;
}
} else if (pin >= range->pin_base &&
pin < range->pin_base + range->npins)
goto out;
}
range = NULL;
out:
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
mutex_unlock(&pctldev->mutex);
return range;
}
EXPORT_SYMBOL_GPL(pinctrl_find_gpio_range_from_pin);

4
drivers/pinctrl/core.h
View File

@ -182,6 +182,10 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
}
extern struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
unsigned int pin);
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
bool dup);
void pinctrl_unregister_map(struct pinctrl_map const *map);

36
drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -15,6 +15,7 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -24,6 +25,7 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/regmap.h>
#include "../core.h"
#include "pinctrl-imx.h"
@ -341,6 +343,31 @@ mux_pin:
return 0;
}
static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
/*
* Only Vybrid has the input/output buffer enable flags (IBE/OBE)
* They are part of the shared mux/conf register.
*/
if (!(info->flags & SHARE_MUX_CONF_REG))
return;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return;
/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~0x7;
writel(reg, ipctl->base + pin_reg->mux_reg);
}
static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
@ -377,6 +404,7 @@ static const struct pinmux_ops imx_pmx_ops = {
.get_function_groups = imx_pmx_get_groups,
.set_mux = imx_pmx_set,
.gpio_request_enable = imx_pmx_gpio_request_enable,
.gpio_disable_free = imx_pmx_gpio_disable_free,
.gpio_set_direction = imx_pmx_gpio_set_direction,
};
@ -692,10 +720,12 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
int imx_pinctrl_probe(struct platform_device *pdev,
struct imx_pinctrl_soc_info *info)
{
struct regmap_config config = { .name = "gpr" };
struct device_node *dev_np = pdev->dev.of_node;
struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
struct regmap *gpr;
int ret, i;
if (!info || !info->pins || !info->npins) {
@ -704,6 +734,12 @@ int imx_pinctrl_probe(struct platform_device *pdev,
}
info->dev = &pdev->dev;
if (info->gpr_compatible) {
gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
if (!IS_ERR(gpr))
regmap_attach_dev(&pdev->dev, gpr, &config);
}
/* Create state holders etc for this driver */
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
if (!ipctl)

1
drivers/pinctrl/freescale/pinctrl-imx.h
View File

@ -82,6 +82,7 @@ struct imx_pinctrl_soc_info {
struct imx_pmx_func *functions;
unsigned int nfunctions;
unsigned int flags;
const char *gpr_compatible;
};
#define SHARE_MUX_CONF_REG 0x1

1
drivers/pinctrl/freescale/pinctrl-imx50.c
View File

@ -389,6 +389,7 @@ static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.pins = imx50_pinctrl_pads,
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
.gpr_compatible = "fsl,imx50-iomuxc-gpr",
};
static const struct of_device_id imx50_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx53.c
View File

@ -452,6 +452,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.pins = imx53_pinctrl_pads,
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
.gpr_compatible = "fsl,imx53-iomuxc-gpr",
};
static const struct of_device_id imx53_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx6dl.c
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@ -458,6 +458,7 @@ static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.pins = imx6dl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6dl_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx6q.c
View File

@ -464,6 +464,7 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.pins = imx6q_pinctrl_pads,
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
};
static const struct of_device_id imx6q_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx6sl.c
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@ -364,6 +364,7 @@ static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.pins = imx6sl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
.gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
};
static const struct of_device_id imx6sl_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx6sx.c
View File

@ -368,6 +368,7 @@ static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.pins = imx6sx_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
.gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
};
static const struct of_device_id imx6sx_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx6ul.c
View File

@ -284,6 +284,7 @@ static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
.pins = imx6ul_pinctrl_pads,
.npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
.gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
};
static struct of_device_id imx6ul_pinctrl_of_match[] = {

1
drivers/pinctrl/freescale/pinctrl-imx7d.c
View File

@ -359,6 +359,7 @@ static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
.pins = imx7d_pinctrl_pads,
.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
};
static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {

4
drivers/pinctrl/intel/pinctrl-intel.c
View File

@ -11,13 +11,9 @@
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/acpi.h>
#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>

22
drivers/pinctrl/mediatek/Kconfig
View File

@ -1,6 +1,6 @@
if ARCH_MEDIATEK || COMPILE_TEST
config PINCTRL_MTK_COMMON
config PINCTRL_MTK
bool
depends on OF
select PINMUX
@ -9,17 +9,29 @@ config PINCTRL_MTK_COMMON
select OF_GPIO
# For ARMv7 SoCs
config PINCTRL_MT2701
bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
depends on OF
default MACH_MT2701
select PINCTRL_MTK
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control" if COMPILE_TEST && !MACH_MT7623
depends on OF
default MACH_MT7623
select PINCTRL_MTK_COMMON
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
depends on OF
default MACH_MT8135
select PINCTRL_MTK_COMMON
select PINCTRL_MTK
config PINCTRL_MT8127
bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
depends on OF
default MACH_MT8127
select PINCTRL_MTK_COMMON
select PINCTRL_MTK
# For ARMv8 SoCs
config PINCTRL_MT8173
@ -27,13 +39,13 @@ config PINCTRL_MT8173
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_COMMON
select PINCTRL_MTK
# For PMIC
config PINCTRL_MT6397
bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
depends on OF
default MFD_MT6397
select PINCTRL_MTK_COMMON
select PINCTRL_MTK
endif

12
drivers/pinctrl/mediatek/Makefile
View File

@ -1,8 +1,10 @@
# Core
obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
obj-y += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o

585
drivers/pinctrl/mediatek/pinctrl-mt2701.c Normal file
View File

@ -0,0 +1,585 @@
/*
* Copyright (c) 2015 MediaTek Inc.
* Author: Biao Huang <biao.huang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt2701.h"
/**
* struct mtk_spec_pinmux_set
* - For special pins' mode setting
* @pin: The pin number.
* @offset: The offset of extra setting register.
* @bit: The bit of extra setting register.
*/
struct mtk_spec_pinmux_set {
unsigned short pin;
unsigned short offset;
unsigned char bit;
};
#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
{ \
.pin = _pin, \
.offset = _offset, \
.bit = _bit, \
}
static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
};
static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
};
static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
};
static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
};
static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
ARRAY_SIZE(mt2701_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
ARRAY_SIZE(mt2701_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
MTK_PINMUX_SPEC(22, 0xb10, 3),
MTK_PINMUX_SPEC(23, 0xb10, 4),
MTK_PINMUX_SPEC(24, 0xb10, 5),
MTK_PINMUX_SPEC(29, 0xb10, 9),
MTK_PINMUX_SPEC(208, 0xb10, 7),
MTK_PINMUX_SPEC(209, 0xb10, 8),
MTK_PINMUX_SPEC(203, 0xf20, 0),
MTK_PINMUX_SPEC(204, 0xf20, 1),
MTK_PINMUX_SPEC(249, 0xef0, 0),
MTK_PINMUX_SPEC(250, 0xef0, 0),
MTK_PINMUX_SPEC(251, 0xef0, 0),
MTK_PINMUX_SPEC(252, 0xef0, 0),
MTK_PINMUX_SPEC(253, 0xef0, 0),
MTK_PINMUX_SPEC(254, 0xef0, 0),
MTK_PINMUX_SPEC(255, 0xef0, 0),
MTK_PINMUX_SPEC(256, 0xef0, 0),
MTK_PINMUX_SPEC(257, 0xef0, 0),
MTK_PINMUX_SPEC(258, 0xef0, 0),
MTK_PINMUX_SPEC(259, 0xef0, 0),
MTK_PINMUX_SPEC(260, 0xef0, 0),
};
static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
unsigned int mode)
{
unsigned int i, value, mask;
unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
unsigned int spec_flag;
for (i = 0; i < info_num; i++) {
if (pin == mt2701_spec_pinmux[i].pin)
break;
}
if (i == info_num)
return;
spec_flag = (mode >> 3);
mask = BIT(mt2701_spec_pinmux[i].bit);
if (!spec_flag)
value = mask;
else
value = 0;
regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
}
static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
{
if (pin > 175)
*reg_addr += 0x10;
}
static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
.pins = mtk_pins_mt2701,
.npins = ARRAY_SIZE(mtk_pins_mt2701),
.grp_desc = mt2701_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
.pin_drv_grp = mt2701_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
.spec_pull_set = mt2701_spec_pull_set,
.spec_ies_smt_set = mt2701_ies_smt_set,
.spec_pinmux_set = mt2701_spec_pinmux_set,
.spec_dir_set = mt2701_spec_dir_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0150,
.pullsel_offset = 0x0280,
.dout_offset = 0x0500,
.din_offset = 0x0630,
.pinmux_offset = 0x0760,
.type1_start = 280,
.type1_end = 280,
.port_shf = 4,
.port_mask = 0x1f,
.port_align = 4,
.eint_offsets = {
.name = "mt2701_eint",
.stat = 0x000,
.ack = 0x040,
.mask = 0x080,
.mask_set = 0x0c0,
.mask_clr = 0x100,
.sens = 0x140,
.sens_set = 0x180,
.sens_clr = 0x1c0,
.soft = 0x200,
.soft_set = 0x240,
.soft_clr = 0x280,
.pol = 0x300,
.pol_set = 0x340,
.pol_clr = 0x380,
.dom_en = 0x400,
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
.port_mask = 6,
.ports = 6,
},
.ap_num = 169,
.db_cnt = 16,
};
static int mt2701_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
}
static const struct of_device_id mt2701_pctrl_match[] = {
{ .compatible = "mediatek,mt2701-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt2701_pinctrl_probe,
.driver = {
.name = "mediatek-mt2701-pinctrl",
.of_match_table = mt2701_pctrl_match,
.pm = &mtk_eint_pm_ops,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

10
drivers/pinctrl/mediatek/pinctrl-mt6397.c
View File

@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -55,7 +55,6 @@ static const struct of_device_id mt6397_pctrl_match[] = {
{ .compatible = "mediatek,mt6397-pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, mt6397_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt6397_pinctrl_probe,
@ -69,9 +68,4 @@ static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
module_init(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver");
MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
device_initcall(mtk_pinctrl_init);

379
drivers/pinctrl/mediatek/pinctrl-mt7623.c Normal file
View File

@ -0,0 +1,379 @@
/*
* Copyright (c) 2016 John Crispin <blogic@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/pinctrl/mt65xx.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include "pinctrl-mtk-common.h"
#include "pinctrl-mtk-mt7623.h"
static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
/* 0E4E8SR 4/8/12/16 */
MTK_DRV_GRP(4, 16, 1, 2, 4),
/* 0E2E4SR 2/4/6/8 */
MTK_DRV_GRP(2, 8, 1, 2, 2),
/* E8E4E2 2/4/6/8/10/12/14/16 */
MTK_DRV_GRP(2, 16, 0, 2, 2)
};
#define DRV_SEL0 0xf50
#define DRV_SEL1 0xf60
#define DRV_SEL2 0xf70
#define DRV_SEL3 0xf80
#define DRV_SEL4 0xf90
#define DRV_SEL5 0xfa0
#define DRV_SEL6 0xfb0
#define DRV_SEL7 0xfe0
#define DRV_SEL8 0xfd0
#define DRV_SEL9 0xff0
#define DRV_SEL10 0xf00
#define MSDC0_CTRL0 0xcc0
#define MSDC0_CTRL1 0xcd0
#define MSDC0_CTRL2 0xce0
#define MSDC0_CTRL3 0xcf0
#define MSDC0_CTRL4 0xd00
#define MSDC0_CTRL5 0xd10
#define MSDC0_CTRL6 0xd20
#define MSDC1_CTRL0 0xd30
#define MSDC1_CTRL1 0xd40
#define MSDC1_CTRL2 0xd50
#define MSDC1_CTRL3 0xd60
#define MSDC1_CTRL4 0xd70
#define MSDC1_CTRL5 0xd80
#define MSDC1_CTRL6 0xd90
#define IES_EN0 0xb20
#define IES_EN1 0xb30
#define IES_EN2 0xb40
#define SMT_EN0 0xb50
#define SMT_EN1 0xb60
#define SMT_EN2 0xb70
static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
};
static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
};
static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
unsigned char align, bool isup, unsigned int r1r0)
{
return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
}
static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
};
static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
};
static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg)
{
if (arg == PIN_CONFIG_INPUT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
ARRAY_SIZE(mt7623_ies_set), pin, align, value);
else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
ARRAY_SIZE(mt7623_smt_set), pin, align, value);
return -EINVAL;
}
static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
.pins = mtk_pins_mt7623,
.npins = ARRAY_SIZE(mtk_pins_mt7623),
.grp_desc = mt7623_drv_grp,
.n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
.pin_drv_grp = mt7623_pin_drv,
.n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
.spec_pull_set = mt7623_spec_pull_set,
.spec_ies_smt_set = mt7623_ies_smt_set,
.dir_offset = 0x0000,
.pullen_offset = 0x0150,
.pullsel_offset = 0x0280,
.dout_offset = 0x0500,
.din_offset = 0x0630,
.pinmux_offset = 0x0760,
.type1_start = 280,
.type1_end = 280,
.port_shf = 4,
.port_mask = 0x1f,
.port_align = 4,
.eint_offsets = {
.name = "mt7623_eint",
.stat = 0x000,
.ack = 0x040,
.mask = 0x080,
.mask_set = 0x0c0,
.mask_clr = 0x100,
.sens = 0x140,
.sens_set = 0x180,
.sens_clr = 0x1c0,
.soft = 0x200,
.soft_set = 0x240,
.soft_clr = 0x280,
.pol = 0x300,
.pol_set = 0x340,
.pol_clr = 0x380,
.dom_en = 0x400,
.dbnc_ctrl = 0x500,
.dbnc_set = 0x600,
.dbnc_clr = 0x700,
.port_mask = 6,
.ports = 6,
},
.ap_num = 169,
.db_cnt = 16,
};
static int mt7623_pinctrl_probe(struct platform_device *pdev)
{
return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
}
static const struct of_device_id mt7623_pctrl_match[] = {
{ .compatible = "mediatek,mt7623-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt7623_pinctrl_probe,
.driver = {
.name = "mediatek-mt7623-pinctrl",
.of_match_table = mt7623_pctrl_match,
},
};
static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);

8
drivers/pinctrl/mediatek/pinctrl-mt8127.c
View File

@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -336,7 +336,6 @@ static const struct of_device_id mt8127_pctrl_match[] = {
{ .compatible = "mediatek,mt8127-pinctrl", },
{ }
};
MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8127_pinctrl_probe,
@ -350,9 +349,4 @@ static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");

8
drivers/pinctrl/mediatek/pinctrl-mt8135.c
View File

@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -351,7 +351,6 @@ static const struct of_device_id mt8135_pctrl_match[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8135_pinctrl_probe,
@ -365,9 +364,4 @@ static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");

8
drivers/pinctrl/mediatek/pinctrl-mt8173.c
View File

@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -378,7 +378,6 @@ static const struct of_device_id mt8173_pctrl_match[] = {
},
{ }
};
MODULE_DEVICE_TABLE(of, mt8173_pctrl_match);
static struct platform_driver mtk_pinctrl_driver = {
.probe = mt8173_pinctrl_probe,
@ -393,9 +392,4 @@ static int __init mtk_pinctrl_init(void)
{
return platform_driver_register(&mtk_pinctrl_driver);
}
arch_initcall(mtk_pinctrl_init);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");

55
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -43,10 +43,13 @@
#define MAX_GPIO_MODE_PER_REG 5
#define GPIO_MODE_BITS 3
#define GPIO_MODE_PREFIX "GPIO"
static const char * const mtk_gpio_functions[] = {
"func0", "func1", "func2", "func3",
"func4", "func5", "func6", "func7",
"func8", "func9", "func10", "func11",
"func12", "func13", "func14", "func15",
};
/*
@ -81,6 +84,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(&reg_addr, offset);
if (input)
/* Different SoC has different alignment offset. */
reg_addr = CLR_ADDR(reg_addr, pctl);
@ -677,9 +683,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
if (pctl->devdata->spec_pinmux_set)
pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
pin, mode);
reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
+ pctl->devdata->pinmux_offset;
mode &= mask;
bit = pin % MAX_GPIO_MODE_PER_REG;
mask <<= (GPIO_MODE_BITS * bit);
val = (mode << (GPIO_MODE_BITS * bit));
@ -725,12 +736,48 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
return 0;
}
static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
unsigned offset)
{
const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
const struct mtk_desc_function *func = pin->functions;
while (func && func->name) {
if (!strncmp(func->name, GPIO_MODE_PREFIX,
sizeof(GPIO_MODE_PREFIX)-1))
return func->muxval;
func++;
}
return -EINVAL;
}
static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset)
{
int muxval;
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
muxval = mtk_pmx_find_gpio_mode(pctl, offset);
if (muxval < 0) {
dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
return -EINVAL;
}
mtk_pmx_set_mode(pctldev, offset, muxval);
mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
return 0;
}
static const struct pinmux_ops mtk_pmx_ops = {
.get_functions_count = mtk_pmx_get_funcs_cnt,
.get_function_name = mtk_pmx_get_func_name,
.get_function_groups = mtk_pmx_get_func_groups,
.set_mux = mtk_pmx_set_mux,
.gpio_set_direction = mtk_pmx_gpio_set_direction,
.gpio_request_enable = mtk_pmx_gpio_request_enable,
};
static int mtk_gpio_direction_input(struct gpio_chip *chip,
@ -756,6 +803,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(&reg_addr, offset);
regmap_read(pctl->regmap1, reg_addr, &read_val);
return !(read_val & bit);
}
@ -814,6 +865,10 @@ static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
/* set mux to INT mode */
mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
/* set gpio direction to input */
mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
/* set input-enable */
mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
return 0;
}

12
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
View File

@ -209,7 +209,14 @@ struct mtk_eint_offsets {
* means when user set smt, input enable is set at the same time. So they
* also need special control. If special control is success, this should
* return 0, otherwise return non-zero value.
*
* @spec_pinmux_set: In some cases, there are two pinmux functions share
* the same value in the same segment of pinmux control register. If user
* want to use one of the two functions, they need an extra bit setting to
* select the right one.
* @spec_dir_set: In very few SoCs, direction control registers are not
* arranged continuously, they may be cut to parts. So they need special
* dir setting.
* @dir_offset: The direction register offset.
* @pullen_offset: The pull-up/pull-down enable register offset.
* @pinmux_offset: The pinmux register offset.
@ -234,6 +241,9 @@ struct mtk_pinctrl_devdata {
unsigned char align, bool isup, unsigned int arg);
int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
unsigned char align, int value, enum pin_config_param arg);
void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
unsigned int mode);
void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
unsigned int dir_offset;
unsigned int ies_offset;
unsigned int smt_offset;

2323
drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h Normal file
View File

File diff suppressed because it is too large Load Diff

1936
drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h Normal file
View File

File diff suppressed because it is too large Load Diff

139
drivers/pinctrl/meson/pinctrl-meson.c
View File

@ -49,7 +49,6 @@
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/pinconf-generic.h>
@ -104,15 +103,13 @@ static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
struct meson_bank **bank)
{
struct meson_domain *d;
int i;
for (i = 0; i < pc->data->num_domains; i++) {
d = &pc->domains[i];
if (pin >= d->data->pin_base &&
pin < d->data->pin_base + d->data->num_pins) {
*domain = d;
return meson_get_bank(d, pin, bank);
}
d = pc->domain;
if (pin >= d->data->pin_base &&
pin < d->data->pin_base + d->data->num_pins) {
*domain = d;
return meson_get_bank(d, pin, bank);
}
return -EINVAL;
@ -204,7 +201,7 @@ static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
for (j = 0; j < group->num_pins; j++) {
if (group->pins[j] == pin) {
/* We have found a group using the pin */
domain = &pc->domains[group->domain];
domain = pc->domain;
regmap_update_bits(domain->reg_mux,
group->reg * 4,
BIT(group->bit), 0);
@ -219,7 +216,7 @@ static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
struct meson_pmx_func *func = &pc->data->funcs[func_num];
struct meson_pmx_group *group = &pc->data->groups[group_num];
struct meson_domain *domain = &pc->domains[group->domain];
struct meson_domain *domain = pc->domain;
int i, ret = 0;
dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
@ -537,76 +534,67 @@ static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
static const struct of_device_id meson_pinctrl_dt_match[] = {
{
.compatible = "amlogic,meson8-pinctrl",
.data = &meson8_pinctrl_data,
.compatible = "amlogic,meson8-cbus-pinctrl",
.data = &meson8_cbus_pinctrl_data,
},
{
.compatible = "amlogic,meson8b-pinctrl",
.data = &meson8b_pinctrl_data,
.compatible = "amlogic,meson8b-cbus-pinctrl",
.data = &meson8b_cbus_pinctrl_data,
},
{
.compatible = "amlogic,meson8-aobus-pinctrl",
.data = &meson8_aobus_pinctrl_data,
},
{
.compatible = "amlogic,meson8b-aobus-pinctrl",
.data = &meson8b_aobus_pinctrl_data,
},
{ },
};
MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
static int meson_gpiolib_register(struct meson_pinctrl *pc)
{
struct meson_domain *domain;
int i, ret;
int ret;
for (i = 0; i < pc->data->num_domains; i++) {
domain = &pc->domains[i];
domain = pc->domain;
domain->chip.label = domain->data->name;
domain->chip.parent = pc->dev;
domain->chip.request = meson_gpio_request;
domain->chip.free = meson_gpio_free;
domain->chip.direction_input = meson_gpio_direction_input;
domain->chip.direction_output = meson_gpio_direction_output;
domain->chip.get = meson_gpio_get;
domain->chip.set = meson_gpio_set;
domain->chip.base = domain->data->pin_base;
domain->chip.ngpio = domain->data->num_pins;
domain->chip.can_sleep = false;
domain->chip.of_node = domain->of_node;
domain->chip.of_gpio_n_cells = 2;
domain->chip.label = domain->data->name;
domain->chip.parent = pc->dev;
domain->chip.request = meson_gpio_request;
domain->chip.free = meson_gpio_free;
domain->chip.direction_input = meson_gpio_direction_input;
domain->chip.direction_output = meson_gpio_direction_output;
domain->chip.get = meson_gpio_get;
domain->chip.set = meson_gpio_set;
domain->chip.base = domain->data->pin_base;
domain->chip.ngpio = domain->data->num_pins;
domain->chip.can_sleep = false;
domain->chip.of_node = domain->of_node;
domain->chip.of_gpio_n_cells = 2;
ret = gpiochip_add_data(&domain->chip, domain);
if (ret) {
dev_err(pc->dev, "can't add gpio chip %s\n",
domain->data->name);
goto fail;
}
ret = gpiochip_add_data(&domain->chip, domain);
if (ret) {
dev_err(pc->dev, "can't add gpio chip %s\n",
domain->data->name);
goto fail;
}
ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
0, domain->data->pin_base,
domain->chip.ngpio);
if (ret) {
dev_err(pc->dev, "can't add pin range\n");
goto fail;
}
ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
0, domain->data->pin_base,
domain->chip.ngpio);
if (ret) {
dev_err(pc->dev, "can't add pin range\n");
goto fail;
}
return 0;
fail:
for (i--; i >= 0; i--)
gpiochip_remove(&pc->domains[i].chip);
gpiochip_remove(&pc->domain->chip);
return ret;
}
static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
struct device_node *np)
{
int i;
for (i = 0; i < pc->data->num_domains; i++) {
if (!strcmp(np->name, pc->data->domain_data[i].name))
return &pc->data->domain_data[i];
}
return NULL;
}
static struct regmap_config meson_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@ -643,7 +631,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
{
struct device_node *np;
struct meson_domain *domain;
int i = 0, num_domains = 0;
int num_domains = 0;
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
@ -651,29 +639,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
num_domains++;
}
if (num_domains != pc->data->num_domains) {
if (num_domains != 1) {
dev_err(pc->dev, "wrong number of subnodes\n");
return -EINVAL;
}
pc->domains = devm_kzalloc(pc->dev, num_domains *
sizeof(struct meson_domain), GFP_KERNEL);
if (!pc->domains)
pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL);
if (!pc->domain)
return -ENOMEM;
domain = pc->domain;
domain->data = pc->data->domain_data;
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
continue;
domain = &pc->domains[i];
domain->data = meson_get_domain_data(pc, np);
if (!domain->data) {
dev_err(pc->dev, "domain data not found for node %s\n",
np->name);
return -ENODEV;
}
domain->of_node = np;
domain->reg_mux = meson_map_resource(pc, np, "mux");
@ -699,7 +680,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
return PTR_ERR(domain->reg_gpio);
}
i++;
break;
}
return 0;
@ -718,7 +699,7 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
pc->dev = dev;
match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
pc->data = (struct meson_pinctrl_data *)match->data;
pc->data = (struct meson_pinctrl_data *) match->data;
ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
if (ret)
@ -754,8 +735,4 @@ static struct platform_driver meson_pinctrl_driver = {
.of_match_table = meson_pinctrl_dt_match,
},
};
module_platform_driver(meson_pinctrl_driver);
MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
MODULE_LICENSE("GPL v2");
builtin_platform_driver(meson_pinctrl_driver);

21
drivers/pinctrl/meson/pinctrl-meson.h
View File

@ -34,7 +34,6 @@ struct meson_pmx_group {
bool is_gpio;
unsigned int reg;
unsigned int bit;
unsigned int domain;
};
/**
@ -144,7 +143,6 @@ struct meson_pinctrl_data {
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
unsigned int num_domains;
};
struct meson_pinctrl {
@ -152,7 +150,7 @@ struct meson_pinctrl {
struct pinctrl_dev *pcdev;
struct pinctrl_desc desc;
struct meson_pinctrl_data *data;
struct meson_domain *domains;
struct meson_domain *domain;
};
#define PIN(x, b) (b + x)
@ -164,7 +162,6 @@ struct meson_pinctrl {
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
.domain = 0, \
}
#define GPIO_GROUP(gpio, b) \
@ -175,16 +172,6 @@ struct meson_pinctrl {
.is_gpio = true, \
}
#define GROUP_AO(grp, r, b) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
.domain = 1, \
}
#define FUNCTION(fn) \
{ \
.name = #fn, \
@ -208,5 +195,7 @@ struct meson_pinctrl {
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
extern struct meson_pinctrl_data meson8_pinctrl_data;
extern struct meson_pinctrl_data meson8b_pinctrl_data;
extern struct meson_pinctrl_data meson8_cbus_pinctrl_data;
extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;
extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;

133
drivers/pinctrl/meson/pinctrl-meson8.c
View File

@ -16,7 +16,7 @@
#define AO_OFF 120
static const struct pinctrl_pin_desc meson8_pins[] = {
static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
MESON_PIN(GPIOX_0, 0),
MESON_PIN(GPIOX_1, 0),
MESON_PIN(GPIOX_2, 0),
@ -137,6 +137,9 @@ static const struct pinctrl_pin_desc meson8_pins[] = {
MESON_PIN(BOOT_16, 0),
MESON_PIN(BOOT_17, 0),
MESON_PIN(BOOT_18, 0),
};
static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
MESON_PIN(GPIOAO_0, AO_OFF),
MESON_PIN(GPIOAO_1, AO_OFF),
MESON_PIN(GPIOAO_2, AO_OFF),
@ -379,7 +382,7 @@ static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
static struct meson_pmx_group meson8_groups[] = {
static struct meson_pmx_group meson8_cbus_groups[] = {
GPIO_GROUP(GPIOX_0, 0),
GPIO_GROUP(GPIOX_1, 0),
GPIO_GROUP(GPIOX_2, 0),
@ -474,22 +477,6 @@ static struct meson_pmx_group meson8_groups[] = {
GPIO_GROUP(GPIOZ_12, 0),
GPIO_GROUP(GPIOZ_13, 0),
GPIO_GROUP(GPIOZ_14, 0),
GPIO_GROUP(GPIOAO_0, AO_OFF),
GPIO_GROUP(GPIOAO_1, AO_OFF),
GPIO_GROUP(GPIOAO_2, AO_OFF),
GPIO_GROUP(GPIOAO_3, AO_OFF),
GPIO_GROUP(GPIOAO_4, AO_OFF),
GPIO_GROUP(GPIOAO_5, AO_OFF),
GPIO_GROUP(GPIOAO_6, AO_OFF),
GPIO_GROUP(GPIOAO_7, AO_OFF),
GPIO_GROUP(GPIOAO_8, AO_OFF),
GPIO_GROUP(GPIOAO_9, AO_OFF),
GPIO_GROUP(GPIOAO_10, AO_OFF),
GPIO_GROUP(GPIOAO_11, AO_OFF),
GPIO_GROUP(GPIOAO_12, AO_OFF),
GPIO_GROUP(GPIOAO_13, AO_OFF),
GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank X */
GROUP(sd_d0_a, 8, 5),
@ -675,26 +662,45 @@ static struct meson_pmx_group meson8_groups[] = {
GROUP(sdxc_d0_b, 2, 7),
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
};
static struct meson_pmx_group meson8_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0, AO_OFF),
GPIO_GROUP(GPIOAO_1, AO_OFF),
GPIO_GROUP(GPIOAO_2, AO_OFF),
GPIO_GROUP(GPIOAO_3, AO_OFF),
GPIO_GROUP(GPIOAO_4, AO_OFF),
GPIO_GROUP(GPIOAO_5, AO_OFF),
GPIO_GROUP(GPIOAO_6, AO_OFF),
GPIO_GROUP(GPIOAO_7, AO_OFF),
GPIO_GROUP(GPIOAO_8, AO_OFF),
GPIO_GROUP(GPIOAO_9, AO_OFF),
GPIO_GROUP(GPIOAO_10, AO_OFF),
GPIO_GROUP(GPIOAO_11, AO_OFF),
GPIO_GROUP(GPIOAO_12, AO_OFF),
GPIO_GROUP(GPIOAO_13, AO_OFF),
GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank AO */
GROUP_AO(uart_tx_ao_a, 0, 12),
GROUP_AO(uart_rx_ao_a, 0, 11),
GROUP_AO(uart_cts_ao_a, 0, 10),
GROUP_AO(uart_rts_ao_a, 0, 9),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
GROUP_AO(remote_input, 0, 0),
GROUP(remote_input, 0, 0),
GROUP_AO(i2c_slave_sck_ao, 0, 2),
GROUP_AO(i2c_slave_sda_ao, 0, 1),
GROUP(i2c_slave_sck_ao, 0, 2),
GROUP(i2c_slave_sda_ao, 0, 1),
GROUP_AO(uart_tx_ao_b0, 0, 26),
GROUP_AO(uart_rx_ao_b0, 0, 25),
GROUP(uart_tx_ao_b0, 0, 26),
GROUP(uart_rx_ao_b0, 0, 25),
GROUP_AO(uart_tx_ao_b1, 0, 24),
GROUP_AO(uart_rx_ao_b1, 0, 23),
GROUP(uart_tx_ao_b1, 0, 24),
GROUP(uart_rx_ao_b1, 0, 23),
GROUP_AO(i2c_mst_sck_ao, 0, 6),
GROUP_AO(i2c_mst_sda_ao, 0, 5),
GROUP(i2c_mst_sck_ao, 0, 6),
GROUP(i2c_mst_sda_ao, 0, 5),
};
static const char * const gpio_groups[] = {
@ -872,7 +878,7 @@ static const char * const i2c_mst_ao_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
static struct meson_pmx_func meson8_functions[] = {
static struct meson_pmx_func meson8_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
@ -899,6 +905,9 @@ static struct meson_pmx_func meson8_functions[] = {
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
};
static struct meson_pmx_func meson8_aobus_functions[] = {
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),
@ -906,7 +915,7 @@ static struct meson_pmx_func meson8_functions[] = {
FUNCTION(i2c_mst_ao),
};
static struct meson_bank meson8_banks[] = {
static struct meson_bank meson8_cbus_banks[] = {
/* name first last pullen pull dir out in */
BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
@ -917,35 +926,43 @@ static struct meson_bank meson8_banks[] = {
BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
};
static struct meson_bank meson8_ao_banks[] = {
static struct meson_bank meson8_aobus_banks[] = {
/* name first last pullen pull dir out in */
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
};
static struct meson_domain_data meson8_domain_data[] = {
{
.name = "banks",
.banks = meson8_banks,
.num_banks = ARRAY_SIZE(meson8_banks),
.pin_base = 0,
.num_pins = 120,
},
{
.name = "ao-bank",
.banks = meson8_ao_banks,
.num_banks = ARRAY_SIZE(meson8_ao_banks),
.pin_base = 120,
.num_pins = 16,
},
static struct meson_domain_data meson8_cbus_domain_data = {
.name = "cbus-banks",
.banks = meson8_cbus_banks,
.num_banks = ARRAY_SIZE(meson8_cbus_banks),
.pin_base = 0,
.num_pins = 120,
};
struct meson_pinctrl_data meson8_pinctrl_data = {
.pins = meson8_pins,
.groups = meson8_groups,
.funcs = meson8_functions,
.domain_data = meson8_domain_data,
.num_pins = ARRAY_SIZE(meson8_pins),
.num_groups = ARRAY_SIZE(meson8_groups),
.num_funcs = ARRAY_SIZE(meson8_functions),
.num_domains = ARRAY_SIZE(meson8_domain_data),
static struct meson_domain_data meson8_aobus_domain_data = {
.name = "ao-bank",
.banks = meson8_aobus_banks,
.num_banks = ARRAY_SIZE(meson8_aobus_banks),
.pin_base = 120,
.num_pins = 16,
};
struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
.pins = meson8_cbus_pins,
.groups = meson8_cbus_groups,
.funcs = meson8_cbus_functions,
.domain_data = &meson8_cbus_domain_data,
.num_pins = ARRAY_SIZE(meson8_cbus_pins),
.num_groups = ARRAY_SIZE(meson8_cbus_groups),
.num_funcs = ARRAY_SIZE(meson8_cbus_functions),
};
struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
.pins = meson8_aobus_pins,
.groups = meson8_aobus_groups,
.funcs = meson8_aobus_functions,
.domain_data = &meson8_aobus_domain_data,
.num_pins = ARRAY_SIZE(meson8_aobus_pins),
.num_groups = ARRAY_SIZE(meson8_aobus_groups),
.num_funcs = ARRAY_SIZE(meson8_aobus_functions),
};

178
drivers/pinctrl/meson/pinctrl-meson8b.c
View File

@ -17,7 +17,7 @@
#define AO_OFF 130
static const struct pinctrl_pin_desc meson8b_pins[] = {
static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
MESON_PIN(GPIOX_0, 0),
MESON_PIN(GPIOX_1, 0),
MESON_PIN(GPIOX_2, 0),
@ -107,7 +107,9 @@ static const struct pinctrl_pin_desc meson8b_pins[] = {
MESON_PIN(DIF_3_N, 0),
MESON_PIN(DIF_4_P, 0),
MESON_PIN(DIF_4_N, 0),
};
static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
MESON_PIN(GPIOAO_0, AO_OFF),
MESON_PIN(GPIOAO_1, AO_OFF),
MESON_PIN(GPIOAO_2, AO_OFF),
@ -346,7 +348,7 @@ static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) };
static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) };
static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) };
static struct meson_pmx_group meson8b_groups[] = {
static struct meson_pmx_group meson8b_cbus_groups[] = {
GPIO_GROUP(GPIOX_0, 0),
GPIO_GROUP(GPIOX_1, 0),
GPIO_GROUP(GPIOX_2, 0),
@ -409,23 +411,6 @@ static struct meson_pmx_group meson8b_groups[] = {
GPIO_GROUP(DIF_4_P, 0),
GPIO_GROUP(DIF_4_N, 0),
GPIO_GROUP(GPIOAO_0, AO_OFF),
GPIO_GROUP(GPIOAO_1, AO_OFF),
GPIO_GROUP(GPIOAO_2, AO_OFF),
GPIO_GROUP(GPIOAO_3, AO_OFF),
GPIO_GROUP(GPIOAO_4, AO_OFF),
GPIO_GROUP(GPIOAO_5, AO_OFF),
GPIO_GROUP(GPIOAO_6, AO_OFF),
GPIO_GROUP(GPIOAO_7, AO_OFF),
GPIO_GROUP(GPIOAO_8, AO_OFF),
GPIO_GROUP(GPIOAO_9, AO_OFF),
GPIO_GROUP(GPIOAO_10, AO_OFF),
GPIO_GROUP(GPIOAO_11, AO_OFF),
GPIO_GROUP(GPIOAO_12, AO_OFF),
GPIO_GROUP(GPIOAO_13, AO_OFF),
GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank X */
GROUP(sd_d0_a, 8, 5),
GROUP(sd_d1_a, 8, 4),
@ -572,6 +557,37 @@ static struct meson_pmx_group meson8b_groups[] = {
GROUP(sdxc_clk_b, 2, 5),
GROUP(sdxc_cmd_b, 2, 4),
/* bank DIF */
GROUP(eth_rxd1, 6, 0),
GROUP(eth_rxd0, 6, 1),
GROUP(eth_rx_dv, 6, 2),
GROUP(eth_rx_clk, 6, 3),
GROUP(eth_txd0_1, 6, 4),
GROUP(eth_txd1_1, 6, 5),
GROUP(eth_tx_en, 6, 0),
GROUP(eth_ref_clk, 6, 8),
GROUP(eth_mdc, 6, 9),
GROUP(eth_mdio_en, 6, 10),
};
static struct meson_pmx_group meson8b_aobus_groups[] = {
GPIO_GROUP(GPIOAO_0, AO_OFF),
GPIO_GROUP(GPIOAO_1, AO_OFF),
GPIO_GROUP(GPIOAO_2, AO_OFF),
GPIO_GROUP(GPIOAO_3, AO_OFF),
GPIO_GROUP(GPIOAO_4, AO_OFF),
GPIO_GROUP(GPIOAO_5, AO_OFF),
GPIO_GROUP(GPIOAO_6, AO_OFF),
GPIO_GROUP(GPIOAO_7, AO_OFF),
GPIO_GROUP(GPIOAO_8, AO_OFF),
GPIO_GROUP(GPIOAO_9, AO_OFF),
GPIO_GROUP(GPIOAO_10, AO_OFF),
GPIO_GROUP(GPIOAO_11, AO_OFF),
GPIO_GROUP(GPIOAO_12, AO_OFF),
GPIO_GROUP(GPIOAO_13, AO_OFF),
GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank AO */
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
@ -601,18 +617,6 @@ static struct meson_pmx_group meson8b_groups[] = {
GROUP(i2s_in_ch01, 0, 13),
GROUP(i2s_ao_clk_in, 0, 15),
GROUP(i2s_lr_clk_in, 0, 14),
/* bank DIF */
GROUP(eth_rxd1, 6, 0),
GROUP(eth_rxd0, 6, 1),
GROUP(eth_rx_dv, 6, 2),
GROUP(eth_rx_clk, 6, 3),
GROUP(eth_txd0_1, 6, 4),
GROUP(eth_txd1_1, 6, 5),
GROUP(eth_tx_en, 6, 0),
GROUP(eth_ref_clk, 6, 8),
GROUP(eth_mdc, 6, 9),
GROUP(eth_mdio_en, 6, 10),
};
static const char * const gpio_groups[] = {
@ -694,7 +698,10 @@ static const char * const i2c_c_groups[] = {
};
static const char * const hdmi_groups[] = {
"hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0",
"hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
};
static const char * const hdmi_cec_groups[] = {
"hdmi_cec_1"
};
@ -770,12 +777,20 @@ static const char * const i2c_mst_ao_groups[] = {
"i2c_mst_sck_ao", "i2c_mst_sda_ao"
};
static const char * const clk_groups[] = {
"clk_24m_out", "clk_32k_in_out"
static const char * const clk_24m_groups[] = {
"clk_24m_out"
};
static const char * const spdif_groups[] = {
"spdif_out_1", "spdif_out_0"
static const char * const clk_32k_groups[] = {
"clk_32k_in_out"
};
static const char * const spdif_0_groups[] = {
"spdif_out_0"
};
static const char * const spdif_1_groups[] = {
"spdif_out_1"
};
static const char * const i2s_groups[] = {
@ -789,7 +804,11 @@ static const char * const pwm_b_groups[] = {
};
static const char * const pwm_c_groups[] = {
"pwm_c0", "pwm_c1", "pwm_c2"
"pwm_c0", "pwm_c1"
};
static const char * const pwm_c_ao_groups[] = {
"pwm_c2"
};
static const char * const pwm_d_groups[] = {
@ -814,7 +833,7 @@ static const char * const tsin_b_groups[] = {
"tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
};
static struct meson_pmx_func meson8b_functions[] = {
static struct meson_pmx_func meson8b_cbus_functions[] = {
FUNCTION(gpio),
FUNCTION(sd_a),
FUNCTION(sdxc_a),
@ -837,14 +856,7 @@ static struct meson_pmx_func meson8b_functions[] = {
FUNCTION(nor),
FUNCTION(sd_b),
FUNCTION(sdxc_b),
FUNCTION(uart_ao),
FUNCTION(remote),
FUNCTION(i2c_slave_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_mst_ao),
FUNCTION(clk),
FUNCTION(spdif),
FUNCTION(i2s),
FUNCTION(spdif_0),
FUNCTION(pwm_b),
FUNCTION(pwm_c),
FUNCTION(pwm_d),
@ -852,9 +864,23 @@ static struct meson_pmx_func meson8b_functions[] = {
FUNCTION(pwm_vs),
FUNCTION(tsin_a),
FUNCTION(tsin_b),
FUNCTION(clk_24m),
};
static struct meson_bank meson8b_banks[] = {
static struct meson_pmx_func meson8b_aobus_functions[] = {
FUNCTION(uart_ao),
FUNCTION(uart_ao_b),
FUNCTION(i2c_slave_ao),
FUNCTION(i2c_mst_ao),
FUNCTION(i2s),
FUNCTION(remote),
FUNCTION(clk_32k),
FUNCTION(pwm_c_ao),
FUNCTION(spdif_1),
FUNCTION(hdmi_cec),
};
static struct meson_bank meson8b_cbus_banks[] = {
/* name first last pullen pull dir out in */
BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
@ -865,35 +891,43 @@ static struct meson_bank meson8b_banks[] = {
BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
};
static struct meson_bank meson8b_ao_banks[] = {
static struct meson_bank meson8b_aobus_banks[] = {
/* name first last pullen pull dir out in */
BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
};
static struct meson_domain_data meson8b_domain_data[] = {
{
.name = "banks",
.banks = meson8b_banks,
.num_banks = ARRAY_SIZE(meson8b_banks),
.pin_base = 0,
.num_pins = 130,
},
{
.name = "ao-bank",
.banks = meson8b_ao_banks,
.num_banks = ARRAY_SIZE(meson8b_ao_banks),
.pin_base = 130,
.num_pins = 16,
},
static struct meson_domain_data meson8b_cbus_domain_data = {
.name = "cbus-banks",
.banks = meson8b_cbus_banks,
.num_banks = ARRAY_SIZE(meson8b_cbus_banks),
.pin_base = 0,
.num_pins = 130,
};
struct meson_pinctrl_data meson8b_pinctrl_data = {
.pins = meson8b_pins,
.groups = meson8b_groups,
.funcs = meson8b_functions,
.domain_data = meson8b_domain_data,
.num_pins = ARRAY_SIZE(meson8b_pins),
.num_groups = ARRAY_SIZE(meson8b_groups),
.num_funcs = ARRAY_SIZE(meson8b_functions),
.num_domains = ARRAY_SIZE(meson8b_domain_data),
static struct meson_domain_data meson8b_aobus_domain_data = {
.name = "aobus-banks",
.banks = meson8b_aobus_banks,
.num_banks = ARRAY_SIZE(meson8b_aobus_banks),
.pin_base = 130,
.num_pins = 16,
};
struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
.pins = meson8b_cbus_pins,
.groups = meson8b_cbus_groups,
.funcs = meson8b_cbus_functions,
.domain_data = &meson8b_cbus_domain_data,
.num_pins = ARRAY_SIZE(meson8b_cbus_pins),
.num_groups = ARRAY_SIZE(meson8b_cbus_groups),
.num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
};
struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
.pins = meson8b_aobus_pins,
.groups = meson8b_aobus_groups,
.funcs = meson8b_aobus_functions,
.domain_data = &meson8b_aobus_domain_data,
.num_pins = ARRAY_SIZE(meson8b_aobus_pins),
.num_groups = ARRAY_SIZE(meson8b_aobus_groups),
.num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
};

7
drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
View File

@ -287,6 +287,10 @@ static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
/* Altfunction B */
static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6,
STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5,
STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 };
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
@ -302,6 +306,7 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
};
/* We use this macro to define the groups applicable to a function */
@ -314,6 +319,7 @@ STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1");
#define FUNCTION(fname) \
{ \
@ -329,6 +335,7 @@ static const struct nmk_function nmk_stn8815_functions[] = {
FUNCTION(i2c1),
FUNCTION(i2c0),
FUNCTION(i2cusb),
FUNCTION(clcd),
};
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {

4
drivers/pinctrl/pinctrl-amd.c
View File

@ -753,8 +753,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (IS_ERR(gpio_dev->base))
return PTR_ERR(gpio_dev->base);
if (!gpio_dev->base)
return -ENOMEM;
irq_base = platform_get_irq(pdev, 0);
if (irq_base < 0) {

4
drivers/pinctrl/pinctrl-at91-pio4.c
View File

@ -824,7 +824,7 @@ static struct pinctrl_desc atmel_pinctrl_desc = {
.pmxops = &atmel_pmxops,
};
static int atmel_pctrl_suspend(struct device *dev)
static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
@ -844,7 +844,7 @@ static int atmel_pctrl_suspend(struct device *dev)
return 0;
}
static int atmel_pctrl_resume(struct device *dev)
static int __maybe_unused atmel_pctrl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);

2
drivers/pinctrl/pinctrl-coh901.c
View File

@ -127,7 +127,7 @@ struct u300_gpio_confdata {
}
/* Initial configuration */
static const struct __initconst u300_gpio_confdata
static const struct u300_gpio_confdata __initconst
bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
/* Port 0, pins 0-7 */
{

148
drivers/pinctrl/pinctrl-lpc18xx.c
View File

@ -49,6 +49,18 @@
#define LPC18XX_SCU_FUNC_PER_PIN 8
/* LPC18XX SCU pin interrupt select registers */
#define LPC18XX_SCU_PINTSEL0 0xe00
#define LPC18XX_SCU_PINTSEL1 0xe04
#define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
#define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
#define LPC18XX_SCU_IRQ_PER_PINTSEL 4
#define LPC18XX_GPIO_PINS_PER_PORT 32
#define LPC18XX_GPIO_PIN_INT_MAX 8
#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
/* LPC18xx pin types */
enum {
TYPE_ND, /* Normal-drive */
@ -618,6 +630,25 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = {
LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
};
/**
* enum lpc18xx_pin_config_param - possible pin configuration parameters
* @PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt
* controller.
*/
enum lpc18xx_pin_config_param {
PIN_CONFIG_GPIO_PIN_INT = PIN_CONFIG_END + 1,
};
static const struct pinconf_generic_params lpc18xx_params[] = {
{"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
};
#endif
static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
{
switch (param) {
@ -693,7 +724,71 @@ static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg
return 0;
}
static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
{
struct pinctrl_gpio_range *range;
range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
if (!range)
return -EINVAL;
return pin - range->pin_base + range->base;
}
static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
{
u32 reg_val;
int i;
reg_val = readl(addr);
for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
return 0;
reg_val >>= BITS_PER_BYTE;
*arg += 1;
}
return -EINVAL;
}
static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
{
unsigned int gpio_port, gpio_pin;
gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
}
static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
int *arg, unsigned pin)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
int gpio, ret;
u32 val;
gpio = lpc18xx_pin_to_gpio(pctldev, pin);
if (gpio < 0)
return -ENOTSUPP;
val = lpc18xx_gpio_to_pintsel_val(gpio);
/*
* Check if this pin has been enabled as a interrupt in any of the two
* PINTSEL registers. *arg indicates which interrupt number (0-7).
*/
*arg = 0;
ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
if (ret == 0)
return ret;
return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
}
static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
int *arg, u32 reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
@ -755,6 +850,9 @@ static int lpc18xx_pconf_get_pin(enum pin_config_param param, int *arg, u32 reg,
}
break;
case PIN_CONFIG_GPIO_PIN_INT:
return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
default:
return -ENOTSUPP;
}
@ -794,7 +892,7 @@ static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
else
ret = lpc18xx_pconf_get_pin(param, &arg, reg, pin_cap);
ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
if (ret < 0)
return ret;
@ -883,9 +981,34 @@ static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
return 0;
}
static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
enum pin_config_param param,
u16 param_val, u32 *reg,
static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
u16 param_val, unsigned pin)
{
struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
int gpio;
if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
return -EINVAL;
gpio = lpc18xx_pin_to_gpio(pctldev, pin);
if (gpio < 0)
return -ENOTSUPP;
val = lpc18xx_gpio_to_pintsel_val(gpio);
reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
reg_val = readl(scu->base + reg_offset);
reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
writel(reg_val, scu->base + reg_offset);
return 0;
}
static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
u16 param_val, u32 *reg, unsigned pin,
struct lpc18xx_pin_caps *pin_cap)
{
switch (param) {
@ -948,6 +1071,9 @@ static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev,
*reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
break;
case PIN_CONFIG_GPIO_PIN_INT:
return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
default:
dev_err(pctldev->dev, "Property not supported\n");
return -ENOTSUPP;
@ -982,7 +1108,7 @@ static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
else if (pin_cap->type == TYPE_USB1)
ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
else
ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin_cap);
ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin, pin_cap);
if (ret)
return ret;
@ -1136,6 +1262,11 @@ static struct pinctrl_desc lpc18xx_scu_desc = {
.pctlops = &lpc18xx_pctl_ops,
.pmxops = &lpc18xx_pmx_ops,
.confops = &lpc18xx_pconf_ops,
.num_custom_params = ARRAY_SIZE(lpc18xx_params),
.custom_params = lpc18xx_params,
#ifdef CONFIG_DEBUG_FS
.custom_conf_items = lpc18xx_conf_items,
#endif
.owner = THIS_MODULE,
};
@ -1170,9 +1301,8 @@ static int lpc18xx_create_group_func_map(struct device *dev,
u16 pins[ARRAY_SIZE(lpc18xx_pins)];
int func, ngroups, i;
for (func = 0; func < FUNC_MAX; ngroups = 0, func++) {
for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
for (func = 0; func < FUNC_MAX; func++) {
for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
if (lpc18xx_valid_pin_function(i, func))
pins[ngroups++] = i;
}

2312
drivers/pinctrl/pinctrl-pic32.c Normal file
View File

File diff suppressed because it is too large Load Diff

141
drivers/pinctrl/pinctrl-pic32.h Normal file
View File

@ -0,0 +1,141 @@
/*
* PIC32 pinctrl driver
*
* Joshua Henderson, <joshua.henderson@microchip.com>
* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef PINCTRL_PINCTRL_PIC32_H
#define PINCTRL_PINCTRL_PIC32_H
/* PORT Registers */
#define ANSEL_REG 0x00
#define TRIS_REG 0x10
#define PORT_REG 0x20
#define LAT_REG 0x30
#define ODCU_REG 0x40
#define CNPU_REG 0x50
#define CNPD_REG 0x60
#define CNCON_REG 0x70
#define CNEN_REG 0x80
#define CNSTAT_REG 0x90
#define CNNE_REG 0xA0
#define CNF_REG 0xB0
/* Input PPS Registers */
#define INT1R 0x04
#define INT2R 0x08
#define INT3R 0x0C
#define INT4R 0x10
#define T2CKR 0x18
#define T3CKR 0x1C
#define T4CKR 0x20
#define T5CKR 0x24
#define T6CKR 0x28
#define T7CKR 0x2C
#define T8CKR 0x30
#define T9CKR 0x34
#define IC1R 0x38
#define IC2R 0x3C
#define IC3R 0x40
#define IC4R 0x44
#define IC5R 0x48
#define IC6R 0x4C
#define IC7R 0x50
#define IC8R 0x54
#define IC9R 0x58
#define OCFAR 0x60
#define U1RXR 0x68
#define U1CTSR 0x6C
#define U2RXR 0x70
#define U2CTSR 0x74
#define U3RXR 0x78
#define U3CTSR 0x7C
#define U4RXR 0x80
#define U4CTSR 0x84
#define U5RXR 0x88
#define U5CTSR 0x8C
#define U6RXR 0x90
#define U6CTSR 0x94
#define SDI1R 0x9C
#define SS1INR 0xA0
#define SDI2R 0xA8
#define SS2INR 0xAC
#define SDI3R 0xB4
#define SS3INR 0xB8
#define SDI4R 0xC0
#define SS4INR 0xC4
#define SDI5R 0xCC
#define SS5INR 0xD0
#define SDI6R 0xD8
#define SS6INR 0xDC
#define C1RXR 0xE0
#define C2RXR 0xE4
#define REFCLKI1R 0xE8
#define REFCLKI3R 0xF0
#define REFCLKI4R 0xF4
/* Output PPS Registers */
#define RPA14R 0x138
#define RPA15R 0x13C
#define RPB0R 0x140
#define RPB1R 0x144
#define RPB2R 0x148
#define RPB3R 0x14C
#define RPB5R 0x154
#define RPB6R 0x158
#define RPB7R 0x15C
#define RPB8R 0x160
#define RPB9R 0x164
#define RPB10R 0x168
#define RPB14R 0x178
#define RPB15R 0x17C
#define RPC1R 0x184
#define RPC2R 0x188
#define RPC3R 0x18C
#define RPC4R 0x190
#define RPC13R 0x1B4
#define RPC14R 0x1B8
#define RPD0R 0x1C0
#define RPD1R 0x1C4
#define RPD2R 0x1C8
#define RPD3R 0x1CC
#define RPD4R 0x1D0
#define RPD5R 0x1D4
#define RPD6R 0x1D8
#define RPD7R 0x1DC
#define RPD9R 0x1E4
#define RPD10R 0x1E8
#define RPD11R 0x1EC
#define RPD12R 0x1F0
#define RPD14R 0x1F8
#define RPD15R 0x1FC
#define RPE3R 0x20C
#define RPE5R 0x214
#define RPE8R 0x220
#define RPE9R 0x224
#define RPF0R 0x240
#define RPF1R 0x244
#define RPF2R 0x248
#define RPF3R 0x24C
#define RPF4R 0x250
#define RPF5R 0x254
#define RPF8R 0x260
#define RPF12R 0x270
#define RPF13R 0x274
#define RPG0R 0x280
#define RPG1R 0x284
#define RPG6R 0x298
#define RPG7R 0x29C
#define RPG8R 0x2A0
#define RPG9R 0x2A4
#endif /* PINCTRL_PINCTRL_PIC32_H */

369
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -64,6 +64,7 @@ enum rockchip_pinctrl_type {
RK3188,
RK3288,
RK3368,
RK3399,
};
/**
@ -85,6 +86,31 @@ struct rockchip_iomux {
int offset;
};
/**
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
enum rockchip_pin_drv_type {
DRV_TYPE_IO_DEFAULT = 0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_3V0_AUTO,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_MAX
};
/**
* @drv_type: drive strength variant using rockchip_perpin_drv_type
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
* to a new value for autocalculating the following drive strength
* registers. if used chips own cal_drv func instead to calculate
* registers offset, the variant could be ignored.
*/
struct rockchip_drv {
enum rockchip_pin_drv_type drv_type;
int offset;
};
/**
* @reg_base: register base of the gpio bank
* @reg_pull: optional separate register for additional pull settings
@ -96,6 +122,7 @@ struct rockchip_iomux {
* @name: name of the bank
* @bank_num: number of the bank, to account for holes
* @iomux: array describing the 4 iomux sources of the bank
* @drv: array describing the 4 drive strength sources of the bank
* @valid: are all necessary informations present
* @of_node: dt node of this bank
* @drvdata: common pinctrl basedata
@ -115,6 +142,7 @@ struct rockchip_pin_bank {
char *name;
u8 bank_num;
struct rockchip_iomux iomux[4];
struct rockchip_drv drv[4];
bool valid;
struct device_node *of_node;
struct rockchip_pinctrl *drvdata;
@ -151,6 +179,47 @@ struct rockchip_pin_bank {
}, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
{ .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = type0, .offset = -1 }, \
{ .drv_type = type1, .offset = -1 }, \
{ .drv_type = type2, .offset = -1 }, \
{ .drv_type = type3, .offset = -1 }, \
}, \
}
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
offset2, offset3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = -1 }, \
{ .type = iom1, .offset = -1 }, \
{ .type = iom2, .offset = -1 }, \
{ .type = iom3, .offset = -1 }, \
}, \
.drv = { \
{ .drv_type = drv0, .offset = offset0 }, \
{ .drv_type = drv1, .offset = offset1 }, \
{ .drv_type = drv2, .offset = offset2 }, \
{ .drv_type = drv3, .offset = offset3 }, \
}, \
}
/**
*/
struct rockchip_pin_ctrl {
@ -161,6 +230,9 @@ struct rockchip_pin_ctrl {
enum rockchip_pinctrl_type type;
int grf_mux_offset;
int pmu_mux_offset;
int grf_drv_offset;
int pmu_drv_offset;
void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
@ -705,7 +777,68 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
}
static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
/* The bank0:16 and bank1:32 pins are located in PMU */
if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3188_PULL_PINS_PER_REG;
*bit *= RK3188_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
*bit = (pin_num % RK3188_PULL_PINS_PER_REG);
*bit *= RK3188_PULL_BITS_PER_PIN;
}
}
static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int drv_num = (pin_num / 8);
/* The bank0:16 and bank1:32 pins are located in PMU */
if ((bank->bank_num == 0) || (bank->bank_num == 1))
*regmap = info->regmap_pmu;
else
*regmap = info->regmap_base;
*reg = bank->drv[drv_num].offset;
if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
(bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
*bit = (pin_num % 8) * 3;
else
*bit = (pin_num % 8) * 2;
}
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
{ 2, 4, 8, 12, -1, -1, -1, -1 },
{ 3, 6, 9, 12, -1, -1, -1, -1 },
{ 5, 10, 15, 20, -1, -1, -1, -1 },
{ 4, 6, 8, 10, 12, 14, 16, 18 },
{ 4, 7, 10, 13, 16, 19, 22, 26 }
};
static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
@ -714,19 +847,74 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data;
u32 data, temp, rmask_bits;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = RK3399_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is
* spread over 2 registers
*/
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
ret = regmap_read(regmap, reg + 0x4, &temp);
if (ret)
return ret;
/*
* the bit data[15] contains bit 0 of the value
* while temp[1:0] contains bits 2 and 1
*/
data >>= 15;
temp &= 0x3;
temp <<= 1;
data |= temp;
return rockchip_perpin_drv_list[drv_type][data];
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
drv_type);
return -EINVAL;
}
ret = regmap_read(regmap, reg, &data);
if (ret)
return ret;
data >>= bit;
data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
data &= (1 << rmask_bits) - 1;
return rockchip_perpin_drv_list[data];
return rockchip_perpin_drv_list[drv_type][data];
}
static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
@ -737,16 +925,23 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
struct regmap *regmap;
unsigned long flags;
int reg, ret, i;
u32 data, rmask;
u32 data, rmask, rmask_bits, temp;
u8 bit;
int drv_type = bank->drv[pin_num / 8].drv_type;
dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
bank->bank_num, pin_num, strength);
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
if (rockchip_perpin_drv_list[i] == strength) {
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
ret = i;
break;
} else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
ret = rockchip_perpin_drv_list[drv_type][i];
break;
}
}
@ -758,8 +953,64 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
spin_lock_irqsave(&bank->slock, flags);
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
rmask_bits = RK3399_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
break;
case 15:
/*
* drive-strength offset is special, as it is spread
* over 2 registers, the bit data[15] contains bit 0
* of the value while temp[1:0] contains bits 2 and 1
*/
data = (ret & 0x1) << 15;
temp = (ret >> 0x1) & 0x3;
rmask = BIT(15) | BIT(31);
data |= BIT(31);
ret = regmap_update_bits(regmap, reg, rmask, data);
if (ret) {
spin_unlock_irqrestore(&bank->slock, flags);
return ret;
}
rmask = 0x3 | (0x3 << 16);
temp |= (0x3 << 16);
reg += 0x4;
ret = regmap_update_bits(regmap, reg, rmask, temp);
spin_unlock_irqrestore(&bank->slock, flags);
return ret;
case 18 ... 21:
/* setting fully enclosed in the second register */
reg += 4;
bit -= 16;
break;
default:
spin_unlock_irqrestore(&bank->slock, flags);
dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
bit, drv_type);
return -EINVAL;
}
break;
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
rmask_bits = RK3288_DRV_BITS_PER_PIN;
break;
default:
spin_unlock_irqrestore(&bank->slock, flags);
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
drv_type);
return -EINVAL;
}
/* enable the write to the equivalent lower bits */
data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
data = ((1 << rmask_bits) - 1) << (bit + 16);
rmask = data | (data >> 16);
data |= (ret << bit);
@ -796,6 +1047,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3188:
case RK3288:
case RK3368:
case RK3399:
data >>= bit;
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
@ -852,6 +1104,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3188:
case RK3288:
case RK3368:
case RK3399:
spin_lock_irqsave(&bank->slock, flags);
/* enable the write to the equivalent lower bits */
@ -1032,6 +1285,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3188:
case RK3288:
case RK3368:
case RK3399:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
@ -1892,7 +2146,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct device_node *np;
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, i, j;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@ -1916,6 +2170,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
grf_offs = ctrl->grf_mux_offset;
pmu_offs = ctrl->pmu_mux_offset;
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
@ -1925,27 +2181,39 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
bank->pin_base = ctrl->nr_pins;
ctrl->nr_pins += bank->nr_pins;
/* calculate iomux offsets */
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
struct rockchip_iomux *iom = &bank->iomux[j];
struct rockchip_drv *drv = &bank->drv[j];
int inc;
if (bank_pins >= bank->nr_pins)
break;
/* preset offset value, set new start value */
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current offset */
} else { /* set current iomux offset */
iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
pmu_offs : grf_offs;
}
dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
i, j, iom->offset);
/* preset drv offset value, set new start value */
if (drv->offset >= 0) {
if (iom->type & IOMUX_SOURCE_PMU)
drv_pmu_offs = drv->offset;
else
drv_grf_offs = drv->offset;
} else { /* set current drv offset */
drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
drv_pmu_offs : drv_grf_offs;
}
dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
i, j, iom->offset, drv->offset);
/*
* Increase offset according to iomux width.
@ -1957,6 +2225,21 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
else
grf_offs += inc;
/*
* Increase offset according to drv width.
* 3bit drive-strenth'es are spread over two registers.
*/
if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
(drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
inc = 8;
else
inc = 4;
if (iom->type & IOMUX_SOURCE_PMU)
drv_pmu_offs += inc;
else
drv_grf_offs += inc;
bank_pins += 8;
}
}
@ -2257,6 +2540,62 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.drv_calc_reg = rk3368_calc_drv_reg_and_bit,
};
static struct rockchip_pin_bank rk3399_pin_banks[] = {
PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_DEFAULT,
DRV_TYPE_IO_DEFAULT,
0x0,
0x8,
-1,
-1
),
PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
0x20,
0x28,
0x30,
0x38
),
PIN_BANK_DRV_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_1V8_ONLY
),
PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_3V3_ONLY,
DRV_TYPE_IO_1V8_OR_3V0
),
PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_3V0_AUTO,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0
),
};
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
.pmu_mux_offset = 0x0,
.grf_drv_offset = 0xe100,
.pmu_drv_offset = 0x80,
.pull_calc_reg = rk3399_calc_pull_reg_and_bit,
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
};
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk2928-pinctrl",
@ -2275,6 +2614,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = (void *)&rk3288_pin_ctrl },
{ .compatible = "rockchip,rk3368-pinctrl",
.data = (void *)&rk3368_pin_ctrl },
{ .compatible = "rockchip,rk3399-pinctrl",
.data = (void *)&rk3399_pin_ctrl },
{},
};
MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);

8
drivers/pinctrl/pinctrl-single.c
View File

@ -254,6 +254,13 @@ static enum pin_config_param pcs_bias[] = {
PIN_CONFIG_BIAS_PULL_UP,
};
/*
* This lock class tells lockdep that irqchip core that this single
* pinctrl can be in a different category than its parents, so it won't
* report false recursion.
*/
static struct lock_class_key pcs_lock_class;
/*
* REVISIT: Reads and writes could eventually use regmap or something
* generic. But at least on omaps, some mux registers are performance
@ -1713,6 +1720,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_set_chip_data(irq, pcs_soc);
irq_set_chip_and_handler(irq, &pcs->chip,
handle_level_irq);
irq_set_lockdep_class(irq, &pcs_lock_class);
irq_set_noprobe(irq);
return 0;

1
drivers/pinctrl/pinctrl-st.c
View File

@ -985,6 +985,7 @@ static struct pinmux_ops st_pmxops = {
.get_function_groups = st_pmx_get_groups,
.set_mux = st_pmx_set_mux,
.gpio_set_direction = st_pmx_set_gpio_direction,
.strict = true,
};
/* Pinconf */

2
drivers/pinctrl/pinctrl-zynq.c
View File

@ -590,7 +590,7 @@ static const char * const usb1_groups[] = {"usb1_0_grp"};
static const char * const mdio0_groups[] = {"mdio0_0_grp"};
static const char * const mdio1_groups[] = {"mdio1_0_grp"};
static const char * const qspi0_groups[] = {"qspi0_0_grp"};
static const char * const qspi1_groups[] = {"qspi0_1_grp"};
static const char * const qspi1_groups[] = {"qspi1_0_grp"};
static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",

3
drivers/pinctrl/pxa/pinctrl-pxa2xx.c
View File

@ -426,7 +426,7 @@ int pxa2xx_pinctrl_init(struct platform_device *pdev,
return 0;
}
EXPORT_SYMBOL(pxa2xx_pinctrl_init);
EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
int pxa2xx_pinctrl_exit(struct platform_device *pdev)
{
@ -435,3 +435,4 @@ int pxa2xx_pinctrl_exit(struct platform_device *pdev)
pinctrl_unregister(pctl->pctl_dev);
return 0;
}
EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit);

8
drivers/pinctrl/qcom/Kconfig
View File

@ -23,6 +23,14 @@ config PINCTRL_APQ8084
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
config PINCTRL_IPQ4019
tristate "Qualcomm IPQ4019 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on GPIOLIB && OF

1
drivers/pinctrl/qcom/Makefile
View File

@ -2,6 +2,7 @@
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o

453
drivers/pinctrl/qcom/pinctrl-ipq4019.c Normal file
View File

@ -0,0 +1,453 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-msm.h"
static const struct pinctrl_pin_desc ipq4019_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
PINCTRL_PIN(1, "GPIO_1"),
PINCTRL_PIN(2, "GPIO_2"),
PINCTRL_PIN(3, "GPIO_3"),
PINCTRL_PIN(4, "GPIO_4"),
PINCTRL_PIN(5, "GPIO_5"),
PINCTRL_PIN(6, "GPIO_6"),
PINCTRL_PIN(7, "GPIO_7"),
PINCTRL_PIN(8, "GPIO_8"),
PINCTRL_PIN(9, "GPIO_9"),
PINCTRL_PIN(10, "GPIO_10"),
PINCTRL_PIN(11, "GPIO_11"),
PINCTRL_PIN(12, "GPIO_12"),
PINCTRL_PIN(13, "GPIO_13"),
PINCTRL_PIN(14, "GPIO_14"),
PINCTRL_PIN(15, "GPIO_15"),
PINCTRL_PIN(16, "GPIO_16"),
PINCTRL_PIN(17, "GPIO_17"),
PINCTRL_PIN(18, "GPIO_18"),
PINCTRL_PIN(19, "GPIO_19"),
PINCTRL_PIN(20, "GPIO_20"),
PINCTRL_PIN(21, "GPIO_21"),
PINCTRL_PIN(22, "GPIO_22"),
PINCTRL_PIN(23, "GPIO_23"),
PINCTRL_PIN(24, "GPIO_24"),
PINCTRL_PIN(25, "GPIO_25"),
PINCTRL_PIN(26, "GPIO_26"),
PINCTRL_PIN(27, "GPIO_27"),
PINCTRL_PIN(28, "GPIO_28"),
PINCTRL_PIN(29, "GPIO_29"),
PINCTRL_PIN(30, "GPIO_30"),
PINCTRL_PIN(31, "GPIO_31"),
PINCTRL_PIN(32, "GPIO_32"),
PINCTRL_PIN(33, "GPIO_33"),
PINCTRL_PIN(34, "GPIO_34"),
PINCTRL_PIN(35, "GPIO_35"),
PINCTRL_PIN(36, "GPIO_36"),
PINCTRL_PIN(37, "GPIO_37"),
PINCTRL_PIN(38, "GPIO_38"),
PINCTRL_PIN(39, "GPIO_39"),
PINCTRL_PIN(40, "GPIO_40"),
PINCTRL_PIN(41, "GPIO_41"),
PINCTRL_PIN(42, "GPIO_42"),
PINCTRL_PIN(43, "GPIO_43"),
PINCTRL_PIN(44, "GPIO_44"),
PINCTRL_PIN(45, "GPIO_45"),
PINCTRL_PIN(46, "GPIO_46"),
PINCTRL_PIN(47, "GPIO_47"),
PINCTRL_PIN(48, "GPIO_48"),
PINCTRL_PIN(49, "GPIO_49"),
PINCTRL_PIN(50, "GPIO_50"),
PINCTRL_PIN(51, "GPIO_51"),
PINCTRL_PIN(52, "GPIO_52"),
PINCTRL_PIN(53, "GPIO_53"),
PINCTRL_PIN(54, "GPIO_54"),
PINCTRL_PIN(55, "GPIO_55"),
PINCTRL_PIN(56, "GPIO_56"),
PINCTRL_PIN(57, "GPIO_57"),
PINCTRL_PIN(58, "GPIO_58"),
PINCTRL_PIN(59, "GPIO_59"),
PINCTRL_PIN(60, "GPIO_60"),
PINCTRL_PIN(61, "GPIO_61"),
PINCTRL_PIN(62, "GPIO_62"),
PINCTRL_PIN(63, "GPIO_63"),
PINCTRL_PIN(64, "GPIO_64"),
PINCTRL_PIN(65, "GPIO_65"),
PINCTRL_PIN(66, "GPIO_66"),
PINCTRL_PIN(67, "GPIO_67"),
PINCTRL_PIN(68, "GPIO_68"),
PINCTRL_PIN(69, "GPIO_69"),
PINCTRL_PIN(70, "GPIO_70"),
PINCTRL_PIN(71, "GPIO_71"),
PINCTRL_PIN(72, "GPIO_72"),
PINCTRL_PIN(73, "GPIO_73"),
PINCTRL_PIN(74, "GPIO_74"),
PINCTRL_PIN(75, "GPIO_75"),
PINCTRL_PIN(76, "GPIO_76"),
PINCTRL_PIN(77, "GPIO_77"),
PINCTRL_PIN(78, "GPIO_78"),
PINCTRL_PIN(79, "GPIO_79"),
PINCTRL_PIN(80, "GPIO_80"),
PINCTRL_PIN(81, "GPIO_81"),
PINCTRL_PIN(82, "GPIO_82"),
PINCTRL_PIN(83, "GPIO_83"),
PINCTRL_PIN(84, "GPIO_84"),
PINCTRL_PIN(85, "GPIO_85"),
PINCTRL_PIN(86, "GPIO_86"),
PINCTRL_PIN(87, "GPIO_87"),
PINCTRL_PIN(88, "GPIO_88"),
PINCTRL_PIN(89, "GPIO_89"),
PINCTRL_PIN(90, "GPIO_90"),
PINCTRL_PIN(91, "GPIO_91"),
PINCTRL_PIN(92, "GPIO_92"),
PINCTRL_PIN(93, "GPIO_93"),
PINCTRL_PIN(94, "GPIO_94"),
PINCTRL_PIN(95, "GPIO_95"),
PINCTRL_PIN(96, "GPIO_96"),
PINCTRL_PIN(97, "GPIO_97"),
PINCTRL_PIN(98, "GPIO_98"),
PINCTRL_PIN(99, "GPIO_99"),
};
#define DECLARE_QCA_GPIO_PINS(pin) \
static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_QCA_GPIO_PINS(0);
DECLARE_QCA_GPIO_PINS(1);
DECLARE_QCA_GPIO_PINS(2);
DECLARE_QCA_GPIO_PINS(3);
DECLARE_QCA_GPIO_PINS(4);
DECLARE_QCA_GPIO_PINS(5);
DECLARE_QCA_GPIO_PINS(6);
DECLARE_QCA_GPIO_PINS(7);
DECLARE_QCA_GPIO_PINS(8);
DECLARE_QCA_GPIO_PINS(9);
DECLARE_QCA_GPIO_PINS(10);
DECLARE_QCA_GPIO_PINS(11);
DECLARE_QCA_GPIO_PINS(12);
DECLARE_QCA_GPIO_PINS(13);
DECLARE_QCA_GPIO_PINS(14);
DECLARE_QCA_GPIO_PINS(15);
DECLARE_QCA_GPIO_PINS(16);
DECLARE_QCA_GPIO_PINS(17);
DECLARE_QCA_GPIO_PINS(18);
DECLARE_QCA_GPIO_PINS(19);
DECLARE_QCA_GPIO_PINS(20);
DECLARE_QCA_GPIO_PINS(21);
DECLARE_QCA_GPIO_PINS(22);
DECLARE_QCA_GPIO_PINS(23);
DECLARE_QCA_GPIO_PINS(24);
DECLARE_QCA_GPIO_PINS(25);
DECLARE_QCA_GPIO_PINS(26);
DECLARE_QCA_GPIO_PINS(27);
DECLARE_QCA_GPIO_PINS(28);
DECLARE_QCA_GPIO_PINS(29);
DECLARE_QCA_GPIO_PINS(30);
DECLARE_QCA_GPIO_PINS(31);
DECLARE_QCA_GPIO_PINS(32);
DECLARE_QCA_GPIO_PINS(33);
DECLARE_QCA_GPIO_PINS(34);
DECLARE_QCA_GPIO_PINS(35);
DECLARE_QCA_GPIO_PINS(36);
DECLARE_QCA_GPIO_PINS(37);
DECLARE_QCA_GPIO_PINS(38);
DECLARE_QCA_GPIO_PINS(39);
DECLARE_QCA_GPIO_PINS(40);
DECLARE_QCA_GPIO_PINS(41);
DECLARE_QCA_GPIO_PINS(42);
DECLARE_QCA_GPIO_PINS(43);
DECLARE_QCA_GPIO_PINS(44);
DECLARE_QCA_GPIO_PINS(45);
DECLARE_QCA_GPIO_PINS(46);
DECLARE_QCA_GPIO_PINS(47);
DECLARE_QCA_GPIO_PINS(48);
DECLARE_QCA_GPIO_PINS(49);
DECLARE_QCA_GPIO_PINS(50);
DECLARE_QCA_GPIO_PINS(51);
DECLARE_QCA_GPIO_PINS(52);
DECLARE_QCA_GPIO_PINS(53);
DECLARE_QCA_GPIO_PINS(54);
DECLARE_QCA_GPIO_PINS(55);
DECLARE_QCA_GPIO_PINS(56);
DECLARE_QCA_GPIO_PINS(57);
DECLARE_QCA_GPIO_PINS(58);
DECLARE_QCA_GPIO_PINS(59);
DECLARE_QCA_GPIO_PINS(60);
DECLARE_QCA_GPIO_PINS(61);
DECLARE_QCA_GPIO_PINS(62);
DECLARE_QCA_GPIO_PINS(63);
DECLARE_QCA_GPIO_PINS(64);
DECLARE_QCA_GPIO_PINS(65);
DECLARE_QCA_GPIO_PINS(66);
DECLARE_QCA_GPIO_PINS(67);
DECLARE_QCA_GPIO_PINS(68);
DECLARE_QCA_GPIO_PINS(69);
DECLARE_QCA_GPIO_PINS(70);
DECLARE_QCA_GPIO_PINS(71);
DECLARE_QCA_GPIO_PINS(72);
DECLARE_QCA_GPIO_PINS(73);
DECLARE_QCA_GPIO_PINS(74);
DECLARE_QCA_GPIO_PINS(75);
DECLARE_QCA_GPIO_PINS(76);
DECLARE_QCA_GPIO_PINS(77);
DECLARE_QCA_GPIO_PINS(78);
DECLARE_QCA_GPIO_PINS(79);
DECLARE_QCA_GPIO_PINS(80);
DECLARE_QCA_GPIO_PINS(81);
DECLARE_QCA_GPIO_PINS(82);
DECLARE_QCA_GPIO_PINS(83);
DECLARE_QCA_GPIO_PINS(84);
DECLARE_QCA_GPIO_PINS(85);
DECLARE_QCA_GPIO_PINS(86);
DECLARE_QCA_GPIO_PINS(87);
DECLARE_QCA_GPIO_PINS(88);
DECLARE_QCA_GPIO_PINS(89);
DECLARE_QCA_GPIO_PINS(90);
DECLARE_QCA_GPIO_PINS(91);
DECLARE_QCA_GPIO_PINS(92);
DECLARE_QCA_GPIO_PINS(93);
DECLARE_QCA_GPIO_PINS(94);
DECLARE_QCA_GPIO_PINS(95);
DECLARE_QCA_GPIO_PINS(96);
DECLARE_QCA_GPIO_PINS(97);
DECLARE_QCA_GPIO_PINS(98);
DECLARE_QCA_GPIO_PINS(99);
#define FUNCTION(fname) \
[qca_mux_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
}
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
{ \
.name = "gpio" #id, \
.pins = gpio##id##_pins, \
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
qca_mux_NA, /* gpio mode */ \
qca_mux_##f1, \
qca_mux_##f2, \
qca_mux_##f3, \
qca_mux_##f4, \
qca_mux_##f5, \
qca_mux_##f6, \
qca_mux_##f7, \
qca_mux_##f8, \
qca_mux_##f9, \
qca_mux_##f10, \
qca_mux_##f11, \
qca_mux_##f12, \
qca_mux_##f13, \
qca_mux_##f14 \
}, \
.nfuncs = 15, \
.ctl_reg = 0x1000 + 0x10 * id, \
.io_reg = 0x1004 + 0x10 * id, \
.intr_cfg_reg = 0x1008 + 0x10 * id, \
.intr_status_reg = 0x100c + 0x10 * id, \
.intr_target_reg = 0x400 + 0x4 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
.oe_bit = 9, \
.in_bit = 0, \
.out_bit = 1, \
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
.intr_detection_width = 2, \
}
enum ipq4019_functions {
qca_mux_gpio,
qca_mux_blsp_uart1,
qca_mux_blsp_i2c0,
qca_mux_blsp_i2c1,
qca_mux_blsp_uart0,
qca_mux_blsp_spi1,
qca_mux_blsp_spi0,
qca_mux_NA,
};
static const char * const gpio_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99",
};
static const char * const blsp_uart1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11",
};
static const char * const blsp_i2c0_groups[] = {
"gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
};
static const char * const blsp_spi0_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
"gpio54", "gpio55", "gpio56", "gpio57",
};
static const char * const blsp_i2c1_groups[] = {
"gpio12", "gpio13", "gpio34", "gpio35",
};
static const char * const blsp_uart0_groups[] = {
"gpio16", "gpio17", "gpio60", "gpio61",
};
static const char * const blsp_spi1_groups[] = {
"gpio44", "gpio45", "gpio46", "gpio47",
};
static const struct msm_function ipq4019_functions[] = {
FUNCTION(gpio),
FUNCTION(blsp_uart1),
FUNCTION(blsp_i2c0),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_uart0),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi0),
};
static const struct msm_pingroup ipq4019_groups[] = {
PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
};
static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.pins = ipq4019_pins,
.npins = ARRAY_SIZE(ipq4019_pins),
.functions = ipq4019_functions,
.nfunctions = ARRAY_SIZE(ipq4019_functions),
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
.ngpios = 70,
};
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
{
return msm_pinctrl_probe(pdev, &ipq4019_pinctrl);
}
static const struct of_device_id ipq4019_pinctrl_of_match[] = {
{ .compatible = "qcom,ipq4019-pinctrl", },
{ },
};
static struct platform_driver ipq4019_pinctrl_driver = {
.driver = {
.name = "ipq4019-pinctrl",
.of_match_table = ipq4019_pinctrl_of_match,
},
.probe = ipq4019_pinctrl_probe,
.remove = msm_pinctrl_remove,
};
static int __init ipq4019_pinctrl_init(void)
{
return platform_driver_register(&ipq4019_pinctrl_driver);
}
arch_initcall(ipq4019_pinctrl_init);
static void __exit ipq4019_pinctrl_exit(void)
{
platform_driver_unregister(&ipq4019_pinctrl_driver);
}
module_exit(ipq4019_pinctrl_exit);
MODULE_DESCRIPTION("Qualcomm ipq4019 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, ipq4019_pinctrl_of_match);

30
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
View File

@ -117,6 +117,7 @@
* @output_enabled: Set to true if MPP output logic is enabled.
* @input_enabled: Set to true if MPP input buffer logic is enabled.
* @paired: Pin operates in paired mode
* @has_pullup: Pin has support to configure pullup
* @num_sources: Number of power-sources supported by this MPP.
* @power_source: Current power-source used.
* @amux_input: Set the source for analog input.
@ -134,6 +135,7 @@ struct pmic_mpp_pad {
bool output_enabled;
bool input_enabled;
bool paired;
bool has_pullup;
unsigned int num_sources;
unsigned int power_source;
unsigned int amux_input;
@ -477,11 +479,14 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
if (ret < 0)
return ret;
val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
if (pad->has_pullup) {
val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val);
if (ret < 0)
return ret;
ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL,
val);
if (ret < 0)
return ret;
}
val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
@ -534,7 +539,8 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
seq_printf(s, " vin-%d", pad->power_source);
seq_printf(s, " %d", pad->aout_level);
seq_printf(s, " %-8s", biases[pad->pullup]);
if (pad->has_pullup)
seq_printf(s, " %-8s", biases[pad->pullup]);
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
if (pad->dtest)
seq_printf(s, " dtest%d", pad->dtest);
@ -748,12 +754,16 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
pad->power_source &= PMIC_MPP_REG_VIN_MASK;
val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
if (val < 0)
return val;
if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT &&
subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) {
val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
if (val < 0)
return val;
pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
pad->pullup &= PMIC_MPP_REG_PULL_MASK;
pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
pad->pullup &= PMIC_MPP_REG_PULL_MASK;
pad->has_pullup = true;
}
val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
if (val < 0)

56
drivers/pinctrl/sh-pfc/Kconfig
View File

@ -2,10 +2,9 @@
# Renesas SH and SH Mobile PINCTRL drivers
#
if ARCH_SHMOBILE || SUPERH
if ARCH_RENESAS || SUPERH
config PINCTRL_SH_PFC
select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
select GENERIC_PINCONF
@ -13,12 +12,12 @@ config PINCTRL_SH_PFC
help
This enables pin control drivers for SH and SH Mobile platforms
config GPIO_SH_PFC
bool "SuperH PFC GPIO support"
depends on PINCTRL_SH_PFC && GPIOLIB
config PINCTRL_SH_PFC_GPIO
select GPIOLIB
select PINCTRL_SH_PFC
bool
help
This enables support for GPIOs within the SoC's pin function
controller.
This enables pin control and GPIO drivers for SH/SH Mobile platforms
config PINCTRL_PFC_EMEV2
def_bool y
@ -28,12 +27,12 @@ config PINCTRL_PFC_EMEV2
config PINCTRL_PFC_R8A73A4
def_bool y
depends on ARCH_R8A73A4
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7740
def_bool y
depends on ARCH_R8A7740
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_R8A7778
def_bool y
@ -73,79 +72,66 @@ config PINCTRL_PFC_R8A7795
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7264
def_bool y
depends on CPU_SUBTYPE_SH7264
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7269
def_bool y
depends on CPU_SUBTYPE_SH7269
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH73A0
def_bool y
depends on ARCH_SH73A0
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
select REGULATOR
config PINCTRL_PFC_SH7720
def_bool y
depends on CPU_SUBTYPE_SH7720
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7722
def_bool y
depends on CPU_SUBTYPE_SH7722
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7723
def_bool y
depends on CPU_SUBTYPE_SH7723
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7724
def_bool y
depends on CPU_SUBTYPE_SH7724
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7734
def_bool y
depends on CPU_SUBTYPE_SH7734
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7757
def_bool y
depends on CPU_SUBTYPE_SH7757
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7785
def_bool y
depends on CPU_SUBTYPE_SH7785
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SH7786
def_bool y
depends on CPU_SUBTYPE_SH7786
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
config PINCTRL_PFC_SHX3
def_bool y
depends on CPU_SUBTYPE_SHX3
depends on GPIOLIB
select PINCTRL_SH_PFC
select PINCTRL_SH_PFC_GPIO
endif

7
drivers/pinctrl/sh-pfc/Makefile
View File

@ -1,8 +1,5 @@
sh-pfc-objs = core.o pinctrl.o
ifeq ($(CONFIG_GPIO_SH_PFC),y)
sh-pfc-objs += gpio.o
endif
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o

24
drivers/pinctrl/sh-pfc/core.c
View File

@ -1,5 +1,7 @@
/*
* SuperH Pin Function Controller support.
* Pin Control and GPIO driver for SuperH Pin Function Controller.
*
* Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
*
* Copyright (C) 2008 Magnus Damm
* Copyright (C) 2009 - 2012 Paul Mundt
@ -17,7 +19,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
@ -503,7 +505,6 @@ static const struct of_device_id sh_pfc_of_table[] = {
#endif
{ },
};
MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif
static int sh_pfc_probe(struct platform_device *pdev)
@ -518,7 +519,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
#ifdef CONFIG_OF
if (np)
info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
info = of_device_get_match_data(&pdev->dev);
else
#endif
info = platid ? (const void *)platid->driver_data : NULL;
@ -558,7 +559,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
if (unlikely(ret != 0))
return ret;
#ifdef CONFIG_GPIO_SH_PFC
#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
/*
* Then the GPIO chip
*/
@ -584,7 +585,7 @@ static int sh_pfc_remove(struct platform_device *pdev)
{
struct sh_pfc *pfc = platform_get_drvdata(pdev);
#ifdef CONFIG_GPIO_SH_PFC
#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
sh_pfc_unregister_gpiochip(pfc);
#endif
sh_pfc_unregister_pinctrl(pfc);
@ -632,7 +633,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
{ "sh-pfc", 0 },
{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
static struct platform_driver sh_pfc_driver = {
.probe = sh_pfc_probe,
@ -649,13 +649,3 @@ static int __init sh_pfc_init(void)
return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);
static void __exit sh_pfc_exit(void)
{
platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);
MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");

686
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View File

File diff suppressed because it is too large Load Diff

1134
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

File diff suppressed because it is too large Load Diff

774
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View File

File diff suppressed because it is too large Load Diff

624
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View File

File diff suppressed because it is too large Load Diff

1405
drivers/pinctrl/sh-pfc/pfc-r8a7794.c
View File

File diff suppressed because it is too large Load Diff

907
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View File

File diff suppressed because it is too large Load Diff

412
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View File

@ -591,547 +591,547 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(IRQ3_B),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_1_0, A0),
PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
PINMUX_IPSR_GPSR(IP0_1_0, A0),
PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
PINMUX_IPSR_DATA(IP0_3_2, A1),
PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
PINMUX_IPSR_GPSR(IP0_3_2, A1),
PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
PINMUX_IPSR_DATA(IP0_5_4, A2),
PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
PINMUX_IPSR_GPSR(IP0_5_4, A2),
PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
PINMUX_IPSR_DATA(IP0_7_6, A3),
PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
PINMUX_IPSR_GPSR(IP0_7_6, A3),
PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
PINMUX_IPSR_DATA(IP0_9_8, A4),
PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
PINMUX_IPSR_GPSR(IP0_9_8, A4),
PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
PINMUX_IPSR_DATA(IP0_11_10, A5),
PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
PINMUX_IPSR_GPSR(IP0_11_10, A5),
PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
PINMUX_IPSR_DATA(IP0_13_12, A6),
PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
PINMUX_IPSR_GPSR(IP0_13_12, A6),
PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
PINMUX_IPSR_DATA(IP0_15_14, A7),
PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
PINMUX_IPSR_GPSR(IP0_15_14, A7),
PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
PINMUX_IPSR_DATA(IP0_17_16, A8),
PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
PINMUX_IPSR_GPSR(IP0_17_16, A8),
PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
PINMUX_IPSR_DATA(IP0_19_18, A9),
PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
PINMUX_IPSR_GPSR(IP0_19_18, A9),
PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
PINMUX_IPSR_DATA(IP0_21_20, A10),
PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
PINMUX_IPSR_GPSR(IP0_21_20, A10),
PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
PINMUX_IPSR_DATA(IP0_23_22, A11),
PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
PINMUX_IPSR_GPSR(IP0_23_22, A11),
PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
PINMUX_IPSR_DATA(IP0_25_24, A12),
PINMUX_IPSR_GPSR(IP0_25_24, A12),
PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
PINMUX_IPSR_DATA(IP0_27_26, A13),
PINMUX_IPSR_GPSR(IP0_27_26, A13),
PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
PINMUX_IPSR_DATA(IP0_29_28, A14),
PINMUX_IPSR_GPSR(IP0_29_28, A14),
PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
PINMUX_IPSR_DATA(IP0_31_30, A15),
PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
PINMUX_IPSR_GPSR(IP0_31_30, A15),
PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
/* IPSR1 */
PINMUX_IPSR_DATA(IP1_1_0, A16),
PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
PINMUX_IPSR_GPSR(IP1_1_0, A16),
PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
PINMUX_IPSR_DATA(IP1_3_2, A17),
PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
PINMUX_IPSR_GPSR(IP1_3_2, A17),
PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
PINMUX_IPSR_DATA(IP1_5_4, A18),
PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
PINMUX_IPSR_GPSR(IP1_5_4, A18),
PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
PINMUX_IPSR_DATA(IP1_7_6, A19),
PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
PINMUX_IPSR_GPSR(IP1_7_6, A19),
PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
PINMUX_IPSR_DATA(IP1_9_8, A20),
PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
PINMUX_IPSR_GPSR(IP1_9_8, A20),
PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
PINMUX_IPSR_DATA(IP1_11_10, A21),
PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
PINMUX_IPSR_GPSR(IP1_11_10, A21),
PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
PINMUX_IPSR_DATA(IP1_13_12, A22),
PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
PINMUX_IPSR_GPSR(IP1_13_12, A22),
PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
PINMUX_IPSR_DATA(IP1_15_14, A23),
PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
PINMUX_IPSR_GPSR(IP1_15_14, A23),
PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
PINMUX_IPSR_DATA(IP1_17_16, A24),
PINMUX_IPSR_GPSR(IP1_17_16, A24),
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
PINMUX_IPSR_DATA(IP1_19_18, A25),
PINMUX_IPSR_GPSR(IP1_19_18, A25),
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
PINMUX_IPSR_DATA(IP1_22_20, D0),
PINMUX_IPSR_GPSR(IP1_22_20, D0),
PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP1_25_23, D1),
PINMUX_IPSR_GPSR(IP1_25_23, D1),
PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP1_28_26, D2),
PINMUX_IPSR_GPSR(IP1_28_26, D2),
PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP1_31_29, D3),
PINMUX_IPSR_GPSR(IP1_31_29, D3),
PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
/* IPSR2 */
PINMUX_IPSR_DATA(IP2_2_0, D4),
PINMUX_IPSR_GPSR(IP2_2_0, D4),
PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP2_4_3, D5),
PINMUX_IPSR_GPSR(IP2_4_3, D5),
PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP2_7_5, D6),
PINMUX_IPSR_GPSR(IP2_7_5, D6),
PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP2_10_8, D7),
PINMUX_IPSR_GPSR(IP2_10_8, D7),
PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP2_13_11, D8),
PINMUX_IPSR_GPSR(IP2_13_11, D8),
PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
PINMUX_IPSR_DATA(IP2_16_14, D9),
PINMUX_IPSR_GPSR(IP2_16_14, D9),
PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
PINMUX_IPSR_DATA(IP2_19_17, D10),
PINMUX_IPSR_GPSR(IP2_19_17, D10),
PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
PINMUX_IPSR_DATA(IP2_22_20, D11),
PINMUX_IPSR_GPSR(IP2_22_20, D11),
PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
PINMUX_IPSR_DATA(IP2_24_23, D12),
PINMUX_IPSR_GPSR(IP2_24_23, D12),
PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
PINMUX_IPSR_DATA(IP2_27_25, D13),
PINMUX_IPSR_GPSR(IP2_27_25, D13),
PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
PINMUX_IPSR_DATA(IP2_30_28, D14),
PINMUX_IPSR_GPSR(IP2_30_28, D14),
PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
/* IPSR3 */
PINMUX_IPSR_DATA(IP3_1_0, D15),
PINMUX_IPSR_GPSR(IP3_1_0, D15),
PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
PINMUX_IPSR_DATA(IP3_2, CS1_A26),
PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_11_9, ATARD),
PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_26_24, DACK2),
PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP3_29_27, ATAG),
PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
/* IPSR4 */
PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
/* IPSR5 */
PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
/* IPSR6 */
PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
/* IPSR7 */
PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
/* IPSR8 */
PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
@ -1139,12 +1139,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
@ -1220,26 +1220,26 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
/* IPSE10 */
PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
@ -1254,13 +1254,13 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
@ -1271,85 +1271,85 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
/* IPSR11 */
PINMUX_IPSR_DATA(IP11_0, SCL1),
PINMUX_IPSR_GPSR(IP11_0, SCL1),
PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
PINMUX_IPSR_DATA(IP11_1, SDA1),
PINMUX_IPSR_GPSR(IP11_1, SDA1),
PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
PINMUX_IPSR_DATA(IP11_2, SDA0),
PINMUX_IPSR_GPSR(IP11_2, SDA0),
PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
PINMUX_IPSR_DATA(IP11_3, SDSELF),
PINMUX_IPSR_GPSR(IP11_3, SDSELF),
PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
PINMUX_IPSR_DATA(IP11_15_13, PENC1),
PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
PINMUX_IPSR_DATA(IP11_22_21, DACK0),
PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP11_27_26, DACK1),
PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
};
static const struct sh_pfc_pin pinmux_pins[] = {

98
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -100,10 +100,31 @@ struct pinmux_cfg_reg {
const u8 *var_field_width;
};
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
* one for each possible combination of the register field bit values.
*/
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
/*
* Describe a config register consisting of several fields of different widths
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
* From left to right (i.e. MSB to LSB)
* This macro must be followed by initialization data: For each register field
* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
* one for each possible combination of the register field bit values.
*/
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.var_field_width = (const u8 [r_width]) \
@ -116,6 +137,14 @@ struct pinmux_data_reg {
const u16 *enum_ids;
};
/*
* Describe a data register
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* This macro must be followed by initialization data: For each register bit
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
*/
#define PINMUX_DATA_REG(name, r, r_width) \
.reg = r, .reg_width = r_width, \
.enum_ids = (const u16 [r_width]) \
@ -124,6 +153,10 @@ struct pinmux_irq {
const short *gpios;
};
/*
* Describe the mapping from GPIOs to a single IRQ
* - ids...: List of GPIOs that are mapped to the same IRQ
*/
#define PINMUX_IRQ(ids...) \
{ .gpios = (const short []) { ids, -1 } }
@ -185,18 +218,65 @@ struct sh_pfc_soc_info {
* sh_pfc_soc_info pinmux_data array macros
*/
/*
* Describe generic pinmux data
* - data_or_mark: *_DATA or *_MARK enum ID
* - ids...: List of enum IDs to associate with data_or_mark
*/
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
#define PINMUX_IPSR_NOGP(ispr, fn) \
/*
* Describe a pinmux configuration without GPIO function that needs
* configuration in a Peripheral Function Select Register (IPSR)
* - ipsr: IPSR field (unused, for documentation purposes only)
* - fn: Function name, referring to a field in the IPSR
*/
#define PINMUX_IPSR_NOGP(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn) \
/*
* Describe a pinmux configuration with GPIO function that needs configuration
* in both a Peripheral Function Select Register (IPSR) and in a
* GPIO/Peripheral Function Select Register (GPSR)
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
*/
#define PINMUX_IPSR_GPSR(ipsr, fn) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
/*
* Describe a pinmux configuration without GPIO function that needs
* configuration in a Peripheral Function Select Register (IPSR), and where the
* pinmux function has a representation in a Module Select Register (MOD_SEL).
* - ipsr: IPSR field (unused, for documentation purposes only)
* - fn: Function name, also referring to the IPSR field
* - msel: Module selector
*/
#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
/*
* Describe a pinmux configuration with GPIO function where the pinmux function
* has no representation in a Peripheral Function Select Register (IPSR), but
* instead solely depends on a group selection.
* - gpsr: GPSR field
* - fn: Function name, also referring to the GPSR field
* - gsel: Group selector
*/
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
/*
* Describe a pinmux configuration with GPIO function that needs configuration
* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
* Function Select Register (GPSR), and where the pinmux function has a
* representation in a Module Select Register (MOD_SEL).
* - ipsr: IPSR field
* - fn: Function name, also referring to the IPSR field
* - msel: Module selector
*/
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn)
/*
* Describe a pinmux configuration for a single-function pin with GPIO
@ -381,7 +461,7 @@ struct sh_pfc_soc_info {
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/*
* PORTnCR macro
* PORTnCR helper macro for SH-Mobile/R-Mobile
*/
#define PORTCR(nr, reg) \
{ \

16
drivers/pinctrl/stm32/Kconfig Normal file
View File

@ -0,0 +1,16 @@
if ARCH_STM32 || COMPILE_TEST
config PINCTRL_STM32
bool
depends on OF
select PINMUX
select GENERIC_PINCONF
select GPIOLIB
config PINCTRL_STM32F429
bool "STMicroelectronics STM32F429 pin control" if COMPILE_TEST && !MACH_STM32F429
depends on OF
default MACH_STM32F429
select PINCTRL_STM32
endif

5
drivers/pinctrl/stm32/Makefile Normal file
View File

@ -0,0 +1,5 @@
# Core
obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o

829
drivers/pinctrl/stm32/pinctrl-stm32.c Normal file
View File

@ -0,0 +1,829 @@
/*
* Copyright (C) Maxime Coquelin 2015
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
* License terms: GNU General Public License (GPL), version 2
*
* Heavily based on Mediatek's pinctrl driver
*/
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
#include "pinctrl-stm32.h"
#define STM32_GPIO_MODER 0x00
#define STM32_GPIO_TYPER 0x04
#define STM32_GPIO_SPEEDR 0x08
#define STM32_GPIO_PUPDR 0x0c
#define STM32_GPIO_IDR 0x10
#define STM32_GPIO_ODR 0x14
#define STM32_GPIO_BSRR 0x18
#define STM32_GPIO_LCKR 0x1c
#define STM32_GPIO_AFRL 0x20
#define STM32_GPIO_AFRH 0x24
#define STM32_GPIO_PINS_PER_BANK 16
#define gpio_range_to_bank(chip) \
container_of(chip, struct stm32_gpio_bank, range)
static const char * const stm32_gpio_functions[] = {
"gpio", "af0", "af1",
"af2", "af3", "af4",
"af5", "af6", "af7",
"af8", "af9", "af10",
"af11", "af12", "af13",
"af14", "af15", "analog",
};
struct stm32_pinctrl_group {
const char *name;
unsigned long config;
unsigned pin;
};
struct stm32_gpio_bank {
void __iomem *base;
struct clk *clk;
spinlock_t lock;
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range range;
};
struct stm32_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl_dev;
struct pinctrl_desc pctl_desc;
struct stm32_pinctrl_group *groups;
unsigned ngroups;
const char **grp_names;
struct stm32_gpio_bank *banks;
unsigned nbanks;
const struct stm32_pinctrl_match_data *match_data;
};
static inline int stm32_gpio_pin(int gpio)
{
return gpio % STM32_GPIO_PINS_PER_BANK;
}
static inline u32 stm32_gpio_get_mode(u32 function)
{
switch (function) {
case STM32_PIN_GPIO:
return 0;
case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
return 2;
case STM32_PIN_ANALOG:
return 3;
}
return 0;
}
static inline u32 stm32_gpio_get_alt(u32 function)
{
switch (function) {
case STM32_PIN_GPIO:
return 0;
case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
return function - 1;
case STM32_PIN_ANALOG:
return 0;
}
return 0;
}
/* GPIO functions */
static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
unsigned offset, int value)
{
if (!value)
offset += STM32_GPIO_PINS_PER_BANK;
clk_enable(bank->clk);
writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
clk_disable(bank->clk);
}
static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_request_gpio(chip->base + offset);
}
static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
{
pinctrl_free_gpio(chip->base + offset);
}
static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
int ret;
clk_enable(bank->clk);
ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
clk_disable(bank->clk);
return ret;
}
static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
}
static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int stm32_gpio_direction_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
__stm32_gpio_set(bank, offset, value);
pinctrl_gpio_direction_output(chip->base + offset);
return 0;
}
static struct gpio_chip stm32_gpio_template = {
.request = stm32_gpio_request,
.free = stm32_gpio_free,
.get = stm32_gpio_get,
.set = stm32_gpio_set,
.direction_input = stm32_gpio_direction_input,
.direction_output = stm32_gpio_direction_output,
};
/* Pinctrl functions */
static struct stm32_pinctrl_group *
stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
{
int i;
for (i = 0; i < pctl->ngroups; i++) {
struct stm32_pinctrl_group *grp = pctl->groups + i;
if (grp->pin == pin)
return grp;
}
return NULL;
}
static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
u32 pin_num, u32 fnum)
{
int i;
for (i = 0; i < pctl->match_data->npins; i++) {
const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
const struct stm32_desc_function *func = pin->functions;
if (pin->pin.number != pin_num)
continue;
while (func && func->name) {
if (func->num == fnum)
return true;
func++;
}
break;
}
return false;
}
static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps)
{
if (*num_maps == *reserved_maps)
return -ENOSPC;
(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
(*map)[*num_maps].data.mux.group = grp->name;
if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
dev_err(pctl->dev, "invalid function %d on pin %d .\n",
fnum, pin);
return -EINVAL;
}
(*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
(*num_maps)++;
return 0;
}
static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
struct device_node *node,
struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps)
{
struct stm32_pinctrl *pctl;
struct stm32_pinctrl_group *grp;
struct property *pins;
u32 pinfunc, pin, func;
unsigned long *configs;
unsigned int num_configs;
bool has_config = 0;
unsigned reserve = 0;
int num_pins, num_funcs, maps_per_pin, i, err;
pctl = pinctrl_dev_get_drvdata(pctldev);
pins = of_find_property(node, "pinmux", NULL);
if (!pins) {
dev_err(pctl->dev, "missing pins property in node %s .\n",
node->name);
return -EINVAL;
}
err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
&num_configs);
if (err)
return err;
if (num_configs)
has_config = 1;
num_pins = pins->length / sizeof(u32);
num_funcs = num_pins;
maps_per_pin = 0;
if (num_funcs)
maps_per_pin++;
if (has_config && num_pins >= 1)
maps_per_pin++;
if (!num_pins || !maps_per_pin)
return -EINVAL;
reserve = num_pins * maps_per_pin;
err = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps, num_maps, reserve);
if (err)
return err;
for (i = 0; i < num_pins; i++) {
err = of_property_read_u32_index(node, "pinmux",
i, &pinfunc);
if (err)
return err;
pin = STM32_GET_PIN_NO(pinfunc);
func = STM32_GET_PIN_FUNC(pinfunc);
if (pin >= pctl->match_data->npins) {
dev_err(pctl->dev, "invalid pin number.\n");
return -EINVAL;
}
if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
dev_err(pctl->dev, "invalid function.\n");
return -EINVAL;
}
grp = stm32_pctrl_find_group_by_pin(pctl, pin);
if (!grp) {
dev_err(pctl->dev, "unable to match pin %d to group\n",
pin);
return -EINVAL;
}
err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
reserved_maps, num_maps);
if (err)
return err;
if (has_config) {
err = pinctrl_utils_add_map_configs(pctldev, map,
reserved_maps, num_maps, grp->name,
configs, num_configs,
PIN_MAP_TYPE_CONFIGS_GROUP);
if (err)
return err;
}
}
return 0;
}
static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps)
{
struct device_node *np;
unsigned reserved_maps;
int ret;
*map = NULL;
*num_maps = 0;
reserved_maps = 0;
for_each_child_of_node(np_config, np) {
ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
return 0;
}
static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->ngroups;
}
static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
return pctl->groups[group].name;
}
static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*pins = (unsigned *)&pctl->groups[group].pin;
*num_pins = 1;
return 0;
}
static const struct pinctrl_ops stm32_pctrl_ops = {
.dt_node_to_map = stm32_pctrl_dt_node_to_map,
.dt_free_map = pinctrl_utils_dt_free_map,
.get_groups_count = stm32_pctrl_get_groups_count,
.get_group_name = stm32_pctrl_get_group_name,
.get_group_pins = stm32_pctrl_get_group_pins,
};
/* Pinmux functions */
static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(stm32_gpio_functions);
}
static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
unsigned selector)
{
return stm32_gpio_functions[selector];
}
static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
unsigned function,
const char * const **groups,
unsigned * const num_groups)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*groups = pctl->grp_names;
*num_groups = pctl->ngroups;
return 0;
}
static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
int pin, u32 mode, u32 alt)
{
u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
unsigned long flags;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + alt_offset);
val &= ~GENMASK(alt_shift + 3, alt_shift);
val |= (alt << alt_shift);
writel_relaxed(val, bank->base + alt_offset);
val = readl_relaxed(bank->base + STM32_GPIO_MODER);
val &= ~GENMASK(pin * 2 + 1, pin * 2);
val |= mode << (pin * 2);
writel_relaxed(val, bank->base + STM32_GPIO_MODER);
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
bool ret;
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct stm32_pinctrl_group *g = pctl->groups + group;
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
u32 mode, alt;
int pin;
ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
if (!ret) {
dev_err(pctl->dev, "invalid function %d on group %d .\n",
function, group);
return -EINVAL;
}
range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
bank = gpio_range_to_bank(range);
pin = stm32_gpio_pin(g->pin);
mode = stm32_gpio_get_mode(function);
alt = stm32_gpio_get_alt(function);
stm32_pmx_set_mode(bank, pin, mode, alt);
return 0;
}
static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned gpio,
bool input)
{
struct stm32_gpio_bank *bank = gpio_range_to_bank(range);
int pin = stm32_gpio_pin(gpio);
stm32_pmx_set_mode(bank, pin, !input, 0);
return 0;
}
static const struct pinmux_ops stm32_pmx_ops = {
.get_functions_count = stm32_pmx_get_funcs_cnt,
.get_function_name = stm32_pmx_get_func_name,
.get_function_groups = stm32_pmx_get_func_groups,
.set_mux = stm32_pmx_set_mux,
.gpio_set_direction = stm32_pmx_gpio_set_direction,
};
/* Pinconf functions */
static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
unsigned offset, u32 drive)
{
unsigned long flags;
u32 val;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= ~BIT(offset);
val |= drive << offset;
writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
unsigned offset, u32 speed)
{
unsigned long flags;
u32 val;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= speed << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
unsigned offset, u32 bias)
{
unsigned long flags;
u32 val;
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= ~GENMASK(offset * 2 + 1, offset * 2);
val |= bias << (offset * 2);
writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
}
static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
unsigned int pin, enum pin_config_param param,
enum pin_config_param arg)
{
struct pinctrl_gpio_range *range;
struct stm32_gpio_bank *bank;
int offset, ret = 0;
range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
bank = gpio_range_to_bank(range);
offset = stm32_gpio_pin(pin);
switch (param) {
case PIN_CONFIG_DRIVE_PUSH_PULL:
stm32_pconf_set_driving(bank, offset, 0);
break;
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
stm32_pconf_set_driving(bank, offset, 1);
break;
case PIN_CONFIG_SLEW_RATE:
stm32_pconf_set_speed(bank, offset, arg);
break;
case PIN_CONFIG_BIAS_DISABLE:
stm32_pconf_set_bias(bank, offset, 0);
break;
case PIN_CONFIG_BIAS_PULL_UP:
stm32_pconf_set_bias(bank, offset, 1);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
stm32_pconf_set_bias(bank, offset, 2);
break;
case PIN_CONFIG_OUTPUT:
__stm32_gpio_set(bank, offset, arg);
ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
unsigned group,
unsigned long *config)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
*config = pctl->groups[group].config;
return 0;
}
static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long *configs, unsigned num_configs)
{
struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct stm32_pinctrl_group *g = &pctl->groups[group];
int i, ret;
for (i = 0; i < num_configs; i++) {
ret = stm32_pconf_parse_conf(pctldev, g->pin,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
if (ret < 0)
return ret;
g->config = configs[i];
}
return 0;
}
static const struct pinconf_ops stm32_pconf_ops = {
.pin_config_group_get = stm32_pconf_group_get,
.pin_config_group_set = stm32_pconf_group_set,
};
static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
struct device_node *np)
{
int bank_nr = pctl->nbanks;
struct stm32_gpio_bank *bank = &pctl->banks[bank_nr];
struct pinctrl_gpio_range *range = &bank->range;
struct device *dev = pctl->dev;
struct resource res;
struct reset_control *rstc;
int err, npins;
rstc = of_reset_control_get(np, NULL);
if (!IS_ERR(rstc))
reset_control_deassert(rstc);
if (of_address_to_resource(np, 0, &res))
return -ENODEV;
bank->base = devm_ioremap_resource(dev, &res);
if (IS_ERR(bank->base))
return PTR_ERR(bank->base);
bank->clk = of_clk_get_by_name(np, NULL);
if (IS_ERR(bank->clk)) {
dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
return PTR_ERR(bank->clk);
}
err = clk_prepare(bank->clk);
if (err) {
dev_err(dev, "failed to prepare clk (%d)\n", err);
return err;
}
npins = pctl->match_data->npins;
npins -= bank_nr * STM32_GPIO_PINS_PER_BANK;
if (npins < 0)
return -EINVAL;
else if (npins > STM32_GPIO_PINS_PER_BANK)
npins = STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip = stm32_gpio_template;
bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
bank->gpio_chip.ngpio = npins;
bank->gpio_chip.of_node = np;
bank->gpio_chip.parent = dev;
spin_lock_init(&bank->lock);
of_property_read_string(np, "st,bank-name", &range->name);
bank->gpio_chip.label = range->name;
range->id = bank_nr;
range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK;
range->npins = bank->gpio_chip.ngpio;
range->gc = &bank->gpio_chip;
err = gpiochip_add_data(&bank->gpio_chip, bank);
if (err) {
dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
return err;
}
dev_info(dev, "%s bank added\n", range->name);
return 0;
}
static int stm32_pctrl_build_state(struct platform_device *pdev)
{
struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
int i;
pctl->ngroups = pctl->match_data->npins;
/* Allocate groups */
pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->groups), GFP_KERNEL);
if (!pctl->groups)
return -ENOMEM;
/* We assume that one pin is one group, use pin name as group name. */
pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
sizeof(*pctl->grp_names), GFP_KERNEL);
if (!pctl->grp_names)
return -ENOMEM;
for (i = 0; i < pctl->match_data->npins; i++) {
const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
struct stm32_pinctrl_group *group = pctl->groups + i;
group->name = pin->pin.name;
group->pin = pin->pin.number;
pctl->grp_names[i] = pin->pin.name;
}
return 0;
}
int stm32_pctl_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
const struct of_device_id *match;
struct device *dev = &pdev->dev;
struct stm32_pinctrl *pctl;
struct pinctrl_pin_desc *pins;
int i, ret, banks = 0;
if (!np)
return -EINVAL;
match = of_match_device(dev->driver->of_match_table, dev);
if (!match || !match->data)
return -EINVAL;
if (!of_find_property(np, "pins-are-numbered", NULL)) {
dev_err(dev, "only support pins-are-numbered format\n");
return -EINVAL;
}
pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
if (!pctl)
return -ENOMEM;
platform_set_drvdata(pdev, pctl);
pctl->dev = dev;
pctl->match_data = match->data;
ret = stm32_pctrl_build_state(pdev);
if (ret) {
dev_err(dev, "build state failed: %d\n", ret);
return -EINVAL;
}
for_each_child_of_node(np, child)
if (of_property_read_bool(child, "gpio-controller"))
banks++;
if (!banks) {
dev_err(dev, "at least one GPIO bank is required\n");
return -EINVAL;
}
pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
GFP_KERNEL);
if (!pctl->banks)
return -ENOMEM;
for_each_child_of_node(np, child) {
if (of_property_read_bool(child, "gpio-controller")) {
ret = stm32_gpiolib_register_bank(pctl, child);
if (ret)
return ret;
pctl->nbanks++;
}
}
pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (i = 0; i < pctl->match_data->npins; i++)
pins[i] = pctl->match_data->pins[i].pin;
pctl->pctl_desc.name = dev_name(&pdev->dev);
pctl->pctl_desc.owner = THIS_MODULE;
pctl->pctl_desc.pins = pins;
pctl->pctl_desc.npins = pctl->match_data->npins;
pctl->pctl_desc.confops = &stm32_pconf_ops;
pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
pctl->pctl_desc.pmxops = &stm32_pmx_ops;
pctl->dev = &pdev->dev;
pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
if (!pctl->pctl_dev) {
dev_err(&pdev->dev, "Failed pinctrl registration\n");
return -EINVAL;
}
for (i = 0; i < pctl->nbanks; i++)
pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range);
dev_info(dev, "Pinctrl STM32 initialized\n");
return 0;
}

51
drivers/pinctrl/stm32/pinctrl-stm32.h Normal file
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@ -0,0 +1,51 @@
/*
* Copyright (C) Maxime Coquelin 2015
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef __PINCTRL_STM32_H
#define __PINCTRL_STM32_H
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>
#define STM32_PIN_NO(x) ((x) << 8)
#define STM32_GET_PIN_NO(x) ((x) >> 8)
#define STM32_GET_PIN_FUNC(x) ((x) & 0xff)
#define STM32_PIN_GPIO 0
#define STM32_PIN_AF(x) ((x) + 1)
#define STM32_PIN_ANALOG (STM32_PIN_AF(15) + 1)
struct stm32_desc_function {
const char *name;
const unsigned char num;
};
struct stm32_desc_pin {
struct pinctrl_pin_desc pin;
const struct stm32_desc_function *functions;
};
#define STM32_PIN(_pin, ...) \
{ \
.pin = _pin, \
.functions = (struct stm32_desc_function[]){ \
__VA_ARGS__, { } }, \
}
#define STM32_FUNCTION(_num, _name) \
{ \
.num = _num, \
.name = _name, \
}
struct stm32_pinctrl_match_data {
const struct stm32_desc_pin *pins;
const unsigned int npins;
};
int stm32_pctl_probe(struct platform_device *pdev);
#endif /* __PINCTRL_STM32_H */

1591
drivers/pinctrl/stm32/pinctrl-stm32f429.c Normal file
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File diff suppressed because it is too large Load Diff

36
drivers/pinctrl/sunxi/Kconfig
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@ -1,67 +1,75 @@
if ARCH_SUNXI
config PINCTRL_SUNXI_COMMON
config PINCTRL_SUNXI
bool
select PINMUX
select GENERIC_PINCONF
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN5I_A10S
def_bool MACH_SUN5I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN5I_A13
def_bool MACH_SUN5I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31S
def_bool MACH_SUN6I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN6I_A31_R
def_bool MACH_SUN6I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN7I_A20
def_bool MACH_SUN7I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A33
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A83T
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3
def_bool MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN8I_H3_R
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
config PINCTRL_SUN9I_A80
def_bool MACH_SUN9I
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN9I_A80_R
def_bool MACH_SUN9I
depends on RESET_CONTROLLER
select PINCTRL_SUNXI_COMMON
select PINCTRL_SUNXI
config PINCTRL_SUN50I_A64
bool
select PINCTRL_SUNXI
endif

4
drivers/pinctrl/sunxi/Makefile
View File

@ -1,5 +1,5 @@
# Core
obj-$(CONFIG_PINCTRL_SUNXI_COMMON) += pinctrl-sunxi.o
obj-y += pinctrl-sunxi.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
@ -12,7 +12,9 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o

601
drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c Normal file
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@ -0,0 +1,601 @@
/*
* Allwinner A64 SoCs pinctrl driver.
*
* Copyright (C) 2016 - ARM Ltd.
* Author: Andre Przywara <andre.przywara@arm.com>
*
* Based on pinctrl-sun7i-a20.c, which is:
* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin a64_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* TX */
SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RX */
SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */
SUNXI_FUNCTION(0x5, "sim"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
SUNXI_FUNCTION(0x5, "sim"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */
SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */
SUNXI_FUNCTION(0x5, "sim"), /* RST */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif2"), /* DIN */
SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */
SUNXI_FUNCTION(0x5, "sim"), /* DET */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "uart0"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "uart0"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
SUNXI_FUNCTION(0x4, "spi0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
SUNXI_FUNCTION(0x4, "spi0")), /* CS */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
SUNXI_FUNCTION(0x3, "uart3"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
SUNXI_FUNCTION(0x5, "ccir")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
SUNXI_FUNCTION(0x3, "uart3"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
SUNXI_FUNCTION(0x5, "ccir")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
SUNXI_FUNCTION(0x3, "uart4"), /* TX */
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
SUNXI_FUNCTION(0x3, "uart4"), /* RX */
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
SUNXI_FUNCTION(0x5, "ccir")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
SUNXI_FUNCTION(0x5, "ccir")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
SUNXI_FUNCTION(0x5, "ccir")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
SUNXI_FUNCTION(0x5, "ccir")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */
SUNXI_FUNCTION(0x5, "ccir")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */
SUNXI_FUNCTION(0x5, "ccir")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
SUNXI_FUNCTION(0x4, "emac")), /* ENULL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x5, "ccir")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x5, "ccir")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
SUNXI_FUNCTION(0x4, "emac")), /* EMDC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* PCK */
SUNXI_FUNCTION(0x4, "ts0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* CK */
SUNXI_FUNCTION(0x4, "ts0")), /* ERR */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */
SUNXI_FUNCTION(0x4, "ts0")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */
SUNXI_FUNCTION(0x4, "ts0")), /* DVLD */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D0 */
SUNXI_FUNCTION(0x4, "ts0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D1 */
SUNXI_FUNCTION(0x4, "ts0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D2 */
SUNXI_FUNCTION(0x4, "ts0")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D3 */
SUNXI_FUNCTION(0x4, "ts0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D4 */
SUNXI_FUNCTION(0x4, "ts0")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D5 */
SUNXI_FUNCTION(0x4, "ts0")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D6 */
SUNXI_FUNCTION(0x4, "ts0")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0"), /* D7 */
SUNXI_FUNCTION(0x4, "ts0")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "csi0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
SUNXI_FUNCTION(0x3, "jtag")), /* MSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out")),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */
SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */
SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */
SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "aif3"), /* DIN */
SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mic"), /* CLK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "mic"), /* DATA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
};
static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
.pins = a64_pins,
.npins = ARRAY_SIZE(a64_pins),
.irq_banks = 3,
};
static int a64_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&a64_pinctrl_data);
}
static const struct of_device_id a64_pinctrl_match[] = {
{ .compatible = "allwinner,sun50i-a64-pinctrl", },
{}
};
static struct platform_driver a64_pinctrl_driver = {
.probe = a64_pinctrl_probe,
.driver = {
.name = "sun50i-a64-pinctrl",
.of_match_table = a64_pinctrl_match,
},
};
builtin_platform_driver(a64_pinctrl_driver);

32
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
View File

@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -960,65 +956,65 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),

106
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c Normal file
View File

@ -0,0 +1,106 @@
/*
* Allwinner H3 SoCs pinctrl driver.
*
* Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_pwm"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_cir_rx"),
SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
};
static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
.pins = sun8i_h3_r_pins,
.npins = ARRAY_SIZE(sun8i_h3_r_pins),
.irq_banks = 1,
.pin_base = PL_BASE,
.irq_read_needs_mux = true
};
static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
{
return sunxi_pinctrl_init(pdev,
&sun8i_h3_r_pinctrl_data);
}
static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
{}
};
static struct platform_driver sun8i_h3_r_pinctrl_driver = {
.probe = sun8i_h3_r_pinctrl_probe,
.driver = {
.name = "sun8i-h3-r-pinctrl",
.of_match_table = sun8i_h3_r_pinctrl_match,
},
};
builtin_platform_driver(sun8i_h3_r_pinctrl_driver);

9
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
View File

@ -9,7 +9,7 @@
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@ -164,7 +164,6 @@ static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
{}
};
MODULE_DEVICE_TABLE(of, sun9i_a80_r_pinctrl_match);
static struct platform_driver sun9i_a80_r_pinctrl_driver = {
.probe = sun9i_a80_r_pinctrl_probe,
@ -174,8 +173,4 @@ static struct platform_driver sun9i_a80_r_pinctrl_driver = {
.of_match_table = sun9i_a80_r_pinctrl_match,
},
};
module_platform_driver(sun9i_a80_r_pinctrl_driver);
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
MODULE_DESCRIPTION("Allwinner A80 R_PIO pinctrl driver");
MODULE_LICENSE("GPL");
builtin_platform_driver(sun9i_a80_r_pinctrl_driver);

7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -15,7 +15,7 @@
#include <linux/gpio/driver.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
@ -459,15 +459,16 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
u8 index = sunxi_data_offset(offset);
u32 set_mux = pctl->desc->irq_read_needs_mux &&
test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
u32 pin = offset + chip->base;
u32 val;
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
if (set_mux)
sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
return !!val;
}

30
drivers/pinctrl/tegra/Kconfig Normal file
View File

@ -0,0 +1,30 @@
config PINCTRL_TEGRA
bool
select PINMUX
select PINCONF
config PINCTRL_TEGRA20
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA30
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA114
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA124
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA210
bool
select PINCTRL_TEGRA
config PINCTRL_TEGRA_XUSB
def_bool y if ARCH_TEGRA
select GENERIC_PHY
select PINCONF
select PINMUX

7
drivers/pinctrl/tegra/Makefile Normal file
View File

@ -0,0 +1,7 @@
obj-y += pinctrl-tegra.o
obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o

4
drivers/pinctrl/pinctrl-tegra-xusb.c → drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
View File

@ -24,8 +24,8 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include "core.h"
#include "pinctrl-utils.h"
#include "../core.h"
#include "../pinctrl-utils.h"
#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)

4
drivers/pinctrl/pinctrl-tegra.c → drivers/pinctrl/tegra/pinctrl-tegra.c
View File

@ -30,9 +30,9 @@
#include <linux/pinctrl/pinconf.h>
#include <linux/slab.h>
#include "core.h"
#include "../core.h"
#include "../pinctrl-utils.h"
#include "pinctrl-tegra.h"
#include "pinctrl-utils.h"
struct tegra_pmx {
struct device *dev;

0
drivers/pinctrl/pinctrl-tegra.h → drivers/pinctrl/tegra/pinctrl-tegra.h
View File

0
drivers/pinctrl/pinctrl-tegra114.c → drivers/pinctrl/tegra/pinctrl-tegra114.c
View File

0
drivers/pinctrl/pinctrl-tegra124.c → drivers/pinctrl/tegra/pinctrl-tegra124.c
View File

0
drivers/pinctrl/pinctrl-tegra20.c → drivers/pinctrl/tegra/pinctrl-tegra20.c
View File

0
drivers/pinctrl/pinctrl-tegra210.c → drivers/pinctrl/tegra/pinctrl-tegra210.c
View File

0
drivers/pinctrl/pinctrl-tegra30.c → drivers/pinctrl/tegra/pinctrl-tegra30.c
View File

14
drivers/pinctrl/uniphier/Kconfig
View File

@ -1,6 +1,6 @@
menuconfig PINCTRL_UNIPHIER
bool "UniPhier SoC pinctrl drivers"
depends on ARCH_UNIPHIER
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && MFD_SYSCON
default y
select PINMUX
@ -8,27 +8,27 @@ menuconfig PINCTRL_UNIPHIER
if PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_PH1_LD4
config PINCTRL_UNIPHIER_LD4
tristate "UniPhier PH1-LD4 SoC pinctrl driver"
default y
config PINCTRL_UNIPHIER_PH1_PRO4
config PINCTRL_UNIPHIER_PRO4
tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
default y
config PINCTRL_UNIPHIER_PH1_SLD8
config PINCTRL_UNIPHIER_SLD8
tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
default y
config PINCTRL_UNIPHIER_PH1_PRO5
config PINCTRL_UNIPHIER_PRO5
tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
default y
config PINCTRL_UNIPHIER_PROXSTREAM2
config PINCTRL_UNIPHIER_PXS2
tristate "UniPhier ProXstream2 SoC pinctrl driver"
default y
config PINCTRL_UNIPHIER_PH1_LD6B
config PINCTRL_UNIPHIER_LD6B
tristate "UniPhier PH1-LD6b SoC pinctrl driver"
default y

14
drivers/pinctrl/uniphier/Makefile
View File

@ -1,8 +1,8 @@
obj-y += pinctrl-uniphier-core.o
obj-y += pinctrl-uniphier-core.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o

0
drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c → drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
View File

0
drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c → drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
View File

0
drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c → drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
View File

0
drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c → drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
View File

0
drivers/pinctrl/uniphier/pinctrl-proxstream2.c → drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
View File

0
drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c → drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
View File

520
include/dt-bindings/pinctrl/mt7623-pinfunc.h Normal file
View File

@ -0,0 +1,520 @@
#ifndef __DTS_MT7623_PINFUNC_H
#define __DTS_MT7623_PINFUNC_H
#include <dt-bindings/pinctrl/mt65xx.h>
#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
#define MT7623_PIN_0_PWRAP_SPI0_MI_FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
#define MT7623_PIN_1_PWRAP_SPI0_MO_FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
#define MT7623_PIN_2_PWRAP_INT_FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
#define MT7623_PIN_2_PWRAP_INT_FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
#define MT7623_PIN_3_PWRAP_SPI0_CK_FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
#define MT7623_PIN_4_PWRAP_SPI0_CSN_FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
#define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
#define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
#define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
#define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
#define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
#define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
#define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
#define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
#define MT7623_PIN_11_WATCHDOG_FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
#define MT7623_PIN_11_WATCHDOG_FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
#define MT7623_PIN_12_SRCLKENA_FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
#define MT7623_PIN_12_SRCLKENA_FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
#define MT7623_PIN_13_SRCLKENAI_FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
#define MT7623_PIN_13_SRCLKENAI_FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
#define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
#define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1)
#define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
#define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
#define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
#define MT7623_PIN_15_GPIO15_FUNC_URXD2 (MTK_PIN_NO(15) | 2)
#define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
#define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
#define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6)
#define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
#define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
#define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6)
#define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
#define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
#define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
#define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6)
#define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
#define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
#define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
#define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6)
#define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
#define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
#define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2)
#define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
#define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1)
#define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2)
#define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
#define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
#define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2)
#define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
#define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1)
#define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
#define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
#define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
#define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
#define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1)
#define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
#define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
#define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
#define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
#define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
#define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1)
#define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
#define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6)
#define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
#define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
#define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6)
#define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
#define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
#define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
#define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
#define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6)
#define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
#define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
#define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
#define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1)
#define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
#define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1)
#define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
#define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1)
#define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
#define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1)
#define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
#define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1)
#define MT7623_PIN_43_NCLE_FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
#define MT7623_PIN_44_NCEB1_FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
#define MT7623_PIN_44_NCEB1_FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
#define MT7623_PIN_44_NCEB1_FUNC_IDDIG (MTK_PIN_NO(44) | 2)
#define MT7623_PIN_45_NCEB0_FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
#define MT7623_PIN_45_NCEB0_FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
#define MT7623_PIN_45_NCEB0_FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
#define MT7623_PIN_46_IR_FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
#define MT7623_PIN_46_IR_FUNC_IR (MTK_PIN_NO(46) | 1)
#define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
#define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1)
#define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
#define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1)
#define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
#define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
#define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6)
#define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
#define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
#define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5)
#define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
#define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
#define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
#define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
#define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
#define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5)
#define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
#define MT7623_PIN_61_GPIO61_FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
#define MT7623_PIN_61_GPIO61_FUNC_TEST_FD (MTK_PIN_NO(61) | 1)
#define MT7623_PIN_62_GPIO62_FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
#define MT7623_PIN_62_GPIO62_FUNC_TEST_FC (MTK_PIN_NO(62) | 1)
#define MT7623_PIN_63_WB_SCLK_FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
#define MT7623_PIN_63_WB_SCLK_FUNC_WB_SCLK (MTK_PIN_NO(63) | 1)
#define MT7623_PIN_64_WB_SDATA_FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
#define MT7623_PIN_64_WB_SDATA_FUNC_WB_SDATA (MTK_PIN_NO(64) | 1)
#define MT7623_PIN_65_WB_SEN_FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
#define MT7623_PIN_65_WB_SEN_FUNC_WB_SEN (MTK_PIN_NO(65) | 1)
#define MT7623_PIN_66_WB_CRTL0_FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
#define MT7623_PIN_66_WB_CRTL0_FUNC_WB_CRTL0 (MTK_PIN_NO(66) | 1)
#define MT7623_PIN_67_WB_CRTL1_FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
#define MT7623_PIN_67_WB_CRTL1_FUNC_WB_CRTL1 (MTK_PIN_NO(67) | 1)
#define MT7623_PIN_68_WB_CRTL2_FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
#define MT7623_PIN_68_WB_CRTL2_FUNC_WB_CRTL2 (MTK_PIN_NO(68) | 1)
#define MT7623_PIN_69_WB_CRTL3_FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
#define MT7623_PIN_69_WB_CRTL3_FUNC_WB_CRTL3 (MTK_PIN_NO(69) | 1)
#define MT7623_PIN_70_WB_CRTL4_FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
#define MT7623_PIN_70_WB_CRTL4_FUNC_WB_CRTL4 (MTK_PIN_NO(70) | 1)
#define MT7623_PIN_71_WB_CRTL5_FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
#define MT7623_PIN_71_WB_CRTL5_FUNC_WB_CRTL5 (MTK_PIN_NO(71) | 1)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_PWM0 (MTK_PIN_NO(72) | 4)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
#define MT7623_PIN_72_I2S0_DATA_IN_FUNC_AP_I2S_DI (MTK_PIN_NO(72) | 6)
#define MT7623_PIN_73_I2S0_LRCK_FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
#define MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
#define MT7623_PIN_73_I2S0_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
#define MT7623_PIN_73_I2S0_LRCK_FUNC_AP_I2S_LRCK (MTK_PIN_NO(73) | 6)
#define MT7623_PIN_74_I2S0_BCK_FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
#define MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
#define MT7623_PIN_74_I2S0_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
#define MT7623_PIN_74_I2S0_BCK_FUNC_AP_I2S_BCK (MTK_PIN_NO(74) | 6)
#define MT7623_PIN_75_SDA0_FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
#define MT7623_PIN_75_SDA0_FUNC_SDA0 (MTK_PIN_NO(75) | 1)
#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
#define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
#define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
#define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
#define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)
#define MT7623_PIN_96_MIPI_TCP_FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
#define MT7623_PIN_96_MIPI_TCP_FUNC_TCP (MTK_PIN_NO(96) | 1)
#define MT7623_PIN_97_MIPI_TDN1_FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
#define MT7623_PIN_97_MIPI_TDN1_FUNC_TDN1 (MTK_PIN_NO(97) | 1)
#define MT7623_PIN_98_MIPI_TDP1_FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
#define MT7623_PIN_98_MIPI_TDP1_FUNC_TDP1 (MTK_PIN_NO(98) | 1)
#define MT7623_PIN_99_MIPI_TDN0_FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
#define MT7623_PIN_99_MIPI_TDN0_FUNC_TDN0 (MTK_PIN_NO(99) | 1)
#define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
#define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3)
#define MT7623_PIN_105_MSDC1_CMD_FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
#define MT7623_PIN_106_MSDC1_CLK_FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
#define MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
#define MT7623_PIN_106_MSDC1_CLK_FUNC_SCL1 (MTK_PIN_NO(106) | 3)
#define MT7623_PIN_106_MSDC1_CLK_FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
#define MT7623_PIN_107_MSDC1_DAT0_FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
#define MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
#define MT7623_PIN_107_MSDC1_DAT0_FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
#define MT7623_PIN_107_MSDC1_DAT0_FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
#define MT7623_PIN_108_MSDC1_DAT1_FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
#define MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM0 (MTK_PIN_NO(108) | 3)
#define MT7623_PIN_108_MSDC1_DAT1_FUNC_URXD0 (MTK_PIN_NO(108) | 5)
#define MT7623_PIN_108_MSDC1_DAT1_FUNC_PWM1 (MTK_PIN_NO(108) | 6)
#define MT7623_PIN_109_MSDC1_DAT2_FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
#define MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
#define MT7623_PIN_109_MSDC1_DAT2_FUNC_SDA2 (MTK_PIN_NO(109) | 3)
#define MT7623_PIN_109_MSDC1_DAT2_FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
#define MT7623_PIN_109_MSDC1_DAT2_FUNC_PWM2 (MTK_PIN_NO(109) | 6)
#define MT7623_PIN_110_MSDC1_DAT3_FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
#define MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
#define MT7623_PIN_110_MSDC1_DAT3_FUNC_SCL2 (MTK_PIN_NO(110) | 3)
#define MT7623_PIN_110_MSDC1_DAT3_FUNC_URXD1 (MTK_PIN_NO(110) | 5)
#define MT7623_PIN_110_MSDC1_DAT3_FUNC_PWM3 (MTK_PIN_NO(110) | 6)
#define MT7623_PIN_111_MSDC0_DAT7_FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
#define MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
#define MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7 (MTK_PIN_NO(111) | 4)
#define MT7623_PIN_112_MSDC0_DAT6_FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
#define MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
#define MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6 (MTK_PIN_NO(112) | 4)
#define MT7623_PIN_113_MSDC0_DAT5_FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
#define MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
#define MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5 (MTK_PIN_NO(113) | 4)
#define MT7623_PIN_114_MSDC0_DAT4_FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
#define MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
#define MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4 (MTK_PIN_NO(114) | 4)
#define MT7623_PIN_115_MSDC0_RSTB_FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
#define MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
#define MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8 (MTK_PIN_NO(115) | 4)
#define MT7623_PIN_116_MSDC0_CMD_FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
#define MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
#define MT7623_PIN_116_MSDC0_CMD_FUNC_NALE (MTK_PIN_NO(116) | 4)
#define MT7623_PIN_117_MSDC0_CLK_FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
#define MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
#define MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB (MTK_PIN_NO(117) | 4)
#define MT7623_PIN_118_MSDC0_DAT3_FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
#define MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
#define MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3 (MTK_PIN_NO(118) | 4)
#define MT7623_PIN_119_MSDC0_DAT2_FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
#define MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
#define MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2 (MTK_PIN_NO(119) | 4)
#define MT7623_PIN_120_MSDC0_DAT1_FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
#define MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
#define MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1 (MTK_PIN_NO(120) | 4)
#define MT7623_PIN_121_MSDC0_DAT0_FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
#define MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
#define MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0 (MTK_PIN_NO(121) | 4)
#define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
#define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1)
#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
#define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4)
#define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5)
#define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1)
#define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4)
#define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5)
#define MT7623_PIN_126_I2S0_MCLK_FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
#define MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
#define MT7623_PIN_126_I2S0_MCLK_FUNC_AP_I2S_MCLK (MTK_PIN_NO(126) | 6)
#define MT7623_PIN_199_SPI1_CK_FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
#define MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
#define MT7623_PIN_200_URXD2_FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
#define MT7623_PIN_200_URXD2_FUNC_URXD2 (MTK_PIN_NO(200) | 6)
#define MT7623_PIN_201_UTXD2_FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
#define MT7623_PIN_201_UTXD2_FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
#define MT7623_PIN_203_PWM0_FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
#define MT7623_PIN_203_PWM0_FUNC_PWM0 (MTK_PIN_NO(203) | 1)
#define MT7623_PIN_203_PWM0_FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
#define MT7623_PIN_204_PWM1_FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
#define MT7623_PIN_204_PWM1_FUNC_PWM1 (MTK_PIN_NO(204) | 1)
#define MT7623_PIN_205_PWM2_FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
#define MT7623_PIN_205_PWM2_FUNC_PWM2 (MTK_PIN_NO(205) | 1)
#define MT7623_PIN_206_PWM3_FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
#define MT7623_PIN_206_PWM3_FUNC_PWM3 (MTK_PIN_NO(206) | 1)
#define MT7623_PIN_207_PWM4_FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
#define MT7623_PIN_207_PWM4_FUNC_PWM4 (MTK_PIN_NO(207) | 1)
#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PWM0 (MTK_PIN_NO(208) | 2)
#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 3)
#define MT7623_PIN_208_AUD_EXT_CK1_FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 3)
#define MT7623_PIN_209_AUD_EXT_CK2_FUNC_PWM1 (MTK_PIN_NO(209) | 5)
#define MT7623_PIN_236_EXT_SDIO3_FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
#define MT7623_PIN_236_EXT_SDIO3_FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
#define MT7623_PIN_236_EXT_SDIO3_FUNC_IDDIG (MTK_PIN_NO(236) | 2)
#define MT7623_PIN_237_EXT_SDIO2_FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
#define MT7623_PIN_237_EXT_SDIO2_FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
#define MT7623_PIN_237_EXT_SDIO2_FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
#define MT7623_PIN_238_EXT_SDIO1_FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
#define MT7623_PIN_238_EXT_SDIO1_FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
#define MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
#define MT7623_PIN_239_EXT_SDIO0_FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
#define MT7623_PIN_240_EXT_XCS_FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
#define MT7623_PIN_240_EXT_XCS_FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
#define MT7623_PIN_241_EXT_SCK_FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
#define MT7623_PIN_241_EXT_SCK_FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
#define MT7623_PIN_242_URTS2_FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
#define MT7623_PIN_242_URTS2_FUNC_URTS2 (MTK_PIN_NO(242) | 1)
#define MT7623_PIN_242_URTS2_FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
#define MT7623_PIN_242_URTS2_FUNC_URXD3 (MTK_PIN_NO(242) | 3)
#define MT7623_PIN_242_URTS2_FUNC_SCL1 (MTK_PIN_NO(242) | 4)
#define MT7623_PIN_243_UCTS2_FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
#define MT7623_PIN_243_UCTS2_FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
#define MT7623_PIN_243_UCTS2_FUNC_URXD3 (MTK_PIN_NO(243) | 2)
#define MT7623_PIN_243_UCTS2_FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
#define MT7623_PIN_243_UCTS2_FUNC_SDA1 (MTK_PIN_NO(243) | 4)
#define MT7623_PIN_250_GPIO250_FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
#define MT7623_PIN_250_GPIO250_FUNC_TEST_MD7 (MTK_PIN_NO(250) | 1)
#define MT7623_PIN_250_GPIO250_FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 6)
#define MT7623_PIN_251_GPIO251_FUNC_GPIO251 (MTK_PIN_NO(251) | 0)
#define MT7623_PIN_251_GPIO251_FUNC_TEST_MD6 (MTK_PIN_NO(251) | 1)
#define MT7623_PIN_251_GPIO251_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 6)
#define MT7623_PIN_252_GPIO252_FUNC_GPIO252 (MTK_PIN_NO(252) | 0)
#define MT7623_PIN_252_GPIO252_FUNC_TEST_MD5 (MTK_PIN_NO(252) | 1)
#define MT7623_PIN_252_GPIO252_FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 6)
#define MT7623_PIN_253_GPIO253_FUNC_GPIO253 (MTK_PIN_NO(253) | 0)
#define MT7623_PIN_253_GPIO253_FUNC_TEST_MD4 (MTK_PIN_NO(253) | 1)
#define MT7623_PIN_253_GPIO253_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 6)
#define MT7623_PIN_254_GPIO254_FUNC_GPIO254 (MTK_PIN_NO(254) | 0)
#define MT7623_PIN_254_GPIO254_FUNC_TEST_MD3 (MTK_PIN_NO(254) | 1)
#define MT7623_PIN_254_GPIO254_FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 6)
#define MT7623_PIN_255_GPIO255_FUNC_GPIO255 (MTK_PIN_NO(255) | 0)
#define MT7623_PIN_255_GPIO255_FUNC_TEST_MD2 (MTK_PIN_NO(255) | 1)
#define MT7623_PIN_255_GPIO255_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 6)
#define MT7623_PIN_256_GPIO256_FUNC_GPIO256 (MTK_PIN_NO(256) | 0)
#define MT7623_PIN_256_GPIO256_FUNC_TEST_MD1 (MTK_PIN_NO(256) | 1)
#define MT7623_PIN_257_GPIO257_FUNC_GPIO257 (MTK_PIN_NO(257) | 0)
#define MT7623_PIN_257_GPIO257_FUNC_TEST_MD0 (MTK_PIN_NO(257) | 1)
#define MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
#define MT7623_PIN_261_MSDC1_INS_FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
#define MT7623_PIN_262_G2_TXEN_FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
#define MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
#define MT7623_PIN_263_G2_TXD3_FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
#define MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
#define MT7623_PIN_264_G2_TXD2_FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
#define MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
#define MT7623_PIN_265_G2_TXD1_FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
#define MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
#define MT7623_PIN_266_G2_TXD0_FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
#define MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
#define MT7623_PIN_267_G2_TXCLK_FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
#define MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
#define MT7623_PIN_268_G2_RXCLK_FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
#define MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
#define MT7623_PIN_269_G2_RXD0_FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
#define MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
#define MT7623_PIN_270_G2_RXD1_FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
#define MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
#define MT7623_PIN_271_G2_RXD2_FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
#define MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
#define MT7623_PIN_272_G2_RXD3_FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
#define MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
#define MT7623_PIN_274_G2_RXDV_FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
#define MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
#define MT7623_PIN_275_G2_MDC_FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
#define MT7623_PIN_275_G2_MDC_FUNC_MDC (MTK_PIN_NO(275) | 1)
#define MT7623_PIN_276_G2_MDIO_FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
#define MT7623_PIN_276_G2_MDIO_FUNC_MDIO (MTK_PIN_NO(276) | 1)
#define MT7623_PIN_278_JTAG_RESET_FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
#define MT7623_PIN_278_JTAG_RESET_FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
#endif /* __DTS_MT7623_PINFUNC_H */