drivers/edac: provide support for tile architecture
Add tile support for the EDAC driver, which provides unified system error (memory, PCI, etc.) reporting. For now, the TILEPro port reports memory correctable error (CE) only. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
d91c641233
commit
5c77075548
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@ -6082,6 +6082,7 @@ S: Supported
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F: arch/tile/
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F: drivers/char/hvc_tile.c
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F: drivers/net/tile/
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F: drivers/edac/tile_edac.c
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TLAN NETWORK DRIVER
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M: Samuel Chessman <chessman@tux.org>
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@ -0,0 +1,29 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_EDAC_H
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#define _ASM_TILE_EDAC_H
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/* ECC atomic, DMA, SMP and interrupt safe scrub function */
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static inline void atomic_scrub(void *va, u32 size)
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{
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/*
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* These is nothing to be done here because CE is
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* corrected by the mshim.
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*/
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return;
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}
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#endif /* _ASM_TILE_EDAC_H */
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@ -0,0 +1,50 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/**
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* @file drv_mshim_intf.h
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* Interface definitions for the Linux EDAC memory controller driver.
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*/
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#ifndef _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
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#define _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H
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/** Number of memory controllers in the public API. */
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#define TILE_MAX_MSHIMS 4
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/** Memory info under each memory controller. */
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struct mshim_mem_info
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{
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uint64_t mem_size; /**< Total memory size in bytes. */
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uint8_t mem_type; /**< Memory type, DDR2 or DDR3. */
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uint8_t mem_ecc; /**< Memory supports ECC. */
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};
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/**
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* DIMM error structure.
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* For now, only correctable errors are counted and the mshim doesn't record
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* the error PA. HV takes panic upon uncorrectable errors.
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*/
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struct mshim_mem_error
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{
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uint32_t sbe_count; /**< Number of single-bit errors. */
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};
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/** Read this offset to get the memory info per mshim. */
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#define MSHIM_MEM_INFO_OFF 0x100
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/** Read this offset to check DIMM error. */
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#define MSHIM_MEM_ERROR_OFF 0x200
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#endif /* _SYS_HV_INCLUDE_DRV_MSHIM_INTF_H */
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@ -338,9 +338,10 @@ typedef int HV_Errno;
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#define HV_ENOTREADY -812 /**< Device not ready */
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#define HV_EIO -813 /**< I/O error */
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#define HV_ENOMEM -814 /**< Out of memory */
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#define HV_EAGAIN -815 /**< Try again */
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#define HV_ERR_MAX -801 /**< Largest HV error code */
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#define HV_ERR_MIN -814 /**< Smallest HV error code */
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#define HV_ERR_MIN -815 /**< Smallest HV error code */
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#ifndef __ASSEMBLER__
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@ -867,6 +868,43 @@ typedef struct
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*/
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HV_PhysAddrRange hv_inquire_physical(int idx);
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/** Possible DIMM types. */
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typedef enum
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{
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NO_DIMM = 0, /**< No DIMM */
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DDR2 = 1, /**< DDR2 */
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DDR3 = 2 /**< DDR3 */
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} HV_DIMM_Type;
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#ifdef __tilegx__
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/** Log2 of minimum DIMM bytes supported by the memory controller. */
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#define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
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/** Max number of DIMMs contained by one memory controller. */
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#define HV_MSH_MAX_DIMMS 8
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#else
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/** Log2 of minimum DIMM bytes supported by the memory controller. */
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#define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
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/** Max number of DIMMs contained by one memory controller. */
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#define HV_MSH_MAX_DIMMS 2
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#endif
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/** Number of bits to right-shift to get the DIMM type. */
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#define HV_DIMM_TYPE_SHIFT 0
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/** Bits to mask to get the DIMM type. */
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#define HV_DIMM_TYPE_MASK 0xf
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/** Number of bits to right-shift to get the DIMM size. */
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#define HV_DIMM_SIZE_SHIFT 4
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/** Bits to mask to get the DIMM size. */
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#define HV_DIMM_SIZE_MASK 0xf
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/** Memory controller information. */
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typedef struct
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@ -1043,6 +1081,7 @@ int hv_console_write(HV_VirtAddr bytes, int len);
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* downcall:
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*
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* INT_MESSAGE_RCV_DWNCL (hypervisor message available)
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* INT_DEV_INTR_DWNCL (device interrupt)
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* INT_DMATLB_MISS_DWNCL (DMA TLB miss)
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* INT_SNITLB_MISS_DWNCL (SNI TLB miss)
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* INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
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@ -7,7 +7,7 @@
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM
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depends on X86 || PPC
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depends on X86 || PPC || TILE
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help
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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@ -282,4 +282,12 @@ config EDAC_CPC925
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a companion chip to the PowerPC 970 family of
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processors.
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config EDAC_TILE
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tristate "Tilera Memory Controller"
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depends on EDAC_MM_EDAC && TILE
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default y
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help
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Support for error detection and correction on the
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Tilera memory controller.
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endif # EDAC
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@ -54,3 +54,4 @@ obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
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obj-$(CONFIG_EDAC_AMD8111) += amd8111_edac.o
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obj-$(CONFIG_EDAC_AMD8131) += amd8131_edac.o
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obj-$(CONFIG_EDAC_TILE) += tile_edac.o
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@ -0,0 +1,254 @@
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/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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* Tilera-specific EDAC driver.
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*
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* This source code is derived from the following driver:
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*
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* Cell MIC driver for ECC counting
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*
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* Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
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* <benh@kernel.crashing.org>
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/edac.h>
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#include <hv/hypervisor.h>
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#include <hv/drv_mshim_intf.h>
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#include "edac_core.h"
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#define DRV_NAME "tile-edac"
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/* Number of cs_rows needed per memory controller on TILEPro. */
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#define TILE_EDAC_NR_CSROWS 1
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/* Number of channels per memory controller on TILEPro. */
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#define TILE_EDAC_NR_CHANS 1
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/* Granularity of reported error in bytes on TILEPro. */
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#define TILE_EDAC_ERROR_GRAIN 8
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/* TILE processor has multiple independent memory controllers. */
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struct platform_device *mshim_pdev[TILE_MAX_MSHIMS];
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struct tile_edac_priv {
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int hv_devhdl; /* Hypervisor device handle. */
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int node; /* Memory controller instance #. */
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unsigned int ce_count; /*
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* Correctable-error counter
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* kept by the driver.
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*/
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};
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static void tile_edac_check(struct mem_ctl_info *mci)
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{
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struct tile_edac_priv *priv = mci->pvt_info;
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struct mshim_mem_error mem_error;
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if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error,
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sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) !=
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sizeof(struct mshim_mem_error)) {
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pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure.\n");
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return;
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}
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/* Check if the current error count is different from the saved one. */
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if (mem_error.sbe_count != priv->ce_count) {
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dev_dbg(mci->dev, "ECC CE err on node %d\n", priv->node);
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priv->ce_count = mem_error.sbe_count;
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edac_mc_handle_ce(mci, 0, 0, 0, 0, 0, mci->ctl_name);
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}
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}
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/*
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* Initialize the 'csrows' table within the mci control structure with the
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* addressing of memory.
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*/
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static int __devinit tile_edac_init_csrows(struct mem_ctl_info *mci)
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{
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struct csrow_info *csrow = &mci->csrows[0];
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struct tile_edac_priv *priv = mci->pvt_info;
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struct mshim_mem_info mem_info;
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if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info,
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sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) !=
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sizeof(struct mshim_mem_info)) {
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pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure.\n");
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return -1;
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}
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if (mem_info.mem_ecc)
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csrow->edac_mode = EDAC_SECDED;
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else
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csrow->edac_mode = EDAC_NONE;
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switch (mem_info.mem_type) {
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case DDR2:
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csrow->mtype = MEM_DDR2;
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break;
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case DDR3:
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csrow->mtype = MEM_DDR3;
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break;
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default:
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return -1;
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}
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csrow->first_page = 0;
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csrow->nr_pages = mem_info.mem_size >> PAGE_SHIFT;
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csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
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csrow->grain = TILE_EDAC_ERROR_GRAIN;
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csrow->dtype = DEV_UNKNOWN;
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return 0;
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}
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static int __devinit tile_edac_mc_probe(struct platform_device *pdev)
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{
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char hv_file[32];
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int hv_devhdl;
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struct mem_ctl_info *mci;
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struct tile_edac_priv *priv;
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int rc;
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sprintf(hv_file, "mshim/%d", pdev->id);
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hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0);
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if (hv_devhdl < 0)
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return -EINVAL;
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/* A TILE MC has a single channel and one chip-select row. */
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mci = edac_mc_alloc(sizeof(struct tile_edac_priv),
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TILE_EDAC_NR_CSROWS, TILE_EDAC_NR_CHANS, pdev->id);
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if (mci == NULL)
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return -ENOMEM;
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priv = mci->pvt_info;
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priv->node = pdev->id;
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priv->hv_devhdl = hv_devhdl;
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mci->dev = &pdev->dev;
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mci->mtype_cap = MEM_FLAG_DDR2;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->mod_name = DRV_NAME;
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mci->ctl_name = "TILEPro_Memory_Controller";
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mci->dev_name = dev_name(&pdev->dev);
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mci->edac_check = tile_edac_check;
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/*
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* Initialize the MC control structure 'csrows' table
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* with the mapping and control information.
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*/
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if (tile_edac_init_csrows(mci)) {
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/* No csrows found. */
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mci->edac_cap = EDAC_FLAG_NONE;
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} else {
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mci->edac_cap = EDAC_FLAG_SECDED;
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}
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platform_set_drvdata(pdev, mci);
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/* Register with EDAC core */
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rc = edac_mc_add_mc(mci);
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if (rc) {
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dev_err(&pdev->dev, "failed to register with EDAC core\n");
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edac_mc_free(mci);
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return rc;
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}
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return 0;
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}
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static int __devexit tile_edac_mc_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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edac_mc_del_mc(&pdev->dev);
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if (mci)
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edac_mc_free(mci);
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return 0;
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}
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static struct platform_driver tile_edac_mc_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.probe = tile_edac_mc_probe,
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.remove = __devexit_p(tile_edac_mc_remove),
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};
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/*
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* Driver init routine.
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*/
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static int __init tile_edac_init(void)
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{
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char hv_file[32];
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struct platform_device *pdev;
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int i, err, num = 0;
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/* Only support POLL mode. */
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edac_op_state = EDAC_OPSTATE_POLL;
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err = platform_driver_register(&tile_edac_mc_driver);
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if (err)
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return err;
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for (i = 0; i < TILE_MAX_MSHIMS; i++) {
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/*
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* Not all memory controllers are configured such as in the
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* case of a simulator. So we register only those mshims
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* that are configured by the hypervisor.
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*/
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sprintf(hv_file, "mshim/%d", i);
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if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0)
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continue;
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pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0);
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if (IS_ERR(pdev))
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continue;
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mshim_pdev[i] = pdev;
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num++;
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}
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if (num == 0) {
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platform_driver_unregister(&tile_edac_mc_driver);
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return -ENODEV;
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}
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return 0;
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}
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/*
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* Driver cleanup routine.
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*/
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static void __exit tile_edac_exit(void)
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{
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int i;
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for (i = 0; i < TILE_MAX_MSHIMS; i++) {
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struct platform_device *pdev = mshim_pdev[i];
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if (!pdev)
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continue;
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platform_set_drvdata(pdev, NULL);
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platform_device_unregister(pdev);
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}
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platform_driver_unregister(&tile_edac_mc_driver);
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}
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module_init(tile_edac_init);
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module_exit(tile_edac_exit);
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