KVM: arm64: Don't set HCR_EL2.TVM when S2FWB is supported
On CPUs that support S2FWB (Armv8.4+), KVM configures the stage 2 page tables to override the memory attributes of memory accesses, regardless of the stage 1 page table configurations, and also when the stage 1 MMU is turned off. This results in all memory accesses to RAM being cacheable, including during early boot of the guest. On CPUs without this feature, memory accesses were non-cacheable during boot until the guest turned on the stage 1 MMU, and we had to detect when the guest turned on the MMU, such that we could invalidate all cache entries and ensure a consistent view of memory with the MMU turned on. When the guest turned on the caches, we would call stage2_flush_vm() from kvm_toggle_cache(). However, stage2_flush_vm() walks all the stage 2 tables, and calls __kvm_flush-dcache_pte, which on a system with S2FWB does ... absolutely nothing. We can avoid that whole song and dance, and simply not set TVM when creating a VM on a system that has S2FWB. Signed-off-by: Christoffer Dall <christoffer.dall@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20191028130541.30536-1-christoffer.dall@arm.com
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arch/arm64/include/asm
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@ -61,7 +61,6 @@
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* RW: 64bit by default, can be overridden for 32bit VMs
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* TAC: Trap ACTLR
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* TSC: Trap SMC
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* TVM: Trap VM ops (until M+C set in SCTLR_EL1)
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* TSW: Trap cache operations by set/way
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* TWE: Trap WFE
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* TWI: Trap WFI
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@ -74,7 +73,7 @@
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* SWIO: Turn set/way invalidates into set/way clean+invalidate
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*/
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#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
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HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
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HCR_BSU_IS | HCR_FB | HCR_TAC | \
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HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
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HCR_FMO | HCR_IMO)
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#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
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@ -53,8 +53,18 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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/* trap error record accesses */
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vcpu->arch.hcr_el2 |= HCR_TERR;
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}
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {
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vcpu->arch.hcr_el2 |= HCR_FWB;
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} else {
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/*
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* For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
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* get set in SCTLR_EL1 such that we can detect when the guest
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* MMU gets turned on and do the necessary cache maintenance
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* then.
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*/
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vcpu->arch.hcr_el2 |= HCR_TVM;
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}
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
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vcpu->arch.hcr_el2 &= ~HCR_RW;
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