PCI: ftpci100: Rename macro name collision
PCI_IOSIZE is defined in mach-loongson64/spaces.h, so change the name of the PCI_* macros in pci-ftpci100.c to use FTPCI_* so that they are more localized and won't conflict with other drivers or arches. ../drivers/pci/controller/pci-ftpci100.c:37: warning: "PCI_IOSIZE" redefined 37 | #define PCI_IOSIZE 0x00 | In file included from ../arch/mips/include/asm/addrspace.h:13, ... from ../drivers/pci/controller/pci-ftpci100.c:15: arch/mips/include/asm/mach-loongson64/spaces.h:11: note: this is the location of the previous definition 11 | #define PCI_IOSIZE SZ_16M Suggested-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210517234117.3660-1-rdunlap@infradead.org Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Krzysztof Wilczyński <kw@linux.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@vger.kernel.org
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@ -34,12 +34,12 @@
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* Special configuration registers directly in the first few words
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* in I/O space.
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*/
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#define PCI_IOSIZE 0x00
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#define PCI_PROT 0x04 /* AHB protection */
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#define PCI_CTRL 0x08 /* PCI control signal */
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#define PCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
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#define PCI_CONFIG 0x28 /* PCI configuration command register */
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#define PCI_DATA 0x2C
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#define FTPCI_IOSIZE 0x00
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#define FTPCI_PROT 0x04 /* AHB protection */
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#define FTPCI_CTRL 0x08 /* PCI control signal */
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#define FTPCI_SOFTRST 0x10 /* Soft reset counter and response error enable */
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#define FTPCI_CONFIG 0x28 /* PCI configuration command register */
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#define FTPCI_DATA 0x2C
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#define FARADAY_PCI_STATUS_CMD 0x04 /* Status and command */
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#define FARADAY_PCI_PMC 0x40 /* Power management control */
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@ -195,9 +195,9 @@ static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number,
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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p->base + PCI_CONFIG);
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p->base + FTPCI_CONFIG);
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*value = readl(p->base + PCI_DATA);
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*value = readl(p->base + FTPCI_DATA);
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if (size == 1)
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*value = (*value >> (8 * (config & 3))) & 0xFF;
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@ -230,17 +230,17 @@ static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number,
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PCI_CONF_FUNCTION(PCI_FUNC(fn)) |
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PCI_CONF_WHERE(config) |
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PCI_CONF_ENABLE,
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p->base + PCI_CONFIG);
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p->base + FTPCI_CONFIG);
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switch (size) {
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case 4:
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writel(value, p->base + PCI_DATA);
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writel(value, p->base + FTPCI_DATA);
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break;
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case 2:
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writew(value, p->base + PCI_DATA + (config & 3));
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writew(value, p->base + FTPCI_DATA + (config & 3));
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break;
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case 1:
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writeb(value, p->base + PCI_DATA + (config & 3));
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writeb(value, p->base + FTPCI_DATA + (config & 3));
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break;
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default:
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ret = PCIBIOS_BAD_REGISTER_NUMBER;
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@ -469,7 +469,7 @@ static int faraday_pci_probe(struct platform_device *pdev)
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if (!faraday_res_to_memcfg(io->start - win->offset,
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resource_size(io), &val)) {
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/* setup I/O space size */
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writel(val, p->base + PCI_IOSIZE);
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writel(val, p->base + FTPCI_IOSIZE);
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} else {
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dev_err(dev, "illegal IO mem size\n");
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return -EINVAL;
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@ -477,11 +477,11 @@ static int faraday_pci_probe(struct platform_device *pdev)
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}
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/* Setup hostbridge */
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val = readl(p->base + PCI_CTRL);
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val = readl(p->base + FTPCI_CTRL);
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val |= PCI_COMMAND_IO;
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val |= PCI_COMMAND_MEMORY;
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val |= PCI_COMMAND_MASTER;
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writel(val, p->base + PCI_CTRL);
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writel(val, p->base + FTPCI_CTRL);
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/* Mask and clear all interrupts */
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faraday_raw_pci_write_config(p, 0, 0, FARADAY_PCI_CTRL2 + 2, 2, 0xF000);
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if (variant->cascaded_irq) {
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