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drm/i915/icl: WaGAPZPriorityScheme 

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)
v5:
  - Rebased
  - C, not lisp (Chris)

References: HSDES#1405543622
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-4-git-send-email-oscar.mateo@intel.com
This commit is contained in:
Oscar Mateo 2018-05-08 14:29:25 -07:00 committed by Mika Kuoppala
parent d65dc3e40b
commit 5bcebe7670
2 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/i915/i915_reg.h
View File

@ -8250,8 +8250,9 @@ enum {
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4) #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6) #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
#define GEN8_GARBCNTL _MMIO(0xB004) #define GEN8_GARBCNTL _MMIO(0xB004)
#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7) #define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7)
#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22)
#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) #define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
#define DFR_DISABLE (1 << 9) #define DFR_DISABLE (1 << 9)

6
drivers/gpu/drm/i915/intel_workarounds.c
View File

@ -699,6 +699,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
/* WaPipelineFlushCoherentLines:icl */ /* WaPipelineFlushCoherentLines:icl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES); GEN8_LQSC_FLUSH_COHERENT_LINES);
/* Wa_1405543622:icl
* Formerly known as WaGAPZPriorityScheme
*/
I915_WRITE(GEN8_GARBCNTL, I915_READ(GEN8_GARBCNTL) |
GEN11_ARBITRATION_PRIO_ORDER_MASK);
} }
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)