[media] s5p-fimc: fix MSCTRL.FIFO_CTRL for performance enhancement
This patch fixes the value of FIFO_CTRL in MSCTRL. Main-scaler has the value to specify a basis FIFO control of input DMA. The description of FIFO_CTRL has been changed as below. 0 = FIFO Empty (Next burst transaction is possible when FIFO is empty) 1 = FIFO Full (Next burst transaction is possible except Full FIFO) Value '1' is recommended to enhance the FIMC operation performance. Reviewed-by: Jonghun Han <jonghun.han@samsung.com> Signed-off-by: Hyunwoong Kim <khw0178.kim@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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@ -437,7 +437,9 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
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| S5P_MSCTRL_C_INT_IN_MASK
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| S5P_MSCTRL_2P_IN_ORDER_MASK);
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cfg |= S5P_MSCTRL_IN_BURST_COUNT(4) | S5P_MSCTRL_INPUT_MEMORY;
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cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4)
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| S5P_MSCTRL_INPUT_MEMORY
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| S5P_MSCTRL_FIFO_CTRL_FULL);
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switch (frame->fmt->color) {
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case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
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@ -226,6 +226,7 @@
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#define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
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#define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
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#define S5P_MSCTRL_FLIP_180 (3 << 13)
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#define S5P_MSCTRL_FIFO_CTRL_FULL (1 << 12)
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#define S5P_MSCTRL_ORDER422_SHIFT 4
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#define S5P_MSCTRL_ORDER422_YCBYCR (0 << 4)
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#define S5P_MSCTRL_ORDER422_CBYCRY (1 << 4)
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