bcma: unify naming schema for clock functions
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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576d28a7c7
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5b5ac41447
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@ -48,8 +48,8 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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/* driver_chipcommon_pmu.c */
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
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u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
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u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
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u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
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#ifdef CONFIG_BCMA_SFLASH
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/* driver_chipcommon_sflash.c */
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@ -25,10 +25,10 @@ static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
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return value;
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}
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static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
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static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
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{
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if (cc->capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_alp_clock(cc);
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return bcma_pmu_get_alp_clock(cc);
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return 20000000;
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}
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@ -79,12 +79,12 @@ static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
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if (cc->capabilities & BCMA_CC_CAP_PMU) {
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
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return bcma_chipco_alp_clock(cc) / 4000;
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return bcma_chipco_get_alp_clock(cc) / 4000;
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else
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/* based on 32KHz ILP clock */
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return 32;
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} else {
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return bcma_chipco_alp_clock(cc) / 1000;
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return bcma_chipco_get_alp_clock(cc) / 1000;
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}
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}
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@ -236,7 +236,7 @@ void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
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struct bcma_serial_port *ports = cc->serial_ports;
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if (ccrev >= 11 && ccrev != 15) {
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baud_base = bcma_chipco_alp_clock(cc);
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baud_base = bcma_chipco_get_alp_clock(cc);
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if (ccrev >= 21) {
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/* Turn off UART clock before switching clocksource. */
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bcma_cc_write32(cc, BCMA_CC_CORECTL,
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@ -168,7 +168,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
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bcma_pmu_workarounds(cc);
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}
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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@ -196,7 +196,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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/* Find the output of the "m" pll divider given pll controls that start with
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* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
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*/
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static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, div, ndiv, p1, p2, fc;
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struct bcma_bus *bus = cc->core->bus;
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@ -225,14 +225,14 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
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/* Do calculation in Mhz */
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fc = bcma_pmu_alp_clock(cc) / 1000000;
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fc = bcma_pmu_get_alp_clock(cc) / 1000000;
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fc = (p1 * ndiv * fc) / p2;
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/* Return clock in Hertz */
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return (fc / div) * 1000000;
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}
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static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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{
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u32 tmp, ndiv, p1div, p2div;
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u32 clock;
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@ -263,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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}
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/* query bus clock frequency for PMU-enabled chipcommon */
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static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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@ -271,40 +271,42 @@ static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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case BCMA_CHIP_ID_BCM4716:
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case BCMA_CHIP_ID_BCM4748:
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case BCMA_CHIP_ID_BCM47162:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM5356:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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return bcma_pmu_pll_clock_bcm4706(cc,
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BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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case BCMA_CHIP_ID_BCM53572:
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return 75000000;
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default:
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bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
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}
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return BCMA_CC_PMU_HT_CLOCK;
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}
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/* query cpu clock frequency for PMU-enabled chipcommon */
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u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
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return 300000000;
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/* New PMUs can have different clock for bus and CPU */
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if (cc->pmu.rev >= 5) {
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u32 pll;
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock_bcm4706(cc,
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return bcma_pmu_pll_clock_bcm4706(cc,
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BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_CPU);
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case BCMA_CHIP_ID_BCM5356:
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@ -319,10 +321,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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break;
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}
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return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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}
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return bcma_pmu_get_clockcontrol(cc);
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/* On old PMUs CPU has the same clock as the bus */
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return bcma_pmu_get_bus_clock(cc);
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}
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static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
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@ -171,7 +171,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
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struct bcma_bus *bus = mcore->core->bus;
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if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_get_clockcpu(&bus->drv_cc);
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return bcma_pmu_get_cpu_clock(&bus->drv_cc);
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bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
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return 0;
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