Second Round of Renesas ARM-based SoC DT updates for v3.11
* Increased DT coverage for renesas-intc-irqpin by Guennadi Liakhovetski * Clean up of address format used in sh73a0 dtsi file by Guennadi Liakhovetski -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRwvf8AAoJENfPZGlqN0++fYkQAI/gPqZtrTvelEaGYkRRTpzC EBnVGatTBZM8AC3LVLM8UXWmZ0wYmS36e106K3QEelwmO6r0A/phaNG9zBHbe7um Bp8LZQoRyFqYuklBe3x8u+FvBM2f+NVmZFHQv/MTbuxLjcZe9o+JoXjFmHxOdTU3 9FXrdq5nJ0tFi+T/Td+zfJTXyHQTB8TQpt2ZiBcD0+hDC+t5ztTxdjFAQmWCsuCs M4MHSBxbUODUW7EIKX0EzOmJF0UQpDxNDSY4PvWt+y6M34Jv3W+xNSucgXBeBO9B jSIG2Opiiq4CW49Gp5fkNBPFqTgga8xk0ZSDFEQAiffmmQvPZGxeepspJqsVCTvS 1bbpya88S3Mjl0KXb/j+CrPCsd4ZgjcczRI79W/7LNZOq61ryH31Fg6R7RfOBFNU lOnu/PV8LRFHZG9H7hXEFKWvqIov3UXLNIQTsSEUa5awOxmmrJSIGroPhEN3bTM2 8wsiASxUsx3nWc/BK/iGwWq5VUNv397Nfc/+nb7I5DuBsdy1NFSUt2kOwxuJG4Jl vtYpyx45lLLJ3OwpWNewKcQCwXTPkaJvNrVkEI0Qb2o7otOmQq+xafIxop9pIaex pXzxAfXADXZUcJ4zMzMeS3t9eimIDoFimTlLSr1juLI/wJNVFBcbqe+HTWZk5fVO sJm8q/vbfgOAaDDXClvJ =cg7n -----END PGP SIGNATURE----- Merge tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt From Simon Horman: Second Round of Renesas ARM-based SoC DT updates for v3.11 * Increased DT coverage for renesas-intc-irqpin by Guennadi Liakhovetski * Clean up of address format used in sh73a0 dtsi file by Guennadi Liakhovetski * tag 'renesas-dt2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: shmobile: sh73a0: remove "0x" prefix from DT node names irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
5b520c94b3
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@ -0,0 +1,16 @@
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DT bindings for the R-/SH-Mobile irqpin controller
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Required properties:
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- compatible: has to be "renesas,intc-irqpin"
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
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if different from the default 4 bits
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- control-parent: disable and enable interrupts on the parent interrupt
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controller, needed for some broken implementations
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@ -119,7 +119,7 @@
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0 32 0x4>;
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};
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i2c0: i2c@0xe6820000 {
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i2c0: i2c@e6820000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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@ -131,7 +131,7 @@
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0 170 0x4>;
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};
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i2c1: i2c@0xe6822000 {
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i2c1: i2c@e6822000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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@ -143,7 +143,7 @@
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0 54 0x4>;
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};
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i2c2: i2c@0xe6824000 {
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i2c2: i2c@e6824000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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@ -155,7 +155,7 @@
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0 174 0x4>;
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};
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i2c3: i2c@0xe6826000 {
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i2c3: i2c@e6826000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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@ -167,7 +167,7 @@
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0 186 0x4>;
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};
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i2c4: i2c@0xe6828000 {
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i2c4: i2c@e6828000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,rmobile-iic";
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@ -179,7 +179,7 @@
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0 190 0x4>;
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};
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mmcif: mmcif@0x10010000 {
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mmcif: mmcif@e6bd0000 {
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compatible = "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupt-parent = <&gic>;
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@ -189,7 +189,7 @@
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status = "disabled";
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};
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sdhi0: sdhi@0xee100000 {
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sdhi0: sdhi@ee100000 {
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compatible = "renesas,r8a7740-sdhi";
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reg = <0xee100000 0x100>;
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interrupt-parent = <&gic>;
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@ -201,7 +201,7 @@
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};
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/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
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sdhi1: sdhi@0xee120000 {
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sdhi1: sdhi@ee120000 {
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compatible = "renesas,r8a7740-sdhi";
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reg = <0xee120000 0x100>;
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interrupt-parent = <&gic>;
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@ -212,7 +212,7 @@
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status = "disabled";
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};
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sdhi2: sdhi@0xee140000 {
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sdhi2: sdhi@ee140000 {
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compatible = "renesas,r8a7740-sdhi";
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reg = <0xee140000 0x100>;
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interrupt-parent = <&gic>;
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@ -18,6 +18,7 @@
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*/
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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@ -347,8 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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}
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/* deal with driver instance configuration */
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if (pdata)
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if (pdata) {
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memcpy(&p->config, pdata, sizeof(*pdata));
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} else {
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of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
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&p->config.sense_bitfield_width);
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p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
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"control-parent");
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}
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if (!p->config.sense_bitfield_width)
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p->config.sense_bitfield_width = 4; /* default to 4 bits */
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