Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6: xtensa: Add config files for Diamond 232L - Rev B processor variant xtensa: Fix io regions xtensa: Add support for the Sonic Ethernet device for the XT2000 board. xtensa: replace remaining __FUNCTION__ occurrences xtensa: use newer __SPIN_LOCK_UNLOCKED macro XTENSA: warn about including <asm/rwsem.h> directly.
This commit is contained in:
Linus Torvalds
commit
5a439c5657
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@ -64,7 +64,12 @@ choice
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default XTENSA_VARIANT_FSF
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config XTENSA_VARIANT_FSF
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bool "fsf"
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bool "fsf - default (not generic) configuration"
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config XTENSA_VARIANT_DC232B
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bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
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help
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This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
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endchoice
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config MMU
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@ -14,6 +14,7 @@
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# (Use VAR=<xtensa_config> to use another default compiler.)
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variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
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variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
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variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
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VARIANT = $(variant-y)
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@ -48,7 +48,7 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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if (irq >= NR_IRQS) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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__FUNCTION__, irq);
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__func__, irq);
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}
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irq_enter();
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@ -640,7 +640,7 @@ static int iss_net_configure(int index, char *init)
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*lp = ((struct iss_net_private) {
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.device_list = LIST_HEAD_INIT(lp->device_list),
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.opened_list = LIST_HEAD_INIT(lp->opened_list),
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.lock = SPIN_LOCK_UNLOCKED,
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.lock = __SPIN_LOCK_UNLOCKED(lp.lock),
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.dev = dev,
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.index = index,
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//.fd = -1,
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@ -464,6 +464,12 @@ config MIPS_JAZZ_SONIC
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This is the driver for the onboard card of MIPS Magnum 4000,
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Acer PICA, Olivetti M700-10 and a few other identical OEM systems.
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config XTENSA_XT2000_SONIC
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tristate "Xtensa XT2000 onboard SONIC Ethernet support"
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depends on XTENSA_PLATFORM_XT2000
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help
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This is the driver for the onboard card of the Xtensa XT2000 board.
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config MIPS_AU1X00_ENET
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bool "MIPS AU1000 Ethernet support"
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depends on SOC_AU1X00
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@ -227,6 +227,8 @@ pasemi_mac_driver-objs := pasemi_mac.o pasemi_mac_ethtool.o
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obj-$(CONFIG_MLX4_CORE) += mlx4/
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obj-$(CONFIG_ENC28J60) += enc28j60.o
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obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
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obj-$(CONFIG_MACB) += macb.o
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obj-$(CONFIG_ARM) += arm/
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@ -0,0 +1,319 @@
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/*
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* xtsonic.c
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*
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* (C) 2001 - 2007 Tensilica Inc.
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* Kevin Chea <kchea@yahoo.com>
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* Marc Gauthier <marc@linux-xtensa.org>
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* Chris Zankel <chris@zankel.net>
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*
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* (C) 1996,1998 by Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*
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* This driver is based on work from Andreas Busse, but most of
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* the code is rewritten.
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*
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* (C) 1995 by Andreas Busse (andy@waldorf-gmbh.de)
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*
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* A driver for the onboard Sonic ethernet controller on the XT2000.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/in.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/dma.h>
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static char xtsonic_string[] = "xtsonic";
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extern unsigned xtboard_nvram_valid(void);
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extern void xtboard_get_ether_addr(unsigned char *buf);
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#include "sonic.h"
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/*
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* According to the documentation for the Sonic ethernet controller,
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* EOBC should be 760 words (1520 bytes) for 32-bit applications, and,
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* as such, 2 words less than the buffer size. The value for RBSIZE
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* defined in sonic.h, however is only 1520.
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*
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* (Note that in 16-bit configurations, EOBC is 759 words (1518 bytes) and
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* RBSIZE 1520 bytes)
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*/
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#undef SONIC_RBSIZE
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#define SONIC_RBSIZE 1524
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/*
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* The chip provides 256 byte register space.
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*/
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#define SONIC_MEM_SIZE 0x100
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/*
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* Macros to access SONIC registers
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*/
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#define SONIC_READ(reg) \
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(0xffff & *((volatile unsigned int *)dev->base_addr+reg))
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#define SONIC_WRITE(reg,val) \
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*((volatile unsigned int *)dev->base_addr+reg) = val
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/* Use 0 for production, 1 for verification, and >2 for debug */
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#ifdef SONIC_DEBUG
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static unsigned int sonic_debug = SONIC_DEBUG;
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#else
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static unsigned int sonic_debug = 1;
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#endif
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/*
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* We cannot use station (ethernet) address prefixes to detect the
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* sonic controller since these are board manufacturer depended.
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* So we check for known Silicon Revision IDs instead.
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*/
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static unsigned short known_revisions[] =
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{
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0x101, /* SONIC 83934 */
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0xffff /* end of list */
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};
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static int xtsonic_open(struct net_device *dev)
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{
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if (request_irq(dev->irq,&sonic_interrupt,IRQF_DISABLED,"sonic",dev)) {
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printk(KERN_ERR "%s: unable to get IRQ %d.\n",
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dev->name, dev->irq);
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return -EAGAIN;
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}
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return sonic_open(dev);
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}
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static int xtsonic_close(struct net_device *dev)
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{
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int err;
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err = sonic_close(dev);
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free_irq(dev->irq, dev);
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return err;
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}
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static int __init sonic_probe1(struct net_device *dev)
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{
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static unsigned version_printed = 0;
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unsigned int silicon_revision;
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struct sonic_local *lp = netdev_priv(dev);
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unsigned int base_addr = dev->base_addr;
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int i;
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int err = 0;
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if (!request_mem_region(base_addr, 0x100, xtsonic_string))
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return -EBUSY;
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/*
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* get the Silicon Revision ID. If this is one of the known
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* one assume that we found a SONIC ethernet controller at
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* the expected location.
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*/
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silicon_revision = SONIC_READ(SONIC_SR);
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if (sonic_debug > 1)
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printk("SONIC Silicon Revision = 0x%04x\n",silicon_revision);
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i = 0;
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while ((known_revisions[i] != 0xffff) &&
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(known_revisions[i] != silicon_revision))
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i++;
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if (known_revisions[i] == 0xffff) {
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printk("SONIC ethernet controller not found (0x%4x)\n",
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silicon_revision);
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return -ENODEV;
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}
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if (sonic_debug && version_printed++ == 0)
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printk(version);
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/*
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* Put the sonic into software reset, then retrieve ethernet address.
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* Note: we are assuming that the boot-loader has initialized the cam.
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*/
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SONIC_WRITE(SONIC_CMD,SONIC_CR_RST);
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SONIC_WRITE(SONIC_DCR,
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SONIC_DCR_WC0|SONIC_DCR_DW|SONIC_DCR_LBR|SONIC_DCR_SBUS);
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SONIC_WRITE(SONIC_CEP,0);
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SONIC_WRITE(SONIC_IMR,0);
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SONIC_WRITE(SONIC_CMD,SONIC_CR_RST);
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SONIC_WRITE(SONIC_CEP,0);
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for (i=0; i<3; i++) {
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unsigned int val = SONIC_READ(SONIC_CAP0-i);
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dev->dev_addr[i*2] = val;
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dev->dev_addr[i*2+1] = val >> 8;
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}
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/* Initialize the device structure. */
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lp->dma_bitmode = SONIC_BITMODE32;
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/*
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* Allocate local private descriptor areas in uncached space.
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* The entire structure must be located within the same 64kb segment.
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* A simple way to ensure this is to allocate twice the
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* size of the structure -- given that the structure is
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* much less than 64 kB, at least one of the halves of
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* the allocated area will be contained entirely in 64 kB.
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* We also allocate extra space for a pointer to allow freeing
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* this structure later on (in xtsonic_cleanup_module()).
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*/
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lp->descriptors =
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dma_alloc_coherent(lp->device,
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SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
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&lp->descriptors_laddr, GFP_KERNEL);
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if (lp->descriptors == NULL) {
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printk(KERN_ERR "%s: couldn't alloc DMA memory for "
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" descriptors.\n", lp->device->bus_id);
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goto out;
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}
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lp->cda = lp->descriptors;
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lp->tda = lp->cda + (SIZEOF_SONIC_CDA
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* SONIC_BUS_SCALE(lp->dma_bitmode));
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lp->rda = lp->tda + (SIZEOF_SONIC_TD * SONIC_NUM_TDS
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* SONIC_BUS_SCALE(lp->dma_bitmode));
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lp->rra = lp->rda + (SIZEOF_SONIC_RD * SONIC_NUM_RDS
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* SONIC_BUS_SCALE(lp->dma_bitmode));
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/* get the virtual dma address */
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lp->cda_laddr = lp->descriptors_laddr;
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lp->tda_laddr = lp->cda_laddr + (SIZEOF_SONIC_CDA
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* SONIC_BUS_SCALE(lp->dma_bitmode));
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lp->rda_laddr = lp->tda_laddr + (SIZEOF_SONIC_TD * SONIC_NUM_TDS
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* SONIC_BUS_SCALE(lp->dma_bitmode));
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lp->rra_laddr = lp->rda_laddr + (SIZEOF_SONIC_RD * SONIC_NUM_RDS
|
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* SONIC_BUS_SCALE(lp->dma_bitmode));
|
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|
||||
dev->open = xtsonic_open;
|
||||
dev->stop = xtsonic_close;
|
||||
dev->hard_start_xmit = sonic_send_packet;
|
||||
dev->get_stats = sonic_get_stats;
|
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dev->set_multicast_list = &sonic_multicast_list;
|
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dev->tx_timeout = sonic_tx_timeout;
|
||||
dev->watchdog_timeo = TX_TIMEOUT;
|
||||
|
||||
/*
|
||||
* clear tally counter
|
||||
*/
|
||||
SONIC_WRITE(SONIC_CRCT,0xffff);
|
||||
SONIC_WRITE(SONIC_FAET,0xffff);
|
||||
SONIC_WRITE(SONIC_MPT,0xffff);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
release_region(dev->base_addr, SONIC_MEM_SIZE);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Probe for a SONIC ethernet controller on an XT2000 board.
|
||||
* Actually probing is superfluous but we're paranoid.
|
||||
*/
|
||||
|
||||
int __init xtsonic_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev;
|
||||
struct sonic_local *lp;
|
||||
struct resource *resmem, *resirq;
|
||||
int err = 0;
|
||||
|
||||
DECLARE_MAC_BUF(mac);
|
||||
|
||||
if ((resmem = platform_get_resource(pdev, IORESOURCE_MEM, 0)) == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
if ((resirq = platform_get_resource(pdev, IORESOURCE_IRQ, 0)) == NULL)
|
||||
return -ENODEV;
|
||||
|
||||
if ((dev = alloc_etherdev(sizeof(struct sonic_local))) == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
lp = netdev_priv(dev);
|
||||
lp->device = &pdev->dev;
|
||||
SET_NETDEV_DEV(dev, &pdev->dev);
|
||||
netdev_boot_setup_check(dev);
|
||||
|
||||
dev->base_addr = resmem->start;
|
||||
dev->irq = resirq->start;
|
||||
|
||||
if ((err = sonic_probe1(dev)))
|
||||
goto out;
|
||||
if ((err = register_netdev(dev)))
|
||||
goto out1;
|
||||
|
||||
printk("%s: SONIC ethernet @%08lx, MAC %s, IRQ %d\n", dev->name,
|
||||
dev->base_addr, print_mac(mac, dev->dev_addr), dev->irq);
|
||||
|
||||
return 0;
|
||||
|
||||
out1:
|
||||
release_region(dev->base_addr, SONIC_MEM_SIZE);
|
||||
out:
|
||||
free_netdev(dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
MODULE_DESCRIPTION("Xtensa XT2000 SONIC ethernet driver");
|
||||
module_param(sonic_debug, int, 0);
|
||||
MODULE_PARM_DESC(sonic_debug, "xtsonic debug level (1-4)");
|
||||
|
||||
#include "sonic.c"
|
||||
|
||||
static int __devexit xtsonic_device_remove (struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *dev = platform_get_drvdata(pdev);
|
||||
struct sonic_local *lp = netdev_priv(dev);
|
||||
|
||||
unregister_netdev(dev);
|
||||
dma_free_coherent(lp->device,
|
||||
SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
|
||||
lp->descriptors, lp->descriptors_laddr);
|
||||
release_region (dev->base_addr, SONIC_MEM_SIZE);
|
||||
free_netdev(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver xtsonic_driver = {
|
||||
.probe = xtsonic_probe,
|
||||
.remove = __devexit_p(xtsonic_device_remove),
|
||||
.driver = {
|
||||
.name = xtsonic_string,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init xtsonic_init(void)
|
||||
{
|
||||
return platform_driver_register(&xtsonic_driver);
|
||||
}
|
||||
|
||||
static void __exit xtsonic_cleanup(void)
|
||||
{
|
||||
platform_driver_unregister(&xtsonic_driver);
|
||||
}
|
||||
|
||||
module_init(xtsonic_init);
|
||||
module_exit(xtsonic_cleanup);
|
||||
|
|
@ -18,10 +18,12 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define XCHAL_KIO_CACHED_VADDR 0xf0000000
|
||||
#define XCHAL_KIO_BYPASS_VADDR 0xf8000000
|
||||
#define XCHAL_KIO_CACHED_VADDR 0xe0000000
|
||||
#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
|
||||
#define XCHAL_KIO_PADDR 0xf0000000
|
||||
#define XCHAL_KIO_SIZE 0x08000000
|
||||
#define XCHAL_KIO_SIZE 0x10000000
|
||||
|
||||
#define IOADDR(x) (XCHAL_KIO_BYPASS_VADDR + (x))
|
||||
|
||||
/*
|
||||
* swap functions to change byte order from little-endian to big-endian and
|
||||
|
|
|
|||
|
|
@ -13,6 +13,10 @@
|
|||
#ifndef _XTENSA_RWSEM_H
|
||||
#define _XTENSA_RWSEM_H
|
||||
|
||||
#ifndef _LINUX_RWSEM_H
|
||||
#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
|
||||
#endif
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/atomic.h>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,424 @@
|
|||
/*
|
||||
* Xtensa processor core configuration information.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 1999-2007 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* floating point pkg */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
|
||||
#define XCHAL_SW_VERSION 701001 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "dc232b" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)"
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 221001 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX2 1
|
||||
#define XCHAL_HW_REL_LX2_1 1
|
||||
#define XCHAL_HW_REL_LX2_1_1 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000100
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00001000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL2_NUM 8
|
||||
#define XCHAL_INTLEVEL4_NUM 12
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt vectors/levels.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0xD0000340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00000340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0xD00002C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000002C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* This header file contains assembly-language definitions (assembly
|
||||
* macros, etc.) for this specific Xtensa processor's TIE extensions
|
||||
* and options. It is customized to this Xtensa processor configuration.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1999-2007 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_ASM_H
|
||||
#define _XTENSA_CORE_TIE_ASM_H
|
||||
|
||||
/* Selection parameter values for save-area save/restore macros: */
|
||||
/* Option vs. TIE: */
|
||||
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
|
||||
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
|
||||
/* Whether used automatically by compiler: */
|
||||
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
|
||||
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
|
||||
/* ABI handling across function calls: */
|
||||
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
|
||||
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
|
||||
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
|
||||
/* Misc */
|
||||
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
|
||||
|
||||
|
||||
|
||||
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Save area ptr (clobbered): ptr (1 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
|
||||
*/
|
||||
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-8, 4, 4
|
||||
rsr \at1, ACCLO // MAC16 accumulator
|
||||
rsr \at2, ACCHI
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
s32i \at2, \ptr, .Lxchal_ofs_ + 4
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-16, 4, 4
|
||||
rsr \at1, M0 // MAC16 registers
|
||||
rsr \at2, M1
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
s32i \at2, \ptr, .Lxchal_ofs_ + 4
|
||||
rsr \at1, M2
|
||||
rsr \at2, M3
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
s32i \at2, \ptr, .Lxchal_ofs_ + 12
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
rsr \at1, SCOMPARE1 // conditional store option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
rur \at1, THREADPTR // threadptr option
|
||||
s32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_store
|
||||
|
||||
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
|
||||
* (not including zero-overhead loop registers).
|
||||
* Save area ptr (clobbered): ptr (1 byte aligned)
|
||||
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
|
||||
*/
|
||||
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
|
||||
xchal_sa_start \continue, \ofs
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-8, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
l32i \at2, \ptr, .Lxchal_ofs_ + 4
|
||||
wsr \at1, ACCLO // MAC16 accumulator
|
||||
wsr \at2, ACCHI
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 8
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-16, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
l32i \at2, \ptr, .Lxchal_ofs_ + 4
|
||||
wsr \at1, M0 // MAC16 registers
|
||||
wsr \at2, M1
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 8
|
||||
l32i \at2, \ptr, .Lxchal_ofs_ + 12
|
||||
wsr \at1, M2
|
||||
wsr \at2, M3
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 16
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wsr \at1, SCOMPARE1 // conditional store option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
|
||||
xchal_sa_align \ptr, 0, 1024-4, 4, 4
|
||||
l32i \at1, \ptr, .Lxchal_ofs_ + 0
|
||||
wur \at1, THREADPTR // threadptr option
|
||||
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
|
||||
.endif
|
||||
.endm // xchal_ncp_load
|
||||
|
||||
|
||||
|
||||
#define XCHAL_NCP_NUM_ATMPS 2
|
||||
|
||||
|
||||
#define XCHAL_SA_NUM_ATMPS 2
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_ASM_H*/
|
||||
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* This header file describes this specific Xtensa processor's TIE extensions
|
||||
* that extend basic Xtensa core functionality. It is customized to this
|
||||
* Xtensa processor configuration.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1999-2007 Tensilica Inc.
|
||||
*/
|
||||
|
||||
#ifndef _XTENSA_CORE_TIE_H
|
||||
#define _XTENSA_CORE_TIE_H
|
||||
|
||||
#define XCHAL_CP_NUM 1 /* number of coprocessors */
|
||||
#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
|
||||
#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
|
||||
#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
|
||||
|
||||
/* Basic parameters of each coprocessor: */
|
||||
#define XCHAL_CP7_NAME "XTIOP"
|
||||
#define XCHAL_CP7_IDENT XTIOP
|
||||
#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
|
||||
#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
|
||||
#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
|
||||
|
||||
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
|
||||
#define XCHAL_CP0_SA_SIZE 0
|
||||
#define XCHAL_CP0_SA_ALIGN 1
|
||||
#define XCHAL_CP1_SA_SIZE 0
|
||||
#define XCHAL_CP1_SA_ALIGN 1
|
||||
#define XCHAL_CP2_SA_SIZE 0
|
||||
#define XCHAL_CP2_SA_ALIGN 1
|
||||
#define XCHAL_CP3_SA_SIZE 0
|
||||
#define XCHAL_CP3_SA_ALIGN 1
|
||||
#define XCHAL_CP4_SA_SIZE 0
|
||||
#define XCHAL_CP4_SA_ALIGN 1
|
||||
#define XCHAL_CP5_SA_SIZE 0
|
||||
#define XCHAL_CP5_SA_ALIGN 1
|
||||
#define XCHAL_CP6_SA_SIZE 0
|
||||
#define XCHAL_CP6_SA_ALIGN 1
|
||||
|
||||
/* Save area for non-coprocessor optional and custom (TIE) state: */
|
||||
#define XCHAL_NCP_SA_SIZE 32
|
||||
#define XCHAL_NCP_SA_ALIGN 4
|
||||
|
||||
/* Total save area for optional and custom state (NCP + CPn): */
|
||||
#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
|
||||
#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
|
||||
|
||||
/*
|
||||
* Detailed contents of save areas.
|
||||
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
|
||||
* before expanding the XCHAL_xxx_SA_LIST() macros.
|
||||
*
|
||||
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
|
||||
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
|
||||
*
|
||||
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
|
||||
* ccused = set if used by compiler without special options or code
|
||||
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
|
||||
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
|
||||
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
|
||||
* name = lowercase reg name (no quotes)
|
||||
* galign = group byte alignment (power of 2) (galign >= align)
|
||||
* align = register byte alignment (power of 2)
|
||||
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
|
||||
* (not including any pad bytes required to galign this or next reg)
|
||||
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
|
||||
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
|
||||
* regnum = reg index in regfile, or special/TIE-user reg number
|
||||
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
|
||||
* gapsz = intervening bits, if bitsz bits not stored contiguously
|
||||
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
|
||||
* reset = register reset value (or 0 if undefined at reset)
|
||||
* x = reserved for future use (0 until then)
|
||||
*
|
||||
* To filter out certain registers, e.g. to expand only the non-global
|
||||
* registers used by the compiler, you can do something like this:
|
||||
*
|
||||
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
|
||||
* #define SELCC0(p...)
|
||||
* #define SELCC1(abikind,p...) SELAK##abikind(p)
|
||||
* #define SELAK0(p...) REG(p)
|
||||
* #define SELAK1(p...) REG(p)
|
||||
* #define SELAK2(p...)
|
||||
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
|
||||
* ...what you want to expand...
|
||||
*/
|
||||
|
||||
#define XCHAL_NCP_SA_NUM 8
|
||||
#define XCHAL_NCP_SA_LIST(s) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
|
||||
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
|
||||
|
||||
#define XCHAL_CP0_SA_NUM 0
|
||||
#define XCHAL_CP0_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP1_SA_NUM 0
|
||||
#define XCHAL_CP1_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP2_SA_NUM 0
|
||||
#define XCHAL_CP2_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP3_SA_NUM 0
|
||||
#define XCHAL_CP3_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP4_SA_NUM 0
|
||||
#define XCHAL_CP4_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP5_SA_NUM 0
|
||||
#define XCHAL_CP5_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP6_SA_NUM 0
|
||||
#define XCHAL_CP6_SA_LIST(s) /* empty */
|
||||
|
||||
#define XCHAL_CP7_SA_NUM 0
|
||||
#define XCHAL_CP7_SA_LIST(s) /* empty */
|
||||
|
||||
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
|
||||
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
|
||||
|
||||
#endif /*_XTENSA_CORE_TIE_H*/
|
||||
|
||||
Loading…
Reference in New Issue