powerpc/mm: Make MMU_FTR_RADIX a MMU family feature
MMU feature bits are defined such that we use the lower half to present MMU family features. Remove the strict split of half and also move Radix to a mmu family feature. Radix introduce a new MMU model and strictly speaking it is a new MMU family. This also free up bits which can be used for individual features later. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
a28e46f109
commit
5a25b6f527
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@ -24,7 +24,7 @@ struct mmu_psize_def {
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extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
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#ifdef CONFIG_PPC_RADIX_MMU
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#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)
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#define radix_enabled() mmu_has_feature(MMU_FTR_TYPE_RADIX)
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#else
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#define radix_enabled() (0)
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#endif
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@ -12,7 +12,7 @@
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*/
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/*
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* First half is MMU families
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* MMU families
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*/
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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@ -21,9 +21,13 @@
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
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/* Radix page table supported and enabled */
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#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
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/*
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* This is individual features
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* Individual features below.
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*/
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/*
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* We need to clear top 16bits of va (from the remaining 64 bits )in
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* tlbie* instructions
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@ -93,11 +97,6 @@
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*/
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#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
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/*
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* Radix page table available
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*/
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#define MMU_FTR_RADIX ASM_CONST(0x80000000)
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/* MMU feature bit sets for various CPUs */
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#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
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MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
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@ -131,7 +130,7 @@ enum {
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MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
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MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
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#ifdef CONFIG_PPC_RADIX_MMU
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MMU_FTR_RADIX |
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MMU_FTR_TYPE_RADIX |
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#endif
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0,
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};
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@ -532,7 +532,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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#ifdef CONFIG_PPC_STD_MMU_64
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BEGIN_MMU_FTR_SECTION
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b 2f
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
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BEGIN_FTR_SECTION
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clrrdi r6,r8,28 /* get its ESID */
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clrrdi r9,r1,28 /* get current sp ESID */
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@ -938,7 +938,7 @@ BEGIN_MMU_FTR_SECTION
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b do_hash_page /* Try to handle as hpte fault */
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MMU_FTR_SECTION_ELSE
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b handle_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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.align 7
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.globl h_data_storage_common
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@ -969,7 +969,7 @@ BEGIN_MMU_FTR_SECTION
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b do_hash_page /* Try to handle as hpte fault */
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MMU_FTR_SECTION_ELSE
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b handle_page_fault
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception)
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@ -1390,7 +1390,7 @@ slb_miss_realmode:
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#ifdef CONFIG_PPC_STD_MMU_64
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BEGIN_MMU_FTR_SECTION
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bl slb_allocate_realmode
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX)
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
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#endif
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/* All done -- return from exception. */
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@ -1404,7 +1404,7 @@ BEGIN_MMU_FTR_SECTION
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beq- 2f
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FTR_SECTION_ELSE
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b 2f
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
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ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
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.machine push
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.machine "power4"
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@ -570,7 +570,7 @@ common_exit:
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BEGIN_MMU_FTR_SECTION
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b no_segments
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
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/* Restore SLB from PACA */
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ld r8,PACA_SLBSHADOWPTR(r13)
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@ -170,7 +170,7 @@ static struct ibm_pa_feature {
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*/
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{CPU_FTR_TM_COMP, 0, 0,
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PPC_FEATURE2_HTM_COMP|PPC_FEATURE2_HTM_NOSC_COMP, 22, 0, 0},
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{0, MMU_FTR_RADIX, 0, 0, 40, 0, 0},
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{0, MMU_FTR_TYPE_RADIX, 0, 0, 40, 0, 0},
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};
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static void __init scan_features(unsigned long node, const unsigned char *ftrs,
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@ -425,7 +425,7 @@ void __init mmu_early_init_devtree(void)
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{
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/* Disable radix mode based on kernel command line. */
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if (disable_radix)
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cur_cpu_spec->mmu_features &= ~MMU_FTR_RADIX;
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cur_cpu_spec->mmu_features &= ~MMU_FTR_TYPE_RADIX;
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if (radix_enabled())
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radix__early_init_devtree();
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