ARM: dts: watchdog0 cannot reliably trigger reset

On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger
a reset to the CPU. The workaround would be to use watchdog1 instead.

Also for watchdog1, there is a dependency on the bootloader to enable the
boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the
control register in the clock manager module of Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

@@ -160,6 +160,6 @@
 	status = "okay";
 };
 
-&watchdog0 {
+&watchdog1 {
 	status = "okay";
 };